TW418548B - Light emitting diode assembly having integrated electrostatic discharge protection - Google Patents

Light emitting diode assembly having integrated electrostatic discharge protection Download PDF

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TW418548B
TW418548B TW088105388A TW88105388A TW418548B TW 418548 B TW418548 B TW 418548B TW 088105388 A TW088105388 A TW 088105388A TW 88105388 A TW88105388 A TW 88105388A TW 418548 B TW418548 B TW 418548B
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emitting diode
light
voltage
patent application
diode assembly
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TW088105388A
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William K Antle
Michael K Lam
James W Stewart
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Hewlett Packard Co
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40Details of LED load circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/20Responsive to malfunctions or to light source life; for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Description

4 185 43 五、發明説明(i ) 由於體積微小之故,高可靠性及低消耗功率之發光二 極體(LED)已取代許多光學信號系統中之白熾燈泡,例如 汽車尾燈以及交通號誌燈等。然而,現有之LED會由於靜 電放電(ESD)而遭致損壞,ESD會導致採用LED之信號系 統的性能劣化,並降低其可靠度。為了避免LED遭致ESD 的破壞,在組裝光學信號系統時會採行某些保護措施》這 些保護措施提高系統的製造成本,因為它們涉及設備接地 作業,例如工作平_台、地板、組裝附件、工具以及處理LED 之人員的接地處理。此外,保護措施無法完全防止靜電電 位的形成,而此電位會引起EDS而損壞LED « 根據本發明之較佳實施例,發光二極體總成與電力分 路元件結合,該元件可對LED提供過電壓保護,並防止LED 由於靜電放電(EDS)而受損。該電力分路元件在LED總成 中與LED並聯,並轉移來自LED之電流,且在跨越LED之 電壓超過臨限電壓時將跨越LED之電壓限制於夾箝電位上 ,以保護LED。 第1圖為具有本發明之電力分路元件之發光二極體總 成之示意圖; 第2圖為本發明第一較佳實施例之發光二極艘總成之 截面圖; 第3圈為本發明第二較佳實施例之發光二極體總成之 截面圖。 第1圖為具有本發明較佳實施例之電力分路元件12之 發光二極體總成10 »電力分路元件12與發光二極體Η並聯 本紙張度適用中國國家標準(CNS } Α4規格(210X297公釐) I Γ—--------裝---- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消费合作社印製 4 4Ί8548 A7 B7 五、發明説明(2 ) ’連接於發光二極體14之第一電氣接點15與第二電氣接點 17之間》當電氣接點之間的電壓v超過臨限電壓時,電力 分路裝置12,會將電壓V箝制於夾箝電壓並將電流Is由 LED 14導出’以限制LED 14之電力消耗。因此,電力分路 元件12可使LED14免於過載,例如,在不具備電力分路元 件12時由於會損壞LED之靜電放電(ESD)所形成之過載》 電力分路元件可由各種電壓箝位裝置構成,例如背對 背绂成的二極體16a、16b。當電壓夾箝裝置為稽納二極體 時,臨限電壓與夾箝電壓係為逆向偏壓之稽納二極體之一 的稽納電壓與順向偏壓與稽納二極體之一的順向導通電壓 加以決定。另一個例子為’背對背之二極體16a與16b為暫 態電壓消除(TVS)二極逋時,臨限電壓與夹箝電壓係由TVS 二極想之平衡(stand-off)電壓加以決定。 電力分路元件12之臨限電壓至少應相當於受保護之 LED14之最大操作電壓。例如’臨限電壓應至少當於led 14 之順向接面電壓,以利LED之正常操作。夾籍電壓必須要 小到可以限制LED 14中的電力消散•以便在所施加之電壓 V超過LED14之順向接面電壓時確保LED之可靠性。 第2圖為本發明第一較佳實施例之發光二極體總成丨〇a 之截面圖。LED14利用樹脂、焊接或其他方法附接於突出 於LED總成之封裝23之第一電極22a之第一安裝位置2U。 電力分路元件12附接於第一電極22a之第二安裝位置21b » 一對線接合片24a與24b、網孔接合片或其他連接裝置提供 LED 14之第一電氣‘接點15'電力分路元件12之第一接點12a 本纸張尺度適用t國國家橾準(CNS ) A4^ ( 210X297公釐) 1—:---^--.---裝,------訂-----^-I線 {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧射產局員工消费合作社印製 4 185 48 A7 B7 五、發明説明(3 ) ~ 與第二電極22b之間的電氣連接·» LED14之第二電氣接點17 舆電力分路元件12之第二接點12b之間的電路係經由第一 電極22a構成。電力分路元件π將LED 14之第一電氣接點15 與第二電氣接點17之間的電壓V限制於夾箝電位,並在施 加之電壓V超過臨限電壓時將電流is由LED14導出。 第3圖為本發明第二較佳實施例之發光二極體總成1〇b 之截面圖。在第二較佳實施例中,電力分路元件安裝於由 LED總成l〇b之封農23突出之第一電極22a之安裝位置2U 。LED 14以倒裝焊接法附接於電力分路元件12之上表面, 使LED 14之第一電氣接點15與電力分路元件丨2之第一接點 12a電氣連接,並使LED14之第二電氣接點17與電力分路 元件12之第二接點12b電氣連接••第一電氣接點丨5與第一 接點12a由線接合片24a或其他連接裝置耦接至第一電極 22a»第二電氣接點17與第二接點12b由線接合片24b或其 他連接裝置耦接至第二電極22b。電力分路元件π將LED14 之第一電氣接點15與第二電氣接點17之間的電壓v限制於 夹箝電位,並在施加之電壓V超過臨限電壓時將電流13由 LED14導出。 僅管以上已就本發明較佳實施例作詳細說明,吾人應 瞭解,熟習此技藝之人士可在不棒離下列申請專利範圍之 範疇的前提下對本發明實施例作各種修改。 本紙張尺度逋用中國國家標準(CNS ) A4规格(210X297公釐) !|!丨I--.---裝-------訂------丨線 (請先閎讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Λ 185 Ao a? Β7 五、發明説明(4 ) 元件標號對照 10…發光二極體總成 l〇b…發光二極體總成 12…電力分路元件 12a…第一接點 12b"_第二接點 14…發光二極體 15···第一接點 16a·*·二極體 16b…二極體 17…第二接點 21a…第一安裝位置 22a…第一電極 23…封裝 2 4 a…線接合片 24b…線接合片 —ίΊ-----;---裝-------訂-----^——線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐)

Claims (1)

  1. 4 185 48 C8 ___ D8 六'申請專利範圍 L 一種發光二極體總成,包含: 發光二極體’具有第一電氣接點與第二電氣接點 » 封裝’具有耦接至第一電氣接點之第一電極與耗 接至第一電氣接點之第二電極,其中第一電極舆第二 電極電以接收外壓; 電力分壓元件,耦接至第一電氣接點與第二電氣 接點,用以在外壓超過臨限電壓時將電流由發光二極 體導出。 2. 如申請專利範圍第1項之發光二極體總成,其中該電力 分路元件包含背對背結構的電壓夾箝裝置。 3. 如_請專利範圍第2項之發光二極體總成,其中該背對 背結構之電麼失箱裝置包含至少一個稽納二極趙。 4. 如申請專利範圍第2項之發光二極體總成,其中該背對 背結構之電壓夾箝裝置包含至少一個暫態電壓消除器 〇 經濟部智慧財產局員工消費合作社印製 I I n l· *1 J ^1 fa i I I I I (請先閱讀背面之注意事項再填寫本頁) -線· 5. 如申請專利範圍第1項之發光二極體總成,其中該第— 電極具有配接發光二極體之第一安裝位置與配接電力 分路元件之第二安裝位置,而第一電極構成第二電氣 接點舆電力分路元件之間的耦接。 6. 如申請專利範圍第5項之發光二極體總成,其中該電力 分路元件包含背對背結構的電壓夾箝裝置》 7. 如申請專利範圍第5項之發光二極體總成,其中該背對 背結構之電壓夾箝裝置包含至少一個稽納二極體。 私紙張又度適用中國國家標準(CNS)A4規格(210 X 297公釐 ASB8C8D8 /、、申請專利範圍 8. 如申請專利範圍第5項之發光二極體總成,其中該背對 背結構之電壓夾箝裝置包含至少一個暫態電壓消除器 〇 9. 如申請專利範圍第1項之發光二極體總成,其中該電力 分路元件之底表面以倒裝片焊接法附接於第一電極, 而頂表面具有第一與第二接點,其中該發光二極體之 第一電氣接點耦接至第一接點,而該發光二極體之第 二電氣接點耦接至第二接點。 10. 如申請專利範圍第9項之發光二極邀總成,其中該電力 分路元件包含背對背結構的電壓夾箝裝置。 11_如申請專利範圍第9項之發光二極體總成,其中該背對 背結構之電壓夾箝裝置包含至少一個稽納二極體。 12.如申請專利範圍第9項之發光二極體總成,其中該背對 背結構之電壓夾箝裝置包含至少一個暫態電壓消除器 — !114._丨_-----^-------訂 ---------線--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製
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KR20000017513A (ko) 2000-03-25
US5914501A (en) 1999-06-22

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