經濟部中央標準局員工消費合作杜印袈 4^353 - 五、發明説明（1 ) 發明之技術領磁 本發明係關於一種電子電路’尤其是關於一種能提供輸 電壓出高於正電源電壓之電子電路。諒電路能用來將其輸出 笔壓供給電晶鱧之—控制端以確保其完全之開關性能。 發明背景 類比開關一般包括場效應電晶體（FETs)。正如所乾要的 ’爲保證該元件足以勝任之性能’這些p^Ts之控制電壓必 需達到使這些電晶體完全導通或截止。舉例來説，當電晶 體之源極保持高於零之電位時’在閘極加正電極源電壓可 能還不夠’因爲此時閘-源電壓Vgs可能還不足以大到保 證電晶體完全導通之程度。這在低電壓供電之電路中是一 個特殊問題’例如因爲企盼用電池來供電且該工作條件下 電源之消耗又很重要。在這類場合，所謂電壓提昇電路或 充電激勵電路就是用來產生一個高於正電源之電签，施加 S %壓到電晶體之閘極以保證足夠南之挪-源電壓。 美國專利第5,0 7 5,5 72號揭示了一種充電激勵電路，包 括一個用兩個場效應電晶體之反相器，其輪出接到電容哭 之—端’電容器、之另一端則通過另一F E T之源-汲通道接 地0 發明概要& , 本發明尋求提供一種電壓提昇電路，它能避免先前技蔽 中所伴有的一些問題’在該電路+，在較佳具體實例中， 能避免蔣雜訊帶入系統，對系統之電流損耗增加不大，而 在有效増加可用電壓時只附加極少額外元件。 -4- 本纸張尺度適用中國國家標準（CNS ) a4規格（210X297公釐 -1Γ-----;---„-----裝-- (請先閔讀背面之注意事項再填寫本頁)The Consumer Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China Du Yinji 4 ^ 353-V. Description of the Invention (1) The Technical Field of the Invention The present invention relates to an electronic circuit, especially to a device that can provide an output voltage higher than a positive power supply voltage. electronic circuit. The circuit can be used to supply its output pen pressure to the transistor-control terminal to ensure its full switching performance. BACKGROUND OF THE INVENTION Analog switches typically include field effect transistors (FETs). As necessary, 'to ensure the adequate performance of the device', the control voltage of these p ^ Ts must be such that the transistors are completely turned on or off. For example, when the source of the transistor is maintained at a potential higher than zero, 'it may not be enough to apply a positive electrode source voltage at the gate', because the gate-source voltage Vgs may not be large enough to ensure that the transistor is fully turned on. degree. This is a special problem in low voltage power supply circuits', for example, because the battery is expected to be used for power supply and the power consumption under this working condition is important. In such cases, the so-called voltage boosting circuit or charging excitation circuit is used to generate an electrical tag higher than the positive power supply, and applying S% voltage to the gate of the transistor to ensure sufficient source voltage. U.S. Patent No. 5,0 7 5,5 72 discloses a charging excitation circuit, which includes an inverter using two field-effect transistors, which are connected to a capacitor, a capacitor, and the other terminal. The source-drain channel is grounded through another FET. Summary of the Invention & The present invention seeks to provide a voltage boosting circuit which can avoid some of the problems associated with the previous technique 'in this circuit +, in a preferred specific example It can avoid the introduction of Jiang Noise into the system, and the current loss of the system is not increased, and only a few additional components are added when the available voltage is effectively increased. -4- This paper size applies to Chinese National Standard (CNS) a4 specification (210X297 mm-1Γ -----; --- „----- packing-(please read the precautions on the back first) (Fill in this page)
、1T 膝 417353 A7 經濟部中央標準局男工消费合作社印製 B7五、發明説明（2 ) 依照本發明，提供之電壓提昇開關驅動器包括—個有輸 4 出和輸入之反相.器，最好用CMOS反相器。反相器輸出經 由電容器接一電晶體之一端，電晶體之另一端施加特定電 壓，該電晶體最好用MOS型電晶體。反相器之輸入連接到 MOS電晶體之閘極。在電晶體及電容器連接處之電壓可用 作爲輸出。 選擇適當元件，能使反相If輸入低電位時保持輸出電壓 等於特定電壓，而在反相器輸入高電位時，其輸出能大體 上等於特定電壓和正電源電壓之和。 這樣，在較佳具體實例中，輸出電壓高出反相器輸入電 壓一個特定値。例如，若特定電壓加在作爲類比開關之 MOS電晶體之源極，就屬這種應用。開關驅動器之輸出電 壓即可施加到電晶體之閘極以保證其閘-源電壓幾乎跨越 從零到正電源電壓之整個區間。 · 附圖簡單説明 圖1爲本發明較佳具體實施例之電路示意圖。 較佳具體實施例之詳細説明 圖1顯示了本發明具體實施例之開關驅動器2，其連接至負 載元件4。 …_ 在本例情況下，負載元件4爲一增強型N通道MOS電晶 體6，該電晶體之源極及汲極分別接端點10和12。 這樣的電路通常是所希望的：在輸出端12，用於開關之 電路輸出電壓與輸入端13處之輸入脈沖同相位。然而，如 果正電源電壓Vdd相對地低，例如由於希望供電電池之數 -5- 本紙張尺度適用中國國家標準（CNS )八扣見格（2ί0Χ297公釐） ----^---^---i------IT------;.妹 (請先閱讀背面之注意事項再填寫本頁) 417353 經濟部中央樣準局負工消費合作社印裝 A7 B7五、發明説明（3 ) 量降到最少，存在於開關4之輸入端10上正電壓Vb可能意 味著簡單地將正電源電壓Vdd加到NMOS電晶體6之閘極端 14是不夠的。如果（Vdd- Vb)不夠高，這將不足以實現完全 開關。 舉例來説，若電晶體6處於信號通路中，可設一正偏壓 使正負信號落在其正偏置電壓週圍。 因此，提供一開關驅動電亨2以提昇正電源電壓Vdd使閘 極端14達到一個足夠之電壓。 特別是，開關驅動電路2包括一反相器16，包含一 PMOS 電晶體18及NMOS電晶體20，連接於正電源電壓Vdd及負電 源電壓Vss之間，其輸入端13接電晶體18，20之閘極，反相 器16之輸出端22接電容器24之一端，電容器之另一端接 NMOS電晶體6之閘極端14。開關驅動電路2還包括另一增 強型NMOS電晶體26，其汲極接閘極14，而其閘極接電跆輸 入13。 重要的是電晶體26之源極保持於正偏電壓。在圖1電路 例中，電晶體26之源極直接地接在開關輸入端10也即電壓 Vb(例如，該電壓可在1.25V左右）。然而，如上所述，電 壓Vb可用作爲正偏置電壓Vb，信號於其上施加到電晶體6 。該等信號之大小必需低於電晶體臨界電壓以保證電路之 正確運作。例如，當Vb= 1.25V時，加在開關輸入端10之電 壓可約在0.95-1.55V範園内3在此場合，-電壓Vb自身仍可 加在電晶體26之源極上= 圖1電路運作中，當輸入節點13之脈衝信號爲高電位， -6 - 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝. 訂 417353 A-7 經濟部中_準局員工消作社印製 B7 五、發明説明（4 ) 即等於Vdd時，反相器16動作使其輸出端22爲低電位，即等 , 於Vss。另外，輸入節點13之高電位加到了電晶體26之閘極 ，使電晶體導通，並使閘端14之電壓箝位到Vb。於是，電 容器24兩端之電壓爲上述兩個電壓値之差，·即（Vb- Vss)。 在輸入電壓的下半周，當節點13處輸入爲Vss時，反相 器16輸出反相電壓，在反相器輸出端22，其電壓爲Vdd。更 明確地説，低電位加到電晶_ 18之閘極.使電晶體導通，反 相器輸出電壓箝位於電路正電源幹線電壓。電容器24兩端 之電壓則由先前存在其上之電荷分享而定。 若電容器24兩端電壓爲（Vb- Vss)，則其上之電荷爲 C ( Vb- Vss)，其中C爲電容器24之電容器。 當輸入節點13處之電壓變爲低電位時，電晶體26截止， 閘端1 4浮動。電容器24上之電荷因之與負載，此處爲開關 4，上之電荷再分配。然而，如果負載之電容量比電釭器 24之電容量C小很多時，只有一小部份電荷轉移到負載上 ，所以電容器24上之電荷，也即電容器24端之電壓，相對 地保持爲常數。 在那種情況下，反相器輸出端22之電壓上昇到Vdd，閘 端14之電壓上昇到逼近（V4d- Vss+ Vb)，這當然比Vb高出電 源電壓之差値。 ; 此效果爲電晶體6之閘-源電壓Vgs接近等於整個電源電 壓（即，電路上正、負電源幹線電壓之差），所以這足以保 證元件之完全開關性能。 上面描述之電路能用N-井CMOS製程將其製造在個積 (請先聞讀背面之注意事項再填寫本頁) •裝 訂 線 本紙張尺度適用中國國家標準（CNS ) Α4规格（210X 297公釐） 417353 ' Μ ___________Β7 五、發明説明（5 ) 體電路中。可以意識到，用PMOS電晶體來代替上述實例 中描述過的NM0S電晶體，反之也然，並將電源電壓之極 性倒過來，則井CMOS製程也可對等應用。 此外’雖然在這裡描述之電路由CMOS元件製造，可以 意識到，用任何P型場效應電晶體或PNP電晶體組合代替所 描述的PMOS元件及用N型場效應電晶體或NPN電晶體組，合 來代替NOMS元件，則雙載子型3雙載子CM〇s型可被應用。 由此’在上述本發明之具體實例中，在閘端14處可得之 增加電壓與節點丨3處之輸入電壓同相，且來自電容耦合， 所以與驅動電路2有關之直流功率損耗不存在。 因之本電路提供了一樓取得高於電路電源電壓之有利方 法° (请先閱讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局員工消費合作社印製 本认張尺度適用中國國家標準（CNS ) A4規格（210/297公釐）1T knee 417353 A7 printed B7 printed by the male workers' consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) According to the present invention, the voltage boost switch driver provided includes an inverter with 4 outputs and inputs. Easy to use CMOS inverter. The output of the inverter is connected to one end of a transistor through a capacitor, and a specific voltage is applied to the other end of the transistor. The transistor is preferably a MOS type transistor. The input of the inverter is connected to the gate of the MOS transistor. The voltage at the transistor and capacitor connections can be used as an output. Selecting proper components can keep the output voltage equal to a specific voltage when the inverting If input is low, and its output can be roughly equal to the sum of the specific voltage and the positive power supply voltage when the inverter inputs a high potential. Thus, in the preferred embodiment, the output voltage is higher than the inverter input voltage by a certain value. For example, if a specific voltage is applied to the source of a MOS transistor as an analog switch, this is the application. The output voltage of the switching driver can be applied to the gate of the transistor to ensure that its gate-source voltage spans almost the entire range from zero to positive supply voltage. Brief description of the drawings Figure 1 is a schematic circuit diagram of a preferred embodiment of the present invention. Detailed Description of the Preferred Embodiment FIG. 1 shows a switch driver 2 according to a specific embodiment of the present invention, which is connected to a load element 4. … _ In the case of this example, the load element 4 is an enhanced N-channel MOS transistor 6 whose source and drain are connected to terminals 10 and 12, respectively. Such a circuit is generally desirable: at the output terminal 12, the output voltage of the circuit for switching is in phase with the input pulse at the input terminal 13. However, if the positive power supply voltage Vdd is relatively low, for example, because of the number of batteries that are expected to supply power -5- This paper size applies the Chinese National Standard (CNS) Bakouge (2ί0 × 297 mm) ---- ^ --- ^- --i ------ IT ------ ;. mei (please read the notes on the back before filling out this page) 417353 Printed A7 B7 by the Consumer Procurement Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs Explanation (3) The quantity is reduced to a minimum. The positive voltage Vb existing on the input terminal 10 of the switch 4 may mean that simply adding the positive power supply voltage Vdd to the gate terminal 14 of the NMOS transistor 6 is not enough. If (Vdd-Vb) is not high enough, this will not be sufficient to achieve full switching. For example, if the transistor 6 is in the signal path, a positive bias voltage can be set so that the positive and negative signals fall around its positive bias voltage. Therefore, a switch is provided to drive the battery 2 to boost the positive supply voltage Vdd to bring the gate terminal 14 to a sufficient voltage. In particular, the switch driving circuit 2 includes an inverter 16 including a PMOS transistor 18 and an NMOS transistor 20, which are connected between the positive power supply voltage Vdd and the negative power supply voltage Vss, and its input terminal 13 is connected to the transistors 18, 20 The gate 22 of the inverter 16 is connected to one terminal of the capacitor 24, and the other terminal of the capacitor is connected to the gate terminal 14 of the NMOS transistor 6. The switch driving circuit 2 also includes another enhanced NMOS transistor 26, whose drain is connected to the gate 14 and its gate is connected to the power input 13. It is important that the source of the transistor 26 is maintained at a forward bias voltage. In the circuit example of FIG. 1, the source of the transistor 26 is directly connected to the switch input terminal 10, that is, the voltage Vb (for example, the voltage may be about 1.25V). However, as described above, the voltage Vb can be used as the positive bias voltage Vb, on which a signal is applied to the transistor 6. The magnitude of these signals must be lower than the threshold voltage of the transistor to ensure the correct operation of the circuit. For example, when Vb = 1.25V, the voltage applied to the input 10 of the switch can be within the range of 0.95-1.55V. In this case,-the voltage Vb itself can still be applied to the source of the transistor 26 = Figure 1 circuit operation When the pulse signal of input node 13 is high potential, -6-This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page)-Install. Order 417353 A-7 in the Ministry of Economic Affairs _ printed by B7 of the Consumer Bureau of the Bureau of the Bureau of the People's Republic of China 5. Description of the Invention (4) When Vdd is equal to Vdd, the inverter 16 operates to make its output terminal 22 low, that is, equal to Vss. In addition, the high potential of the input node 13 is applied to the gate of the transistor 26, which turns on the transistor and clamps the voltage of the gate 14 to Vb. Therefore, the voltage across the capacitor 24 is the difference between the above two voltages, i.e., (Vb-Vss). In the second half of the input voltage, when the input at node 13 is Vss, the inverter 16 outputs an inverted voltage, and at the inverter output terminal 22, the voltage is Vdd. More specifically, a low potential is applied to the gate of transistor_18. The transistor is turned on, and the output voltage of the inverter is clamped to the positive mains voltage of the circuit. The voltage across capacitor 24 is determined by the charge sharing previously existing on it. If the voltage across capacitor 24 is (Vb-Vss), the charge on it is C (Vb-Vss), where C is the capacitor of capacitor 24. When the voltage at the input node 13 becomes a low potential, the transistor 26 is turned off, and the gate terminal 14 is floated. The charge on the capacitor 24 is related to the load, here is the switch 4, and the charge on the capacitor is redistributed. However, if the capacitance of the load is much smaller than the capacitance C of the capacitor 24, only a small portion of the charge is transferred to the load, so the charge on the capacitor 24, that is, the voltage at the capacitor 24, is relatively maintained as constant. In that case, the voltage at the output terminal 22 of the inverter rises to Vdd, and the voltage at the gate terminal 14 approaches (V4d-Vss + Vb), which is of course higher than Vb by the difference in power supply voltage. This effect is that the gate-source voltage Vgs of transistor 6 is nearly equal to the entire power supply voltage (that is, the difference between the positive and negative mains voltages on the circuit), so this is sufficient to ensure the full switching performance of the component. The circuit described above can be manufactured in a single product using the N-well CMOS process (please read the precautions on the back before filling out this page) • The binding paper size applies the Chinese National Standard (CNS) Α4 specification (210X 297 male) (Centi) 417353 'M ___________ Β7 5. Description of the invention (5) in the body circuit. It can be realized that the PMOS transistor is used to replace the NMOS transistor described in the above example, and vice versa, and the polarity of the power supply voltage is reversed, and the well CMOS process can also be applied equivalently. In addition, 'Although the circuit described here is made of a CMOS element, it can be appreciated that any P-type field effect transistor or combination of PNP transistors is used in place of the described PMOS element and an N-type field effect transistor or NPN transistor group, Combined instead of the NOMS element, the three-carrier 3 CM0s type can be used. Therefore, in the above-mentioned specific example of the present invention, the increase voltage available at the gate terminal 14 is in phase with the input voltage at the node 3, and comes from the capacitive coupling, so the DC power loss related to the driving circuit 2 does not exist. Therefore, this circuit provides a favorable method for obtaining a voltage higher than the power supply of the circuit on the first floor. (Please read the precautions on the back before filling this page.) National Standard (CNS) A4 Specification (210/297 mm)