JP2803463B2 - Transfer gate transistor gate booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate potential boosting circuit for a transfer gate transistor.

[0002]

2. Description of the Related Art As shown in FIG. 5, a gate booster circuit section 16b of a conventional transfer gate transistor receives an analog input voltage vi to output an analog output voltage vo, and has a gate connected to a transfer gate node N2. A transfer gate transistor 12 shown by a bold line having an N-channel MOS transistor 2
When the transfer gate selection voltage SEL is input, the node N
3, a gate selection / voltage protection circuit 14b for supplying an inversion signal S3R to the transistor gate 3, and a charge-up circuit 15 for receiving the selection signal SEL and the inversion signal S3R and supplying the node voltage S2 charged up to the transistor gate N2. Having.

The gate selection / voltage protection circuit 14b uses an N-channel MOS field effect transistor (hereinafter abbreviated as N-channel transistor) connected between the transfer gate node N2 and the ground GND using the transfer gate selection voltage SEL as a gate input voltage. 4, an inverter IN that supplies an inverted voltage S3R of the selection voltage SEL to a node N3 to which the charge-up input voltage S3 is input, a power supply voltage VD to a drain, and a source and a gate both connected to a transfer gate node N2. And a clamp diode D of a MOS transistor.

The charge-up circuit 15 has a gate node N
N-channel transistor 5 having a drain / source inserted between node 2 and node N3 and a gate connected to node 5
And a delay circuit 8 which receives the selection voltage SEL and supplies the delay voltage S8 to the node N8 with a delay time T2, and a drain / source inserted between the node N8 and the node N5 to supply the power supply voltage VD to the gate. And the threshold VTZ
Is set to approximately 0V, an N-channel transistor Z, a second delay circuit 9 which receives a delay voltage S8 and supplies a delay voltage S9 of a delay time T3 to a node N9, and a selection voltage S
It has a NOR gate 10 that inputs the EL and the delay voltage S9 and outputs a NOR voltage to a node N10, and a capacitive element C inserted between the node N10 and the gate node N2.

FIG. 6 shows the timing of each signal to explain the operation of the circuit of FIG. A period T1 including the time point t1 is a non-selection period of the transfer gate transistor 12, and the gate node voltage S2 is at the GND level because the N-channel transistor 4 is on.

In this period, the node voltage S5 is higher than the power supply voltage VD by the threshold voltage VTZ of the N-channel transistor Z.
The transistor Z is in a cut-off state because the level is only lower (VD-VTZ).

Next, when the selection voltage SEL changes from "H" (VD) to "L" (GND) at a time point t2 when the period T2 starts, the inverted voltage S3 of the inverter circuit IN changes from "L" to "H". At the same time, the voltage S at the gate node N5 is changed by the gate-drain capacitance CD and the gate-source capacitance CS of the N-channel transistor 5 indicated by the dotted lines.
5 is [(VD−VTZ) + VD] = (2 · VD−VT)
Z), and the gate node voltage S2 is charged to VD.

Next, after the selection time T2, when the delay element S8 output from the delay circuit 8 changes from "H" to "L" at a time point t3 at which the period T3 starts, the node voltage S5 becomes GND.
Level, so that the N-channel transistor 5 is cut off.

Subsequently, the NOR voltage S10 changes from "L" to "H", and the gate node voltage S2 is charged up to the level of 2.multidot.VD via the capacitive element C.

However, the gate node voltage S2 is the sum of the power supply voltage VD and the threshold value VTD of the clamp diode D in which a MOS transistor is diode-connected (VD +
VTD) to prevent the voltage breakdown of the gate insulating film of the transistor 2.

In this case, when the power supply voltage VD is 6 V, the threshold voltage VTD of the clamp diode D is 1 V, and the analog input and output voltages vi and vo are zero, that is, the drain and source voltages are zero, the gate node voltage S2 becomes Clamped to 7V.

[0012]

In this conventional gate booster circuit of a transfer gate transistor, the transfer gate node voltage of the transfer gate transistor is higher than the power supply voltage. -When a large voltage stress is applied to the vicinity of the drain and the source of the gate oxide film of the transistor and exceeds the gate maximum rated voltage VGM, there is a problem that the gate oxide film is broken.

[0013]

According to the present invention, a gate booster circuit for a transfer gate transistor receives a transfer gate selection voltage for setting a power supply voltage and a ground potential to a high or low level, and outputs a charge-up input voltage. A selection / voltage protection circuit, a transistor switch and a capacitor connected to a transfer gate node connected to the gate of an N-channel MOS field effect transistor constituting the transfer gate transistor, and a charge-up input voltage connected to a charge-up input node. , And a boosted voltage obtained by adding a high level of the transfer gate selection voltage to the transfer gate node, the gate boosting circuit of the transfer gate transistor, Get An N-channel MOS field-effect transistor having a drain connected to the transfer gate node and having a source grounded, and inserted between an analog input voltage input terminal of the transfer gate transistor and a ground potential point. It comprises a second transfer gate transistor, a series circuit of the charge-up input node and an N-channel MOS field-effect transistor for pull-down.

Further, the gate boosting circuit of the transfer gate transistor according to the present invention is a gate selection / voltage protection circuit for inputting a transfer gate selection voltage for setting a power supply voltage and a ground potential to high and low levels and outputting a charge-up input voltage. A transistor switch and a capacitive element are connected to a transfer gate node connected to a gate of an N-channel MOS field effect transistor forming a transfer gate transistor, and the charge-up input voltage is input to a charge-up input node. In a gate boosting circuit of a transfer gate transistor in which a boosted voltage obtained by adding a high level of the transfer gate selection voltage is output to the transfer gate node, the gate selection and voltage protection circuit may be configured such that a gate is connected to the transfer gate selection voltage. And an N-channel MOS field-effect transistor whose drain is connected to the transfer gate node and whose source is grounded, and a gate inserted between a ground potential point of the power supply terminal and an analog of the transfer gate transistor An N-channel MOS field-effect transistor having a low threshold connected to an input voltage input terminal, a second transfer gate transistor, a series circuit of the charge-up input node and an N-channel MOS field-effect transistor for pull-down are provided. It is configured.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. The gate booster circuit section 16 of the present embodiment has a gate selection circuit / voltage protection circuit 14 in which the gate selection / voltage protection circuit 16b of FIG. 5 is partially modified, and the transfer gate transistor 12 and the charge-up circuit 15 are completely different. They have the same configuration.

The gate selection / voltage protection circuit 14 has an N-channel transistor 4 whose gate inputs a transfer gate selection voltage SEL, a second transfer gate transistor 13 between the analog voltage input terminal IN and the ground potential, and charge-up. An N-channel transistor 6 for pull-down is inserted in series via an input node N3.
The gate of the transistor 6 receives the selection voltage SEL.

FIG. 2 is a timing chart of each voltage for explaining the operation of the circuit of FIG. As in FIG. 6 described above, the period T1 is a non-selection period of the transfer gate transistor 12, and the operation in this period is the same as the operation of the conventional circuit of FIG.

Next, in the period T2, when the transfer gate selection voltage SEL changes from "H" to "L",
N-channel transistors 4 and 6 are both turned off, and P-channel transistor 3 and N-channel transistor 5 are turned on.

Accordingly, the charge-up input voltage S3 at the node N3 becomes substantially the same potential as the analog voltage vi, and at the same time, the gate-drain capacitance CD and the gate-source capacitance CS of the N-channel transistor 5 indicated by the dotted lines indicate
The node voltage S5 is boosted to (VD-VTZ + vi),
The gate node voltage S2 is charged to the analog input voltage vi.

Next, when the delay voltage S8 output from the delay circuit 8 changes from "H" to "L" at the start time t3 of the period T3, the node voltage S5 becomes GND level.
Channel transistor 5 is cut off.

Subsequently, the NOR output from the NOR gate 10
The voltage S10 changes from “L” to “H” and the capacitance element C
, The gate node voltage S2 is boosted to approximately (vi + VD).

As described above, according to the present embodiment, when the transfer gate node voltage S2 is charged up, the gate-drain voltage and the gate-source voltage of the N-channel MOS transistor 2 constituting the transfer gate transistor 12 are increased. The voltage is always kept at about VD of the power supply voltage regardless of the value of the analog input voltage vi. Therefore, since a stress higher than the rated value VGM is not applied to the gate oxide film, destruction of the gate oxide film and the like can be prevented.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the transfer gate node voltage S2 is changed to the analog input voltage vi.
As a means for charging up, the drain is supplied with the power supply voltage VD, the source is connected to the voltage input terminal of the second transfer gate transistor 13, the gate is connected to the analog input voltage terminal IN, and the threshold voltage is applied. VTz has an N-channel MOS transistor z set to a value close to zero.

FIG. 4 is a timing chart of each signal for explaining the operation of the circuit of FIG. The difference from the operation of the circuit of the first embodiment is that the gate node voltage S2 (vi
−VTz).

In the present embodiment, as in the first embodiment, the gate oxide film of the transfer gate transistor can be prevented from being destroyed.

[0026]

As described above, according to the present invention, when the transfer gate node voltage supplied to the transfer gate transistor is charged up, the gate-drain voltage and the gate-source voltage of the transfer gate transistor are always supplied to the power supply. Since the voltage can be suppressed to the voltage or less, unnecessary stress is not applied to the vicinity of the drain and the source of the gate oxide film of the transfer gate transistor, so that the gate oxide film can be prevented from being broken.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a timing chart of each signal for explaining the operation of the circuit of FIG. 3;

FIG. 5 is a circuit diagram of an example of a conventional gate booster circuit of a transfer gate transistor.

FIG. 6 is a timing chart of each signal for explaining the operation of the circuit of FIG. 5;

[Explanation of symbols]

 1,3 P-channel MOS transistor 2,4-7 N-channel MOS transistor 8,9 delay circuit 10 NOR gate Z, Z1 low threshold N-channel MOS transistor 12 transfer gate transistor 13 second transfer gate transistor 14, 14a Gate selection / voltage protection circuit 15 Charge-up circuit 16 Gate booster circuit IN Analog voltage input terminal C Capacitance element CD, CS Parasitic capacitance NOR NOR gate N2 Transfer gate node N3 Charge-up input node N5, N8, N10 Node S2 Transfer gate node Voltage S3 Charge-up input voltage S5 Node voltage S8, S10 Delay voltage S10 NOR voltage SEL Transfer gate selection voltage GND Ground potential OUT Analog voltage output terminal VD Source voltage vi analog input voltage vo analog output voltage

Claims (2)

(57) [Claims] 1. A gate selection / voltage protection circuit for inputting a transfer gate selection voltage for setting a power supply voltage and a ground potential to a high / low level and outputting a charge-up input voltage, and an N-channel MOS constituting a transfer gate / transistor A transistor switch and a capacitance element are connected to a transfer gate node connected to the gate of the field effect transistor, and the charge-up input voltage is input to a charge-up input node, and the booster is added by a high level of the transfer gate selection voltage. In a gate booster circuit of a transfer gate transistor in which a voltage is output to the transfer gate node,
The voltage protection circuit includes an N-channel MOS field-effect transistor having a gate inputting the transfer gate selection voltage, a drain connected to the transfer gate node and a source grounded, an analog input voltage input terminal of the transfer gate transistor and a ground. A gate of a transfer gate transistor, comprising: a second transfer gate transistor inserted between the potential point and a series circuit of the charge-up input node and an N-channel MOS field-effect transistor for pull-down. Boost circuit. 2. A gate selection / voltage protection circuit for inputting a transfer gate selection voltage for setting a power supply voltage and a ground potential to a high / low level and outputting a charge-up input voltage, and an N-channel MOS constituting a transfer gate transistor A transistor switch and a capacitance element are connected to a transfer gate node connected to the gate of the field effect transistor, and the charge-up input voltage is input to a charge-up input node, and the booster is added by a high level of the transfer gate selection voltage. In a gate booster circuit of a transfer gate transistor in which a voltage is output to the transfer gate node,
The voltage protection circuit is provided between an N-channel MOS field-effect transistor whose gate receives the transfer gate selection voltage, whose drain is connected to the transfer gate node and whose source is grounded, and the ground potential point of the power supply voltage terminal. An inserted gate is connected to an analog input voltage input terminal of the transfer gate transistor, an N-channel MOS field effect transistor having a low threshold value, a second transfer gate transistor, the charge-up input node, and an N for pull-down. A gate boosting circuit for a transfer gate transistor, comprising a series circuit with a channel MOS field effect transistor.