--—— 五、發明說明（l) 本發明是有關於-種半導體製程，且特別是有關於一 種適用於蝕刻後清理步驟的灰化製程。 一般：ί去除光阻之方法’不外乎是利用光阻去除液 溶解光阻圖案的濕式光阻剝除法，以及利用電锻為擊光阻 圖案使光阻圖案被，能量的電漿粒子轟掉或者利用灰化法 使光阻围案在含有乳氣的高溫環境下被剝❺的乾式光阻剝 除法。由於利用i式光阻剝㉟法或者電浆Α擊的乾式剝除 法均會破壞接觸開口或溝渠下所裸露的基底、金屬内連線 表面或者接觸Μ 口或溝渠之形&，因&灰化法便 剝除光降圖案之主要步驟1中，由於灰化法是使光阻二 案在充滿氧氣的高溫環境下被氧化掉，進而達到光 被剝除的目的，因此高溫的氧氣將容易與部分具反應活性 之薄膜產生氧化反應，例如接觸開口下所露出之金屬内連 線表面便容易在此充滿氧氣的高溫環境下產生氧化反應並 於金屬内連線表面產生-薄金屬氧化物。&薄金屬氧化 將會影響後續元件之導電性能 為使此習知灰化製程之缺點更清楚可見，⑽於第以 〜1Β圖中，說明一種在定義完雙鑲嵌溝渠後之光阻灰化步 驟。 首先’請參照第U圖’ ®中顯示的是__雙職溝渠之 製程。其中，標號110所代表的是位在半導體基底1〇〇上的 金屬銅内連線’而標號120代表的則是介電層。此步驟將 預備以光阻圖案130定義出一貫穿介電層12〇之雙鑲嵌溝 中的窄溝渠140。 ”------ V. Description of the invention (l) The present invention relates to a semiconductor process, and particularly to an ashing process suitable for a cleaning step after etching. General: The method of removing the photoresist is nothing more than a wet photoresist stripping method using a photoresist removal solution to dissolve the photoresist pattern, and the use of electroforging to strike the photoresist pattern to make the photoresist pattern quilt and plasma particles of energy Dry photoresist stripping method in which the photoresist enclosure is bombarded or ashed to exfoliate in a high temperature environment containing milk gas. Because using the i-type photoresist stripping method or the plasma A-type dry stripping method will damage the exposed substrate or the surface of the trench under the trench, the metal interconnecting surface, or the shape of the M port or trench, & The ashing method is the main step 1 of stripping the light drop pattern. Since the ashing method is to oxidize the photoresist in a high temperature environment full of oxygen, and then achieve the purpose of light stripping, the high temperature oxygen will It is easy to produce oxidation reaction with some reactive thin films. For example, the surface of the metal interconnects exposed under the openings is liable to produce oxidation reactions and generate thin metal oxides on the surface of the metal interconnects under the high temperature environment full of oxygen. . & Thin metal oxidation will affect the conductivity of subsequent components. In order to make the shortcomings of this conventional ashing process more clearly visible, as shown in Figure 1 ~ 1B, a photoresist ashing after defining the dual damascene trench is illustrated. step. First of all, please refer to the picture in Figure U. The process of __Shuang Duo Trench is shown. Among them, reference numeral 110 represents a metal copper interconnect on a semiconductor substrate 100, and reference numeral 120 represents a dielectric layer. In this step, a narrow trench 140 in a double damascene trench passing through the dielectric layer 120 is defined by the photoresist pattern 130. "
417241 五、發明說明（2) 其次’请參照第1 B圖’窄溝渠1 4 〇定義出來後，再於 充滿氧氣的環境中’進行灰化處理，使光阻圖案丨4〇被灰 化剝除。惟此灰化步驟是在充滿氧氣之高溫環境中進行， 光阻圖案1 3 0雖可在此灰化步驟中被剝除，但高溫的氧氣 將會與雙鑲搬溝渠150底部所露出之金屬銅内連線表面 產生氧化反應，而生成一薄氧化銅層1 6 〇。此薄氧化銅層 160無法在氫氣/氦氣之環境中被還原，因而將影響雙鑲嵌 結構狀插检連接金屬内連線時之導電特性。 有鑑於此，本發明乃揭示一種適用於蝕刻後清理步驟 的新穎灰化製程，其包括下列步驟：（a)於含有氧氣/四氟 化碳之環境中進行第一階段灰化步驟；（b)於含有氧氣/氮 氣/氫氣之環境中進行第二階段灰化步驟；以及（c)於含有 氧氣/四氟化碳之環境中進行第三階段灰化步驟。 如上所述之製程，其中第一階段灰化步驟時之氧氣/ 四氟化碳的比例為5 : 1，灰化之能量為9〇〇w，且灰化時間 為30秒1二階段灰化步料之氧氣：（氣氣/氫氣）的比 例為1 5 . 4，灰化之能量為9 〇 〇w，且灰化時間為1 2 〇秒；而 第二階段灰化步驟時之氧氣/四氟化碳的比例為5 :1灰 化之能篁為900W，且灰化時間為go秒。 為使本發明之優點和特徵更清楚可見，玆將以根據本 發明之較佳實施例和相關圖式，詳細說明如下。 圖式之簡單說明： 第1)〜1B圖顯示的是習知一種適用於蝕刻後清理步驟417241 V. Description of the invention (2) Secondly, "please refer to Figure 1B," Narrow trench 1 14 is defined, and then ashing in an environment full of oxygen ", so that the photoresist pattern is ashed and stripped. except. However, the ashing step is performed in a high-temperature environment filled with oxygen. Although the photoresist pattern 130 can be stripped in this ashing step, the high-temperature oxygen will be exposed to the metal exposed at the bottom of the double mounting trench 150. An oxidation reaction occurs on the surface of the copper interconnects, and a thin copper oxide layer 16 is formed. The thin copper oxide layer 160 cannot be reduced in a hydrogen / helium environment, and thus will affect the conductivity characteristics of the dual damascene structure-like plug-in connection to the metal interconnects. In view of this, the present invention discloses a novel ashing process suitable for the post-etching cleaning step, which includes the following steps: (a) performing the first-stage ashing step in an environment containing oxygen / carbon tetrafluoride; (b) ) Performing a second-stage ashing step in an environment containing oxygen / nitrogen / hydrogen; and (c) performing a third-stage ashing step in an environment containing oxygen / carbon tetrafluoride. The process as described above, wherein the oxygen / carbon tetrafluoride ratio in the first stage of the ashing step is 5: 1, the energy of the ashing is 900w, and the ashing time is 30 seconds. Oxygen: (Gas / Hydrogen) ratio of step material is 15.4, energy of ashing is 900w, and ashing time is 120 seconds; and oxygen / The ratio of carbon tetrafluoride is 5: 1, the energy of ashing is 900W, and the ashing time is go seconds. In order to make the advantages and features of the present invention more clearly visible, the preferred embodiments according to the present invention and related drawings are described in detail below. Brief description of the drawings: Figures 1) to 1B show a conventional method suitable for cleaning after etching.
417241 五、發明說明（3) 第2A〜2B圖顯示的是根據本發明之適用於蝕刻後清理 步驟之灰化製程。 實施例： 首先’請參照第2A圖，圖中顯示的是—雙鑲嵌溝渠之 製程。其中’標號21〇所代表的是位在半導體基底2〇()上的 金屬銅内連線，而標號22〇代表的則是介電層。此步驟將 預備以光阻圖案230定義出一貫穿介電層12〇之雙鑲嵌溝渠 中的窄溝渠240。 _其次’請參照第2B圖，窄溝渠240定義出來後，再進 行二階段灰化處理’使光阻圖案14〇被灰化剝除。其中， 第:階段灰化步驟是在充滿氧氣/四氟化碳（比例：5〇/1) 之環，中，於能量9〇〇W之條件灰化處理3〇秒。然後，再於 充滿氧氣：（氮氣/氫氣）（比例：1 5 /4 )的環境中，於能量 900W之條件進行第二階段灰化處理，為時12〇秒。最後， 再於充滿氧氣/四氟化碳（比例：50/1)之環境中，以能量 9 0 0W之條件進行第二階段灰化處理，為時3 〇秒。經過此三 階段灰化步驟後’冑可將光阻圖案23〇完整地剝除，並且 不會使雙鑲嵌溝渠2 50下所露出的銅内連線在灰化過程中 被氧化’而形成如第1B圖所示之不可被還原的氧化銅層 比較在進行本發明所揭 銅金屬内連線之電阻後可發 化前約為20. 605 ,而經過本 所得到之金屬内連線電阻約 示之三階段灰化步驟前、後的 現’銅金屬内連線之電阻在灰 發明之三階段灰化步驟處理後 為18.711。此外’銅金屬内連 417241 五、發明說明（4) 線之反射率約為1 48. 4，使此鋼金屬内連線產生氧化反應 後’其反射率為107.9 ’顯示其表面已生成有氧化銅薄 。 膜。利用本發明所揭示的灰化步驟處理此表面已生成有氧 化銅薄膜之銅金屬内連線後，其反射率轉變為〗44.9，此 值與為產生氧化反應前的銅金屬内連線之反射率相當，顯 示絕大多數的氧化銅已經在此灰化步驟中被還原為金屬 銅。再使此經過本發明所揭示的灰化步驟處理過的銅金屬 内連線進行第二次如本發明所揭示的灰化步驟，所測量到 的反射率為146 ’此值已大於未產生氧化反應之銅金屬内 連線’顯示不僅全部在氧化反應中所產生的氧化銅已全部 被還原為金屬銅，且在氧化反應前已出現在銅金屬内連線 表面之些微氧化銅薄膜也已經被還原，故其表面之還原狀 況較未產生氧化反應之銅金屬内連線佳。 因此，根據本發明所接式的三階段灰化步驟，便可 = 金屬内連線表面在灰化步驟中被氧4匕，而影響 八原有的導電特性，降低阻率。 雖然本發 限定本發明， 和範圍内，所 内’因此本發 所界定者為準 明已以較佳實施例揭露如上，然其並非用以 任何熟習此技藝者，在不脫離本發明之精神 作之各種更動與潤飾均落在本發明之範圍 明之專利保護範圍當梘後附之申請專利範417241 V. Description of the invention (3) Figures 2A to 2B show the ashing process suitable for the post-etching cleaning step according to the present invention. Embodiment: First, please refer to FIG. 2A, which shows the process of a double-inlaid trench. Among them, the reference numeral 20 represents a metal copper interconnect located on the semiconductor substrate 20 (), and the reference numeral 22 represents a dielectric layer. This step prepares to define a narrow trench 240 in the dual damascene trenches passing through the dielectric layer 120 with the photoresist pattern 230. _Secondly, please refer to FIG. 2B. After the narrow trench 240 is defined, a two-stage ashing process is performed to cause the photoresist pattern 14 to be ashed and stripped. Among them, the first-stage ashing step is an ashing treatment for 30 seconds in a ring full of oxygen / carbon tetrafluoride (ratio: 50 // 1) under the condition of an energy of 900 W. Then, in the environment filled with oxygen: (nitrogen / hydrogen) (ratio: 1 5/4), the second-stage ashing treatment was performed under the condition of energy 900W for 12 seconds. Finally, the second stage of ashing was performed in an environment full of oxygen / carbon tetrafluoride (proportion: 50/1) with an energy of 900 W for 30 seconds. After this three-stage ashing step, 'the photoresist pattern 23 can be completely peeled off, and the copper interconnects exposed under the double damascene trench 2 50 will not be oxidized during the ashing process' and formed as The non-reducible copper oxide layer shown in FIG. 1B is approximately 20.605 before the resistance of the copper metal interconnects disclosed in the present invention can be developed, and the resistance of the metal interconnects obtained by the present invention is about 20.605. The resistance of the existing copper metal interconnects before and after the three-stage ashing step is shown as 18.711 after the treatment of the three-stage ashing step of the ash invention. In addition, 'copper metal interconnect 417241 V. Description of the invention (4) The reflectivity of the wire is about 18.4. After the oxidation reaction of the steel metal interconnect is generated,' the reflectance is 107.9 ', indicating that oxidation has occurred on the surface. Copper is thin. membrane. After using the ashing step disclosed in the present invention to process the copper metal interconnects on which copper oxide films have been formed on the surface, the reflectance is changed to 44.9, which is the reflection of the copper metal interconnects before the oxidation reaction occurs. The rates are comparable, showing that most of the copper oxide has been reduced to metallic copper in this ashing step. Then the copper metal interconnects treated by the ashing step disclosed in the present invention are subjected to the second ashing step as disclosed in the present invention, and the measured reflectance is 146 'This value is greater than that without oxidation The reaction of copper metal interconnects shows that not only all the copper oxides generated during the oxidation reaction have been reduced to metallic copper, but also some micro-oxide films that have appeared on the surface of the copper metal interconnects before the oxidation reaction. Reduction, so the reduction condition on the surface is better than copper metal interconnects that do not have an oxidation reaction. Therefore, according to the three-stage ashing step connected to the present invention, the surface of the metal interconnects can be oxygenated in the ashing step, which affects the original conductivity characteristics and reduces the resistivity. Although the present invention limits the present invention, and within the scope, therefore, what is defined in the present invention shall be disclosed in the preferred embodiment as above, but it is not intended to be used by anyone skilled in the art, without departing from the spirit of the present invention Various changes and retouches fall within the patent protection scope of the present invention.