A7 415074 B7_ 五、發明說明有) 發明背景 本發明係關於一種半導體裝置，特別是關於一種使用 MO S型電晶體之比較電路。 使用MO S型電晶體之比較電路已被廣泛的應用。已 知一種具有MO S電晶體的比較路，其具有大的通道寬度 與長的通道長度以獲得一偏移電壓小的比較電路， 然而，習知之使用MO S型電晶體的比較電路，其是 用一種機構以增加Μ 0 S型電晶體之通道寬度及通道長度 ，俾降低偏移電壓。因此，存在著比較電路所佔據的面積 增大的問題。 本發明的目的是提供一種比較電路，其在一小面積內 具有小的偏移電壓，此非習知之使用MO S型電晶體之比 較電路所能達成。 發明槪要 . 本發明使用以下的方式達成上述目的。 (1 )在一種由Μ 0 S型電晶體所舊成之比較路電中 ，負載側之Μ 0 S型電晶體的互導性g m ( mutual conductance)是被設成小於一位在差動側之Μ 0 S型電晶 體之互導性g m。 .(2 )在該比較電路內，該位於負載側之MO S型電 晶體之移動性（mobility )是被設成小於該位於差動側之 Μ 0 S型電:晶體之移動性。 (3 )在該比較電路內，該位於負載側之MO S型電 一J裝--------訂---------線 \ (請先閱讀背面之注意事項士、填寫本頁) α- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明$ ) 晶體之雜質濃度（impurity concentration)是被設成薄於該 位於差動側之Μ 0 S型電晶體之雜質濃度。 (4 )在該比較電路內，該位於負載側之MO S型電 晶體之臨界電壓是被設成小於該位於差動側之Μ 0 S型電 晶體之臨界電壓。 (_ 5 )在該比較電路內，該位於負載側之Μ 0 S型電 晶體之閘極氧化薄膜（gate oxide film)是被設成厚於該位 於差動側之MO S型電晶體之閘極氧化薄膜。 (6 )在該比較電路內，該位於負載側之MO S型電 晶體是被設成P _型電晶體，而該位於差動側之MO S型 電晶體是被設成N-型電晶體。 (7 )在該比較電路內，該位於負載側之MO S型電 晶體是被設成N-型電晶體，而該位於差動側之MO S型 電晶體是被設成P -型電晶體。 (8 )植入該MO S電晶體之通道區域內的雜質是磷 〇 (9 )植入該MO S電晶體之通道篇域內的雜質是砷 〇 (1 0 )植入該MO S電晶體之通道區域內的雜質是 硼。 (1 1 )植入該MO S電晶體之通道區域內的雜質是 B F 2。 (1 2:)兩種或兩種以上的雜質被植入該.M 0 S電晶 體之通道區域° (請先閱讀背面之注意事項再填寫本頁) 裝 > t— It 1> 1 1 I 訂 ------- Q. 本紙張尺度適用中國國家標準（CNS)A4規柊（210 X 297公釐） -5- 經濟部智慧財產局員工消費合作社印製 415074 . A7 __B7_____ 五、發明說明6 ) (1 3 )在該比較電路內，僅在該位於負載側之 MO S型電晶體內，沒有閘極是與形成在基底之源極擴散 層與汲極擴散層重疊。 (1 4) 一種第二導電型之阱勢區域（WELL AR E A )是形成在一第一導電型之矽半導體的基底內， 且在醇負載側的一MO S型電晶體是形成在該第二導電型 的一阱勢區域內，且在差動側的一MO S型電晶體是形成 在該第二導電型之阱勢區域的外側。 (1 5 ) —種第二導電型之阱勢區域是形成在一第一 導電型之矽半導體的基底內，且位在該差動側的M O S型 電晶體是形成在該第二導電型之阱勢區域之內，且該位在 負載側的MO S型電晶體是形成在該第二導電型之拼勢區 域的外側。 (1 6 )第二與第三導_電型之阱勢區域是形成在一第 一導電型之矽半導體的基底內，且位在負載側與位在差動 側的Μ 0 S型電晶體相對的阱勢區域之內。 圖示簡單說明 圖1是一比較電路的電路圖，其顯示本發明之半導體 裝置之第一實施例，其中一Ν -型電晶體是設成一差動（ DIFFERENTIAL )電晶體，且一 Ρ-型電晶體是被設成一負 載（load)電晶體。 圖2是·一比較電路的電路圖，其顯示本發.明之半導體 裝置之第六實施例，其中一 P -型電晶體是被設成—負載 (請先閱讀背面之注意事項再填寫本頁) v裝---------訂----------線； 本紙張尺度適用令國國家標準（CNS)A4規格（210x297公釐） -6 - 經濟部智慧財產局員工消費合作社印製 415074> A7 __；__B7____ 五、發明說明4 ) (load )電晶體，且一 N -型電晶體是設成一差動（ DIFFERENTIAL)電晶體。 圖3是顯示於本發明第一實施例之半導體裝置之比較 電路之MO S電晶體的槪略截面圖。 圖4顯示兩種或兩種以上之通道雜質之VT P與一硼 通道齊|1量（dose)之間的關係圖> 圖5顯示兩種或兩種以上之通道雜質之VTN與一硼 通道劑量之間的關係圖。 圖6顯示通道劑量與移動性之間的關係。 圖7顯示對於任一N-阱勢濃度下，VTP與B F 2 之通道劑量之間的關係圖。 圖8顯示對於任一P—阱勢濃度下，VTN與BF2 之通道劑量之間的關係圖。 圖9顯示不同溫度基礎下，未飽合之VTP與移動性 兩者間的關係圖。 . 圖1 0顯示除去了本發明第5實施例之半導體裝置之 比較電路之比較電路與比較電路之M CVS電晶體的截面圖 〇 元件對照表 101 電源端子 102，103，201，202 P —型電晶體 1 0 4 輸出端子 105 參考電壓端子 (請先閲讀背面之迮意事項再填寫本頁) Ό 裝 -— I I I ----I 1 1 σ 本紙張尺度適用尹國國家標準（CNS)A4規格（2〗0 * 297公釐） 415074 A7 _B7五、發明說明έ ) 經濟部智慧財產局員工消費合作社印製 1 0 6 輸 入 端子 1 0 7 ' '1 0 8 ，2 0 3， 2 0 4 N — 型 電晶 體 1 0 9 接 地 端子 3 0 1 P — 型矽半導體 基 底 3 0 2 N -型阱勢層 3 0 3 P + -型擴散層 3 0 4 N + -型擴散層 3 0 5 閘 極 3 0 6 > 3 0 7 通道區 域 3 0 8 氧 化 薄膜 3 1 1 閘 極 氧化薄膜 4 0 1 比 較 電路 4 0 2 電 路 4 0 3 P — 型金氧半電 晶 體 4 0 4， 4 0 6 N -型 金 氧 半電 晶體 4 0 9 低 濃 度擴散層 4 1 2 側 間 隔. 發 明 詳細說 明 在本發 明 之 半導體裝置 中 藉著 使用 Μ 0 S型 電 晶 體 > 可 以了解 — 種 具降低的偏 移 雷 壓及 高準 確 性 ，且 佔 據 小 面積的比較電路。 接下來，將伴隨著所附圖示詳細說明本發明之較佳實 施例。 (請先閱讀背面之注意事項再填寫本頁) · 褒！-----訂---------線) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -8- A7 415074 ___B7 _ 五、發明說明6 ) 將顯示的是依據本發明之半導體裝置的第一個實施例 。圖1所示之比較電路中，兩個Ρ —型電晶體1 〇 2、 1 0 3皆是被設成一負載電晶體，兩個Ν —型電晶體 1 0 7，1 0 8皆是被設成差動電體。該比較電路亦包含 一電源端子1 0 1、一輸出端子1 0 4、一參考電壓端子 10$、一輸入端子106、以及一接地端子109 恒定的電位能施於參考電壓端子1 0 5。此時，當施於輸 入端子1 0 6的電位能小於施於參考電壓端子10 5的電 位能時，施於電源端子1 0 1的電位能從輸出端子1 0 4 被輸出。相反地，當施於輸入端子1 0 6的電位能大於施 於參考電壓端子1 〇 5的電位能時，施於接地端子1 0 9 的電位能從輸出端子1 0 4被輸出。輸出的改變被稱爲反 相（inversion) ° 在該皆被設成負載電晶體之P-型電晶體1 0 2、 1 0 3的尺寸彼此相同，且該被設成差動電晶體之N-型 電晶體1 0 7、1 0 8的尺寸彼此相同的情形下，當施於 參考電壓端子1 0 5的電位能與施於輸_入端子1 0 6的電 位能彼此相等時，其輸出是反相。但是，此反相實際上是 由於施於參考電壓端子1 0 5的電位能以及施於輸出端子 的電位能彼此並不相同之下之處理的準確性及其它因素所 造成。此時，施於參考電壓端子1 0 5的電位能與施於輸 出端子的電位能的差稱爲偏移電壓。偏移電壓的計算公式 如下。 · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項#填寫本頁) 裝 ! —訂-- - -----線. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 415074 A7 ___B7 ___ 五、發明說明6 )A7 415074 B7_ 5. Description of the invention Background of the invention The present invention relates to a semiconductor device, and more particularly to a comparison circuit using a MO S type transistor. Comparison circuits using MO S-type transistors have been widely used. A comparison circuit with a MO S transistor is known, which has a large channel width and a long channel length to obtain a comparison circuit with a small offset voltage. However, a comparison circuit using a MO S type transistor is conventionally known. A mechanism is used to increase the channel width and channel length of the M 0 S-type transistor and reduce the offset voltage. Therefore, there is a problem that the area occupied by the comparison circuit increases. The object of the present invention is to provide a comparison circuit which has a small offset voltage in a small area, which is a non-conventional comparison circuit using a MO S-type transistor. Summary of the Invention The present invention achieves the above-mentioned objects using the following methods. (1) In a comparative circuit formed by an M 0 S-type transistor, the mutual conductance gm (mutal conductance) of the M 0 S-type transistor on the load side is set to less than one bit on the differential side. The mutual conductivity gm of the M 0 S-type transistor. (2) In the comparison circuit, the mobility of the MO S-type transistor on the load side is set to be smaller than that of the M 0S-type transistor on the differential side: the mobility of the crystal. (3) In the comparison circuit, the MO S-type electric J-equipment located on the load side -------- order --------- line \ (Please read the precautions on the back first (Fill out this page) α- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) -4- A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs System V. Description of the Invention The impurity concentration of the crystal is set to be thinner than the impurity concentration of the M 0 S type transistor located on the differential side. (4) In the comparison circuit, the threshold voltage of the MO S-type transistor on the load side is set to be smaller than the threshold voltage of the M 0S-type transistor on the differential side. (_ 5) In the comparison circuit, the gate oxide film of the M 0 S-type transistor on the load side is set thicker than the gate of the MO S-type transistor on the differential side. Extremely oxidized film. (6) In the comparison circuit, the MO S-type transistor on the load side is set as a P_-type transistor, and the MO S-type transistor on the differential side is set as an N-type transistor . (7) In the comparison circuit, the MO S-type transistor on the load side is set as an N-type transistor, and the MO S-type transistor on the differential side is set as a P-type transistor . (8) The impurity implanted in the channel region of the MOS transistor is phosphorus. (9) The impurity implanted in the channel region of the MOS transistor is arsenic. (10) The implanted in the MOS transistor. The impurity in the channel region is boron. (1 1) The impurity implanted in the channel region of the MOS transistor is B F 2. (1 2 :) Two or more kinds of impurities are implanted into the channel area of the M 0 S transistor. (Please read the precautions on the back before filling this page.) Equipment > t— It 1 > 1 1 Order I ------- Q. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -5- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 415074. A7 __B7_____ V. Description of the invention 6) (1 3) In the comparison circuit, only in the MO S-type transistor located on the load side, no gate electrode overlaps the source diffusion layer and the drain diffusion layer formed on the substrate. (1 4) A well conductivity region of the second conductivity type (WELL AR EA) is formed in the substrate of a silicon semiconductor of the first conductivity type, and a MO S-type transistor on the alcohol load side is formed in the first conductivity type A MO S-type transistor in a well potential region of the two conductivity type and on the differential side is formed outside the well potential region of the second conductivity type. (1 5) A well potential region of a second conductivity type is formed in a substrate of a silicon semiconductor of a first conductivity type, and a MOS transistor located on the differential side is formed in the second conductivity type The MO S-type transistor located in the well potential region and located on the load side is formed outside the potential region of the second conductivity type. (1 6) The well potential regions of the second and third conductivity types are M 0 S-type transistors formed in the substrate of a silicon semiconductor of the first conductivity type and located on the load side and on the differential side. Within the opposite well potential region. Brief Description of the Drawings Figure 1 is a circuit diagram of a comparison circuit showing a first embodiment of the semiconductor device of the present invention, in which an N-type transistor is set as a differential (DIFFERENTIAL) transistor, and a P-type The transistor is set as a load transistor. Figure 2 is a circuit diagram of a comparison circuit showing a sixth embodiment of the semiconductor device of the present invention, in which a P-type transistor is set as a load (please read the precautions on the back before filling this page) v --------- order ---------- line; this paper size applies the national standard (CNS) A4 specification (210x297 mm) -6-Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperatives 415074 > A7 __; __ B7____ V. Description of the invention 4) (load) transistor, and an N-type transistor is set as a differential (DIFFERENTIAL) transistor. Fig. 3 is a schematic cross-sectional view of a MOS transistor of a comparison circuit of a semiconductor device according to a first embodiment of the present invention. Figure 4 shows the relationship between VT P of two or more channel impurities and a boron channel | 1 dose > Figure 5 shows VTN and one boron of two or more channel impurities Diagram of the relationship between channel doses. Figure 6 shows the relationship between channel dose and mobility. Figure 7 shows the relationship between VTP and the channel dose of B F 2 for any N-well potential concentration. Figure 8 shows the relationship between the channel doses of VTN and BF2 for any P-well potential concentration. Figure 9 shows the relationship between unsaturated VTP and mobility at different temperature bases. Fig. 10 shows a cross-sectional view of a comparison circuit and a comparison circuit of an M CVS transistor of a comparison circuit of a semiconductor device according to a fifth embodiment of the present invention. ○ Component comparison table 101 Power terminals 102, 103, 201, 202 P-type Transistor 1 0 4 Output terminal 105 Reference voltage terminal (please read the intention on the back before filling this page) Ό Equipment-— III ---- I 1 1 σ This paper size is applicable to Yin National Standard (CNS) A4 Specifications (2〗 0 * 297 mm) 415074 A7 _B7 V. Description of invention) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 0 6 Input terminals 1 0 7 '' 1 0 8 2 0 3 2 0 4 N — type transistor 1 0 9 ground terminal 3 0 1 P — type silicon semiconductor substrate 3 0 2 N-type well potential layer 3 0 3 P + -type diffusion layer 3 0 4 N + -type diffusion layer 3 0 5 Gate Pole 3 0 6 > 3 0 7 Channel area 3 0 8 Oxide film 3 1 1 Gate oxide film 4 0 1 Comparator circuit 4 0 2 Circuit 4 0 3 P — type Oxygen semi-transistor 4 0 4, 4 0 6 N-type gold-oxygen semi-transistor 4 0 9 low-concentration diffusion layer 4 1 2 side space. Detailed description of the invention By using M 0 S-type Crystals> You can understand — a comparison circuit with reduced offset lightning pressure and high accuracy, occupying a small area. Next, a preferred embodiment of the present invention will be described in detail with accompanying drawings. (Please read the notes on the back before filling out this page) · 褒! ----- Order --------- line) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -8- A7 415074 ___B7 _ V. Description of the invention 6) will A first embodiment of a semiconductor device according to the present invention is shown. In the comparison circuit shown in FIG. 1, two P-type transistors 1 0 2 and 103 are both set as a load transistor, and two N-type transistors 10 7 and 108 are both Set as a differential electric body. The comparison circuit also includes a power terminal 101, an output terminal 104, a reference voltage terminal 10 $, an input terminal 106, and a ground terminal 109. A constant potential can be applied to the reference voltage terminal 105. At this time, when the potential energy applied to the input terminal 106 is smaller than the potential energy applied to the reference voltage terminal 105, the potential applied to the power terminal 101 can be output from the output terminal 104. In contrast, when the potential energy applied to the input terminal 106 is larger than the potential energy applied to the reference voltage terminal 105, the potential applied to the ground terminal 1009 can be output from the output terminal 104. The change in output is called inversion. Here P-type transistors 1 0 2 and 1 0 3 which are all set as load transistors are the same in size, and N which is set as a differential transistor. When the sizes of the -type transistors 1 0 7 and 1 8 are the same as each other, when the potential applied to the reference voltage terminal 1 0 5 and the potential applied to the input terminal 1 0 6 are equal to each other, their outputs It is inverted. However, this inversion is actually caused by the accuracy of the processing of the potential energy applied to the reference voltage terminal 105 and the potential energy applied to the output terminal and other factors. At this time, the difference between the potential energy applied to the reference voltage terminal 105 and the potential energy applied to the output terminal is called an offset voltage. The formula for calculating the offset voltage is as follows. · This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back first # Fill this page) Binding! —Order------- line. Ministry of Economy Wisdom Printed by the Consumer Cooperative of the Property Bureau Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 415074 A7 ___B7 ___ V. Description of Invention 6)
Voff = AVtn + -/(αΚρ/βΚη) χ | AVtp | + (V{a/p) - 1) (Vref -Vb - Vtn) -(1) … 在公式（1)中，Vo f f表示偏移電壓，Δνΐ： n 表示組成差動電晶體之Ν —型電晶體1 0 7、1 0 8之臨 界電壓的差（此後以Vth表示）-AVtp表示表示組 成負_電晶體之P -型電晶體1 0 2、1 0 3之V t h的 差，而Κ η表示組成差動電晶體之任~個N -型電晶體 1 0 7、1 0 8之互導性gm 〇 Κρ表示組成負載電晶體 之任一個:Ρ —型電晶體1 0 2、1 0 3之互導性gm。a 表示組成負載電晶體之P —型電晶體1 0 2、1 0 3之互 導性gm的比値。；3表示組成差動電晶體之N —型電晶體 107、108之互導性gm的比値。Vr e f表示施於 參考電壓端子1 0 5之電位能（此後以V r e ί表示）° + Va表示施於電源端子1 〇 1之電位能，而Vb表示施於 接地端子1 0 9之電位能。V t η表示組成差動電晶體之 任一Ν-型電晶體107、108之Vt h，而Vt ρ表 示組成負載電晶體之任一 P —型電晶體'Ί 0 2 ' 10 3之 V t h。 公式（1 )是由以下的方式獲得。圖1中組成負載電 晶體之兩P —型電晶體102、103的通道寬度、通道 長度、以及V t h値分別被設成是彼此相等，且組成差動 電晶體之兩N_型電晶體107、108的通道寬度 '通 道長度、以及V t h値亦分別被設成是彼此相等。.流經組 成負載電晶體之P -型電晶體1 0 2以及組成差動電晶體 —D裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中囤國家標準（CNS)A4規格（210 X 297公釐） -10- A7 415074 __；_B7_ 五、發明說明έ ) (請先閱讀背面之注意事項再填寫本頁) 之Ν -型電晶體1 0 7的電流以I 1表示。流經組成負載 電晶體之Ρ —型電晶體1 0 3以及組成差動電晶體之Ν — 型電晶體1 0 8的電流以I 2表示。在此狀況下’電流 I 1與I 2可以下列公式表示。 11 = Kp(Va - vref - |vtp|)2 = Kn{Vref - Vb-Vtn)2 -(2) 12 — aKp{Va. — Vdd - |vtp - AVtpJ}1 =βκη<νίη - Vb - (vtn - AVtn)>2 Vin = vref - Voff _(4) 此處，V i n是施於輸入端子1 0 6的電位能（此後 以V i η表示）。 經濟部智慧財產局員工消費合作社印製 若組成負載電晶體之兩Ρ -型電晶體1〇2、103 彼此的通道寬度、通道長度、V t h '以及互導性gm是 相同的，且若組成差動電晶體之兩N 一型電晶體1 0 7、 108彼此的通道寬度、通道長度、v t h、以及互導性 gm是相同的’當V i n = V r e f時’一開始的輸出是 反相的e但是，當造成偏向電壓而達到'公式（4 )的狀態 時，輸出是反相的。當輸出是反相時，建立了11=12 ，所以公式（2 )與公式（3 )相等，且公式（4 )被取 代，假設造成了偏向電壓。公式（1 )是由解決上述公式 所獲得。從公式（1 )需了解的是，負載電晶體之互導性 gm降低而差動電晶體之互導性增大，俾降低偏移電 壓。 ： 由於在P -型電晶體內的載子是正的電洞’ P型電晶 11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公爱） 經濟部智慧財產局員工消費合作社印*J衣 415074 A7 _____B7___ 五、發明說明6 ) 體的移動性是以電子爲載子之1N[-型電晶體的移動性的1 /2到1/3。由於互導性gm與移動性成正比，P —型 電晶體是被安排在負載側而N _型電晶體是被安排在差動 側，在與N -型電晶體是在負載側而P -型電晶體是在差 動側的比較電路相比之下，可以使偏移電壓降低。 璋下來，將詳細說明依據本發明之半導體裝置的第二 實施例。圖3是以P -型電晶體爲負載側、N —型電晶體 爲差動側之本發明之半導體裝置的槪略截面圖。 N—型電晶體包含一閘極氧化薄膜311及一形成於 一 P —型矽半導體基底3 0 1上之多晶矽閘極3 0 5，分 別稱爲源、汲極之高濃度的N+型擴散層3 0 4是形成在 該矽基底上之閘極的兩端，且一通道區域3 0 7是形成在 該擴散層3 0 3之間。而P —型電晶體是包含一閘極氧化 薄膜3 1 1及形成於該矽半導體基底3 0 1上之另一個多 晶矽閘極3 0 5，分別稱爲源、汲極之高濃度的P +型擴 散層3 0 3是形成在該矽基底上之N —型阱勢層3 0 2之 閘極的兩端，且一通道區域3 0 6是形成在該擴散層3 0 3之間。一屏蔽氧化薄膜3 0 8形成於上述元件之間，以 將上述元件分隔開。一屏蔽氧化薄膜形成於上述元件之間 ，以將上述元件分隔開。 硼、BF2等P -型雜質或砷、磷等N_型雜質是被 植入M OS電晶體的通道區域。當該P〇ly cry st al矽閘極是N 一型時，Ρ· -型雜質如硼、B F 2等是被植入增強模式及 減弱模式之P _通道MO S電晶體之通道區域。在增強模 (請先閱‘讀背面之注意事項系填寫本頁) 裝------！|訂---------線 σ 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） -12- 經濟部智慧財產局員工消費合作社印製 415074 A7 _____B7____ 五、發明說明彳o ) 式下，P _型雜質如硼、B F 2等是被植入一 N -通道 MO S電晶體之通道區域，而在減弱模式下，N_型雜質 如砷、磷是被植入該N -通道MO S電晶體之通道區域。 當該多晶矽閘極是P -型時，在增強模式下，N_型雜質 如砷、磷是被植入該P —通道MO S電晶體的通道區域， 而在鱗弱模式下，P —型雜質如硼、B F 2等是被植入該 P -通道MO S電晶體之通道區域。N-型雜質如砷、磷 是被植入增強模式及減弱模式之N -通道M〇 S電晶體之 通道區域。此時，在負載側之通道區域的雜質密度濃於在 差動側之通道區域之雜質密度，俾降低移動性。 .藉著在該負載側的MOS電晶體植入兩種或兩種以上. 的雜質，可更進一步的降低移動性。在此例中’任可時刻 下該P _型雜質與N -型雜質是彼此混合。例如’在輕微 的植入該N -型雜質後，接著植入該P. _型雜質。由於該 P -型雜質與N -型雜質彼此電性抵消，即使植入大量的 雜質（P —型）時，該MO S電晶體仍可以被設置成具有 相同的特性（臨界.電壓）。圖4顯示VTP與硼通道劑量 的關係圖。例如，當欲使VTP等於習知的0.5伏特時 ，7 . 4 7 X 1 0 1 1 ( atoms/cm2)的通道雜質（硼）被植 入（標準），當lxl 0^( atom s/cm2 )的磷與通道雜質 混合時，8、84X1011 ( atoms/cm2)的通道雜質被植 入。更進一步地’當2 X 1 0 11 (atoms/cm2)的磷與通道 雜質混合時_.，9 . 5 7 X 1 0 1 1 ( atoms/cm2)的通道雜質 被植入。也就是，當不同極的雜質彼此混合時，即使在相 7'\裝--------訂----- '... (請先閲讀背面之注意事項再填寫本頁) 線 ο· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -13- 415074 A7 _B7_____ 五、發明說明¢1 ) 同之VT P之下，仍可以植入大量的雜質。圖5顯示 VTN與硼通道劑量的關係圖。同樣地，當N —型雜質如 磷等被混合時，即使在相同之VTN的情形下’仍可以植 入大量的P -型雜質。例如，當欲使VTN等於習知的 0 · 5 伏特時，2 . 2 5 X 1 0 1 1 ( atoms/cm2)的通道雜 質（W)被植入（標準），且當lxlO11»： at〇ms/cm2) 的磷與通道雜質混合時，2 . 87X1011 ( atoms/cm2) 的通道雜質被植入_。更進一步地，當2 x 1 Ο11 ( atoms/ cm2)的磷與通道雜質混合時，3 · 40 x 1 Ο11 ( atoms/ cm2)的通道雜質被植入。 接下來將說明當雜質被植入MO S型電晶體之通道區 域時其移動性的改變。圖6顯示當以與P型半導體基底具 有相同導電型態之硼作爲雜質，以及以具有與該半導體基 底相反導電型態之砷作爲雜質被植入該P型半導體基底之 通道區域時，劑量與移動性之間的關係。當通道劑量增加 時移動性降低。從此關係需了解的是，藉著將雜質植入通 道區域，可容易地改變移動性。因此，’藉著將負載側之通 道雜質濃度設定的比差動側的濃，在負載側之MO S型電 晶體之互導性g m會變得小於差動側之Μ 0 S電晶體之互 導性g m，因此可以降低偏移電壓》 接下來將詳細說明依據本發明第之半導體裝置之第三 個實施實例。構成一負載電晶體之P型電晶體的臨界電壓 是被設成高:於構成一差動電晶體之N -型電晶體的臨界電 壓。圖7顯示該P -型電晶體與一通道雜質的量的關係。 ------------3裝 K!J (請先閲讀背面之生意事項再填寫本頁) ----訂---------線 σ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格<210 * 297公釐） -14- 415074 A7 ___B7_五、發明說明（2 ) 圖8顯示該N -型電晶體與一通道雜 1當該P _型電晶體的臨界電壓被設 將通道雜質的量設至6 6 2X10 如，當該N -型電晶體的臨界電壓被 需將通道雜質的量設至2 . 8 7X1 當臨坪電壓增大時，通道雜質的量增 側之MO S電晶體之臨界電壓被設置 M〇S電晶體之臨界電壓時’可以降 質的量的關係。例如 成0 . 6 V時，必需 1 1 ( atom/cm2)。例 設成0 . 5 V時，必 0 1 1 ( atom/cm2)。 加。也就是，當負載 成高於差動側之. 低偏移電壓。更佳的 的.更高些。圖9顯示 從圖9可以了解，當 是，將該P -型電晶體的臨界電壓設 該P -型電晶體與移動性的關係圖。 該P -型電晶體的臨界電壓增大.時，移動性降低 請 先 Μ 讀 背 之 it 意 事 項Voff = AVtn +-/ (αΚρ / βΚη) χ | AVtp | + (V {a / p)-1) (Vref -Vb-Vtn)-(1)… In formula (1), Vo ff represents the offset Voltage, Δνΐ: n represents the difference between the threshold voltages of the N-type transistors 1 0, 108, which constitute the differential transistor (hereinafter referred to as Vth)-AVtp, which represents the P-type transistor, which constitutes a negative transistor The difference in V th between 1 0 2 and 1 0 3, and κ η represents any one of the N-type transistors. The mutual conductance gm of the 7- and 108-g transistors 〇 ρ represents the composition of the load transistor Either: the mutual conductivity gm of the P-type transistor 1 0 2, 1 0 3. a represents the ratio 互 of the transconductivity gm of the P-type transistors 1 0 2 and 1 0 3 which make up the load transistor. ; 3 represents the ratio 互 of the mutual conductivity gm of the N-type transistors 107 and 108 constituting the differential transistor. Vr ef represents the potential energy applied to the reference voltage terminal 1 0 5 (hereinafter referred to as V re ί) ° + Va represents the potential energy applied to the power terminal 1 〇1, and Vb represents the potential energy applied to the ground terminal 1 0 9 . V t η represents Vt h of any N-type transistor 107, 108 constituting a differential transistor, and Vt ρ represents V th of any P-type transistor 'Ί 0 2' 10 3 constituting a load transistor. . The formula (1) is obtained in the following manner. The channel width, channel length, and V th 値 of the two P-type transistors 102 and 103 constituting the load transistor in FIG. 1 are set to be equal to each other, and the two N_-type transistors 107 constituting the differential transistor are respectively set. The channel width, channel length, and Vth 値 of 108 are also set to be equal to each other. .P-type transistor 102 that flows through the load transistor and the differential transistor—D package -------- order --------- (read the first Note: Please fill in this page again.) This paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm) -10- A7 415074 __; _B7_ V. Description of the invention) (Please read the precautions on the back before Fill out this page) The current of the N-type transistor 1 0 7 is represented by I 1. The current flowing through the P-type transistor 103 which constitutes the load transistor and the N-type transistor 108 which constitutes the differential transistor is represented by I 2. In this condition, the currents I 1 and I 2 can be expressed by the following formulas. 11 = Kp (Va-vref-| vtp |) 2 = Kn {Vref-Vb-Vtn) 2-(2) 12 — aKp {Va. — Vdd-| vtp-AVtpJ} 1 = βκη < νίη-Vb-( vtn-AVtn) > 2 Vin = vref-Voff _ (4) Here, V in is the potential energy applied to the input terminal 1 0 6 (hereinafter referred to as V i η). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the two P-type transistors 10 and 103 constituting the load transistor have the same channel width, channel length, Vth 'and mutual conductivity gm, and if the composition The two N-type transistors 1 0 7 and 108 of the differential transistor have the same channel width, channel length, vth, and mutual conductivity gm. 'When V in = V ref', the initial output is inverted. E However, when the bias voltage is reached to reach the state of 'Formula (4), the output is inverted. When the output is inverted, 11 = 12 is established, so formula (2) is equal to formula (3), and formula (4) is replaced, assuming that a bias voltage is caused. Formula (1) is obtained by solving the above formula. It should be understood from formula (1) that the transconductance gm of the load transistor is reduced and the transconductance of the differential transistor is increased, so that the offset voltage is reduced. ： Because the carriers in the P-type transistor are positive holes' P-type transistor 11-This paper size applies the Chinese National Standard (CNS) A4 specification (210x 297 public love) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * J clothing 415074 A7 _____B7___ V. Description of invention 6) The mobility of the body is 1/2 [1/3] of the mobility of 1N [-type transistor with electrons as carriers. Since the transconductance gm is proportional to the mobility, the P-type transistor is arranged on the load side and the N_-type transistor is arranged on the differential side, while the N-type transistor is on the load side and P- Compared with the comparison circuit on the differential side, the type transistor can reduce the offset voltage. Now, a second embodiment of the semiconductor device according to the present invention will be described in detail. Fig. 3 is a schematic cross-sectional view of a semiconductor device of the present invention with a P-type transistor as a load side and an N-type transistor as a differential side. The N-type transistor includes a gate oxide film 311 and a polycrystalline silicon gate 305 formed on a P-type silicon semiconductor substrate 301, which are called a high-concentration N + type diffusion layer of a source and a drain, respectively. 3 0 4 are both ends of the gate formed on the silicon substrate, and a channel region 3 7 is formed between the diffusion layer 3 3. The P-type transistor includes a gate oxide film 3 1 1 and another polycrystalline silicon gate 3 5 formed on the silicon semiconductor substrate 3 0 1, which are called a high concentration P + of a source and a drain, respectively. The type diffusion layer 3 0 3 is formed at both ends of the gate of the N-type well potential layer 3 2 2 formed on the silicon substrate, and a channel region 3 06 is formed between the diffusion layer 3 0 3. A shielding oxide film 308 is formed between the above elements to separate the above elements. A shielding oxide film is formed between the components to separate the components. P-type impurities such as boron and BF2 or N-type impurities such as arsenic and phosphorus are the channel regions of the M OS transistor. When the Ply cry st al silicon gate is N-type, P · -type impurities such as boron, B F 2 and the like are implanted in the channel region of the P_channel MOS transistor in the enhanced mode and the weakened mode. Install in the enhancement mode (please read ‘Precautions on the back page and fill out this page first). | Order --------- Line σ This paper size is applicable to China National Standard (CNS) A4 (210x297 mm) -12- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 415074 A7 _____B7____ 5. Description of the invention彳 o) In the formula, P_-type impurities such as boron and BF 2 are implanted in the channel region of an N-channel MOS transistor, and in the weakened mode, N_-type impurities such as arsenic and phosphorus are implanted. The channel region of the N-channel MOS transistor. When the polycrystalline silicon gate is P-type, in the enhancement mode, N-type impurities such as arsenic and phosphorus are implanted in the channel region of the P-channel MOS transistor, and in the scale mode, the P-type Impurities such as boron, BF 2 and the like are implanted in the channel region of the P-channel MOS transistor. N-type impurities such as arsenic and phosphorous are implanted in the channel region of N-channel MOS transistor in enhanced mode and weakened mode. At this time, the impurity density in the channel region on the load side is higher than the impurity density in the channel region on the differential side, thereby reducing mobility. By implanting two or more impurities in the MOS transistor on the load side, the mobility can be further reduced. In this example, the P_-type impurity and the N-type impurity are mixed with each other at any time. For example, 'after the N-type impurity is slightly implanted, then the P._type impurity is implanted. Since the P-type impurity and the N-type impurity are electrically canceled from each other, even when a large amount of the impurity (P-type) is implanted, the MOS transistor can be set to have the same characteristics (threshold voltage). Figure 4 shows the relationship between VTP and boron channel dose. For example, when it is desired to make VTP equal to the conventional 0.5 volt, a channel impurity (boron) of 7.4 7 X 1 0 1 1 (atoms / cm2) is implanted (standard), and when lxl 0 ^ (atom s / cm2 When phosphorus is mixed with channel impurities, channel impurities of 8, 84 × 1011 (atoms / cm2) are implanted. Still further, when 2 X 1 0 11 (atoms / cm2) phosphorus is mixed with the channel impurities, .5, 7 7 X 1 0 1 1 (atoms / cm2) channel impurities are implanted. That is, when impurities of different poles are mixed with each other, even in the phase 7 '\ install -------- order -----' ... (Please read the precautions on the back before filling this page) Line ο · This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -13- 415074 A7 _B7_____ V. Description of the invention ¢ 1) Under the same VT P, a large amount of impurities can still be implanted. Figure 5 shows the relationship between VTN and boron channel dose. Similarly, when N-type impurities such as phosphorus are mixed, even in the case of the same VTN, a large amount of P-type impurities can be implanted. For example, when it is desired to make VTN equal to the conventional 0.5 volts, a channel impurity (W) of 2. 2 X X 1 0 1 1 (atoms / cm2) is implanted (standard), and when lxlO11 »: at〇 ms / cm2) of phosphorus is mixed with channel impurities, 2.87X1011 (atoms / cm2) of channel impurities are implanted. Furthermore, when 2 x 1 0 11 (atoms / cm2) phosphorus is mixed with the channel impurities, 3 · 40 x 1 0 11 (atoms / cm2) channel impurities are implanted. Next, the change in mobility when an impurity is implanted in the channel region of a MO S-type transistor will be explained. FIG. 6 shows the dose and The relationship between mobility. Mobility decreases as the channel dose increases. It is important to understand from this relationship that mobility can be easily changed by implanting impurities into the channel area. Therefore, 'by setting the impurity concentration of the channel on the load side to be thicker than that on the differential side, the transconductance gm of the MO S-type transistor on the load side becomes smaller than that of the M 0 S transistor on the differential side. Conductivity gm, so that the offset voltage can be reduced. "Next, a third embodiment of the semiconductor device according to the present invention will be described in detail. The threshold voltage of the P-type transistor constituting a load transistor is set to be high: the threshold voltage of the N-type transistor constituting a differential transistor. FIG. 7 shows the relationship between the P-type transistor and the amount of one channel impurity. ------------ 3 Pack K! J (please read the business matters on the back before filling this page) ---- Order --------- Line σ Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 specification < 210 * 297 mm) -14- 415074 A7 ___B7_ V. Description of the invention (2) Figure 8 shows the N-type transistor and the One channel miscellaneous 1 When the critical voltage of the P_-type transistor is set to set the amount of channel impurities to 6 6 2X10 For example, when the critical voltage of the N-type transistor is required to set the amount of channel impurities to 2.8 7X1 When the threshold voltage increases, the threshold voltage of the MOS transistor on the increase side of the channel impurity is set to the threshold voltage of the MOS transistor when the threshold voltage can be degraded. For example, if it is 0.6 V, 1 1 (atom / cm2) is required. For example, when it is set to 0.5 V, it must be 0 1 1 (atom / cm2). plus. That is, when the load becomes higher than the differential side. Low offset voltage. Better. Higher. Figure 9 shows the relationship between the mobility of the P-type transistor and the threshold voltage of the P-type transistor when it is understood from Figure 9. The threshold voltage of the P-type transistor increases. When the mobility decreases, please read it first.
填 V./· 寫裝 本衣 頁I 經濟部智慧財產局員工消費合作社印製 更有效的是使該構成負載側之P -型電晶體是設置在 一厚的N -型阱勢區域內以，俾將構成負載側之p —型電 晶體之通道區域的雜質濃度設定成濃於該構成差動側之N -型電晶體之通道區域的雜質濃度。圖7顯示VTP與各 個N —阱勢濃度之通道雜質量的關係。例如，當VTP被 設至 0.5V 時，在一 2X1012( at'cm/cm2)的 N —阱 勢中，需要將通道雜質（硼）的量設至6 . 44X1011 (atom/cm2)，而在 3 X 1 0 1 2 ( atom/cm2)的 N -阱勢中 ，需設至 7 , 4 7 X 1 0 1 1 ( atom/cm2)，而在一3 X 1 0 1 2 ( atom/cm2)的 N -阱勢中，需設至 9 . 5 7 X 1 0 1 1 ( atom/cm2)。當N_阱勢的濃度增加時，通道雜 質的量增加：。 如果構成負載側之P-型電晶體的移動性小於構成差 訂 卜紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 15 A7 415074 _____B7__ 五、發明說明彳3 ) (請先閱讀背面之注意事項再填寫本頁) 動側之N -型電晶體的移動性時，構成負載側之P -型電 晶體與構成差動側之N -型電晶體兩者皆可設置在N ~阱 勢區域內。此時，可以使N -型電晶體之通道區域內的雜 質濃度與P -型電晶體之通道區域區內之雜質濃度的差異 可以變得更大。圖8顯示VTN與各個P —阱勢濃度之通 道雜寫量的關係。例如，當VTN被設至0.45V時， 在一4 X 1 0 1 2 ( atom/cm2)的N —阱勢中，需要將通道 雜質（硼）的量設至2 · 3 4 X 1 0 1 1 ( atom/cm2)，而 在一6 X 1 0 12 (atom/cm2)的N —阴1勢中，需設至 1 . 9 9 X 1 0 1 1 ( atom/cm2)。因此，當 P —阱勢的濃 度增加時，通道雜質的量可以降低，所以，雜雜濃度的差 異增大。 經濟部智慧財產局員工消費合作社印製 位於負載側的MO S電晶體並不需要設置在阱勢區域 內。可以藉著使用一 N—型基底製造出一 P —型阱勢，且 構成負載側電晶體的一P -型電晶體可以從N -型矽半導 體基底內被製造出，且構成差動側電晶體的一N —型電晶 體可以從該P -型阱勢內 被製造出’。在此例下，可以成 功地將構成負載側的P -型電晶體之通道區域的雜質濃度 設得濃於構成差動側之N-型電晶體之通道區域的雜質濃 度。 依據本發明之半導體裝置之第四實施例將詳細說明於 下。藉.著將位於負載側之Μ 0 S電晶體的閘極氧化膜的厚 度設定成厚:於位於差動側之Μ 0 S電晶體的閘極氧化膜的 厚度時，可以降低偏移電壓：互動性gm與該閘極氧化膜 -16- 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 415074 A7 B7 五、發明說明（u ) 的厚度成反比。因此，當厚度增加時，互導性gm降低。 例如，當一厚度爲1 5 Ο A的氧化膜形成在一半導體基底 的整個表面時，該氧化膜只有選擇性的在形成差動側之 MO S型電晶體所在的區域內被蝕刻。該基底的整個表面 再度的被氧化以彤成一厚度爲2 0 Ο A的氧化膜。因此， .在差_側之MO S型電晶體的閘極氧化膜的厚度是被設成 最後氧化之氧化膜的厚度，2 0 0A。位在負載側之 M G S電晶體之閘極氧化膜的厚度是1 50 + 200A， 即約3 0 0 Α。因此，位於負載側之Μ 0 S電晶體的互導 性'g m可以被設得小於差動側。 依據本發明之半導體裝置之第五實施例將詳細說明如 下。圖5顯示構成如電源IC'LCD控制IC等之比較 電路4 0 1之MO S電晶體，以及除了該比較電路外，一 電路4 0 2之MOS電晶體的截面圖。 該比較電路4 0 1是由一位在差動側之N —型MO_S 電晶體以及一位在負載側之P -型Μ 0 S電晶體所組成。 在差動側的Ν -型.Μ ◦ S電晶體4 0 4 ”內，一側間隔 4 1 2形成在一閘極3 0 5的兩端。低濃度的擴散層（Ν —LDD) 4 0 9是形成在該側間隔之下的矽基底內°稱 爲源汲極（source drain )的高濃度的擴散層（Ν +擴散層 )3 0 4是形成在低濃度擴散層4 0 9的側邊。因此’形 成一種所謂之N —型LDD電晶體。除了比較電路之外’ 一電路之N:—型MO S電晶體4 06亦是相同.之L DD電 晶體。 -------------D裝--------訂---------線 <請先閲讀背面之注意事項再填寫本頁》 Q· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .17 415074 A7 __B7 _____ 五、發明說明（15 ) 在負載側之P -型MOS電晶體40 3內，另一側間 隔4 1 2是同樣地是形成在另一閘極的兩側。但是，在該 側間隔之下的基底內並沒有形成低濃度的擴散層（LDD )，且一所謂之源汲極之高濃度的擴散層（P +擴散層） 3 0 3是不與該閘極重疊而形成。當該P —型MO S電晶 體是P上述方式建構時，在該P -型MO S電晶體作動時 ，一 L DD部的作用將如同電阻。因此，在不增大電晶體 的大小之下，可以降低互導性g m。相反地，除了該比較 電路之外，一 P —型MO S電晶體4 0 5形成一LDD 408，且此P —型MOS電晶體40 5的操作速度（互 .導性g m )並未降低。因此，在一I C內，只有位在比較 電路之負載側之M〇 S型電晶體的互導性gm降低，且可 以在不降低其它電路的特性之下將偏移電壓降低。 依據本發明之半導體裝置之第六實施例將詳細說明如 下。在以上的說明中，該P _型電晶體是設置在負載側且 該N -型電晶體是設置在差動側。但是，接下來的描述顯 示一比較電路內，.P -型電晶體是設成"差動電晶體而N -型電晶體是設成負載電晶體。 圖2所顯示的比較電路中，兩個N -型電晶體2 〇 3 、2 0 4是設成負載電晶體，而兩個P —型電晶體2 0 1 、2 0 2是被設成差動電晶體。該比較電路的其它部分的 說明將予省略，因爲這些部分的指示符號是與圖1之參照 號碼相同^與圖1類似，一偏移電壓在圖2內被算出，且 以下列公式表示。 本紙張尺度適用中國园家標準<CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項#填寫本頁) 裝·---！|訂>--- H 1· H ^1 I 線： 經濟部智慧財產局員工消費合作社印製 -18- 415074 A7 __B7___ 五、發明說明¢6 )Fill in V. /. This page is printed by I. The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy printed it more effectively so that the P-type transistor constituting the load side is set in a thick N-type well potential region to The impurity concentration of the channel region constituting the p-type transistor on the load side is set to be higher than the impurity concentration of the channel region constituting the N-type transistor on the differential side. Figure 7 shows the relationship between VTP and the channel impurity of each N-well potential concentration. For example, when VTP is set to 0.5V, in an N-well potential of 2X1012 (at'cm / cm2), the amount of channel impurities (boron) needs to be set to 6. 44X1011 (atom / cm2), and in In the N-well potential of 3 X 1 0 1 2 (atom / cm2), it needs to be set to 7, 4 7 X 1 0 1 1 (atom / cm2), and in a 3 X 1 0 1 2 (atom / cm2) In the N-well potential, it needs to be set to 9.5 7 X 1 0 1 1 (atom / cm2). As the concentration of the N_well potential increases, the amount of channel impurities increases:. If the mobility of the P-type transistor constituting the load side is less than the size of the constitutive paper, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. 15 A7 415074 _____B7__ V. Description of the invention 彳 3) (Please first (Please read the notes on the back and fill in this page again.) When moving the N-type transistor on the moving side, both the P-type transistor constituting the load side and the N-type transistor constituting the differential side can be set at N. ~ Within the well potential region. At this time, the difference between the impurity concentration in the channel region of the N-type transistor and the impurity concentration in the channel region of the P-type transistor can be made larger. Figure 8 shows the relationship between VTN and the amount of channel miscellaneous P-well potential concentration. For example, when VTN is set to 0.45V, in an N-well potential of 4 X 1 0 1 2 (atom / cm2), the amount of channel impurities (boron) needs to be set to 2 · 3 4 X 1 0 1 1 (atom / cm2), and in a 6 X 1 0 12 (atom / cm2) N-anion 1 potential, it needs to be set to 1. 9 X 1 0 1 1 (atom / cm2). Therefore, as the concentration of the P-well potential increases, the amount of channel impurities can decrease, so the difference in the impurity concentration increases. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the MOS transistor on the load side does not need to be set in the well potential area. A P-type well potential can be manufactured by using an N-type substrate, and a P-type transistor constituting a load-side transistor can be manufactured from an N-type silicon semiconductor substrate and constitute a differential-side transistor. An N-type transistor of the crystal can be fabricated from within the P-type well potential. In this example, the impurity concentration of the channel region constituting the P-type transistor on the load side can be successfully set to be higher than the impurity concentration of the channel region constituting the N-type transistor on the differential side. A fourth embodiment of the semiconductor device according to the present invention will be described in detail below. By setting the thickness of the gate oxide film of the M 0 S transistor on the load side to be thicker: when the gate oxide film of the M 0 S transistor on the differential side is thick, the offset voltage can be reduced: Interactive gm and the gate oxide film -16- This paper size applies to Chinese national standards (CNS > A4 size (210 X 297 mm)) Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 415074 A7 B7 V. Description of the invention (u ) Thickness is inversely proportional. Therefore, as the thickness increases, the mutual conductivity gm decreases. For example, when an oxide film with a thickness of 150 A is formed on the entire surface of a semiconductor substrate, the oxide film is only selectively The area where the MO S-type transistor on the differential side is formed is etched. The entire surface of the substrate is oxidized again to form an oxide film with a thickness of 20 Å. Therefore, the MO S-type on the differential side The thickness of the gate oxide film of the transistor is set to the thickness of the last oxidized oxide film, 200 A. The thickness of the gate oxide film of the MGS transistor on the load side is 1 50 + 200 A, which is about 30 0 Α. Therefore, the M 0 S transistor on the load side The interconductivity 'gm can be set smaller than the differential side. A fifth embodiment of the semiconductor device according to the present invention will be described in detail as follows. FIG. A cross-sectional view of a MOS transistor and a MOS transistor of a circuit 402 in addition to the comparison circuit. The comparison circuit 401 is composed of a N-type MO_S transistor on the differential side and a The P-type M 0 S transistor on the load side is composed of the N-type .M ◦ S transistor 4 0 4 ”on the differential side, with one side spaced 4 1 2 between the two gates 3 0 5 The low-concentration diffusion layer (N-LDD) 409 is a high-concentration diffusion layer (N + diffusion layer) called a source drain formed in a silicon substrate formed below the side gap. 3 0 4 is formed on the side of the low-concentration diffusion layer 4 0 9. Therefore, 'a so-called N-type LDD transistor is formed. In addition to the comparison circuit', a circuit N: -type MO S transistor 4 06 is also The same. L DD transistor. ------------- D equipment -------- Order --------- Wire < Please read the note on the back first Please fill in this page for matters Zhang scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm). 17 415074 A7 __B7 _____ V. Description of the invention (15) P-type MOS transistor 40 3 on the load side, the other side is spaced 4 12 is also formed on both sides of the other gate. However, a low-concentration diffusion layer (LDD) is not formed in the substrate below the side gap, and a so-called source-drain high-concentration The diffusion layer (P + diffusion layer) 3 0 3 is formed without overlapping the gate. When the P-type MOS transistor is constructed in the manner described above, when the P-type MOS transistor is operated, an L DD portion functions as a resistor. Therefore, without increasing the size of the transistor, the mutual conductivity g m can be reduced. In contrast, in addition to the comparison circuit, a P-type MOS transistor 405 forms an LDD 408, and the operation speed (mutual conductivity gm) of the P-type MOS transistor 405 is not reduced. Therefore, in an IC, only the transconductance gm of the MOS transistor located on the load side of the comparison circuit is reduced, and the offset voltage can be reduced without degrading the characteristics of other circuits. The sixth embodiment of the semiconductor device according to the present invention will be described in detail as follows. In the above description, the P_-type transistor is provided on the load side and the N-type transistor is provided on the differential side. However, the following description shows that in a comparison circuit, the .P-type transistor is set as a " differential transistor and the N-type transistor is set as a load transistor. In the comparison circuit shown in FIG. 2, two N-type transistors 2 0 3 and 204 are set as load transistors, and two P-type transistors 2 0 1 and 2 0 2 are set as differential. Power transistor. The description of the other parts of the comparison circuit will be omitted because the reference signs of these parts are the same as the reference numbers in FIG. 1 ^ Similar to FIG. 1, an offset voltage is calculated in FIG. 2 and expressed by the following formula. This paper size applies to the Chinese Gardener's Standard < CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first # Fill this page). | Order > --- H 1 · H ^ 1 Line I: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -18- 415074 A7 __B7___ V. Description of Invention ¢ 6)
Voff = |AVtp| + V~〇Kn/aKp)*AVtn + (^(β/α) - l)(Va - Vref -|vtp|) -(5) 在此，V t p表示構成差動電晶體之P -型電晶體 20 1的V t h，而V t η表示構成負載電晶體之N_型 電晶1|2 0 3之V t h。AV t p表示構成差動電晶體之P -型電晶體20 1、202間之Vt h的差。AV t η表示 構成負載電晶體之Ν-型電晶體2 0 3、2 0 4間之 V t h的差。Κρ表示該構成差動電晶體之Ρ —型電晶體 2 0 1的互導性gm。Κη表示該構成負載電晶體之Ν — 經濟部智慧財產局員工消費合作社印製 V裝--- (請先閱讀背面之注意事項#/皆寫本頁) -線· 型電晶體2 0 3的互導性gm。α表示構成差動電晶體之 Ρ —型電晶體20 1、202之互導性gm的比値。石表 示構成負載電晶體之N —型電晶體2 0 3、2 0 4之互導 性gm的比値。從公式（5 )需了解的是，可以充分的降 低負載電晶體的互導性g m以及增加差動電晶體的互導性 gm，俾使偏移電壓減小。因此，當電路內的偏移電壓減 小時，可以對於構成上述負載電晶體之'_N -型電晶體的互 導性g m的降低作一充分的測量。 如上所述，依據本發明，在一使用MO S型電晶體的 比較電路中，當位於負載側之Μ 0 S型電晶體的互導性 gm是被設置成小於位於差動側之MO S型電晶體的互導 性g m時，可在不增加電晶體的大小之下減小偏移電壓。 因此，可以·提供僅佔據小的面積之具有小的偏移電壓的比 較電路，這是習知的比較電路所無法達成的。另外，以上 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -19 - A7 經濟部智慧財產局員工消費合作社印製 415074 _B7___ 五、發明說明<7 ) 的效果可用於眾多的I C而降低成本，且該比較路可應用 於受制於晶片大小的I C。 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉Voff = | AVtp | + V ~ 〇Kn / aKp) * AVtn + (^ (β / α)-l) (Va-Vref-| vtp |)-(5) Here, V tp means a differential transistor V th of the P-type transistor 20 1, and V t η represents the V th of the N_-type transistor 1 | 2 0 3 constituting the load transistor. AV t p represents the difference in Vt h between the P -type transistors 201 and 202 constituting the differential transistor. AV t η represents the difference in V t h between the N-type transistors 2 0 3 and 2 0 4 constituting the load transistor. Κρ represents the transconductance gm of the P-type transistor 2 0 1 constituting the differential transistor. Κη indicates the N that constitutes the load transistor — V-printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs --- (Please read the precautions on the back # / all write this page)-Line type transistor 2 0 3 Mutual conductivity gm. α represents the ratio 互 of the mutual conductivity gm of the P-type transistors 201 and 202 constituting the differential transistor. Stone indicates the ratio 互 of the mutual conductivity gm of the N-type transistors 2 0 3, 2 0 4 constituting the load transistor. It should be understood from formula (5) that the mutual conductivity gm of the load transistor can be sufficiently reduced and the mutual conductivity gm of the differential transistor can be increased, thereby reducing the offset voltage. Therefore, when the offset voltage in the circuit is decreased, it is possible to make a sufficient measurement of the decrease in the conductivity gm of the '_N-type transistor constituting the load transistor described above. As described above, according to the present invention, in a comparison circuit using a MO S-type transistor, the transconductance gm of the M 0 S-type transistor on the load side is set to be smaller than that of the MO S-type on the differential side. With the transconductance gm of the transistor, the offset voltage can be reduced without increasing the size of the transistor. Therefore, it is possible to provide a comparison circuit with a small offset voltage which occupies only a small area, which cannot be achieved by the conventional comparison circuit. In addition, the above paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -19-A7 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 415074 _B7___ V. The effect of the invention < 7) can be used for Many ICs reduce the cost, and the comparison circuit can be applied to ICs that are limited by the chip size. -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)