TW413902B - Method for forming landing pads - Google Patents

Abstract

A method for forming landing pads comprises: providing a substrate deposited with an insulated assembly layer, wherein the assembly layer includes a top dielectric layer, a middle dielectric layer and a bottom dielectric layer, and the etching rate of the bottom dielectric layer is lower than that of the top dielectric layer; etching a part of the top dielectric layer isotropically so as to form a lateral etching profile which is the opening of the top region of the landing pad; etching a part of middle dielectric layer and bottom dielectric layer anisotropically so as to form the opening of the bottom region of the landing pad; depositing a polysilicon layer in the opening of the landing pad to form the landing pad structure; and using, for example, chemical mechanic polishing method to remove the excessive polysilicon layer, thereby obtaining a flattened surface for the subsequent semiconductor manufacturing process.

Description

413902 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a semiconductor integrated circuit manufacturing process, and particularly to an improvement method for forming a land pad structure in the integrated circuit β 5- 2 Background of the Invention: Design criteria for integrated circuit design (de s gn ru 1 e) need to be able to prevent integrated circuits from generating destructive errors in different manufacturing processes and ensure electrical parameters of the components. The electrical variable system is related to the characteristics of physical dimensions. There must be certain characteristic sizes and reduced space or design tolerances between the components, so that the shape and size of the electrical accumulation of the components may be exposed with the alignment error of the mask or the exposure of the photoresist. Change. So there are already several design guidelines that apply to the different types of substances used and the specific locations of the components on the wafer. For example, several design criteria apply to metal, diffused and polycrystalline silicon materials, and contact window openings, such as the space where metal is used to contact the gate. Any misalignment during the formation of a metal contact window, such as the connection to the diffusion region, may cause the required space to be misaligned. This required space is, for example, between the contact window and a surrounding element. This surrounding element For example, it is a polysilicon gate. Therefore, for special materials, & 'even if the required space is reduced, it may not meet the design tolerance and ensure the electrical characteristics of the device.

413902 V. Description of the invention (2) In order to avoid the problem caused by the misalignment of the metal contact window or other space configuration problems of the contact window and the gate, it is necessary to form a landing between the metal contact window and the diffusion area below. pad. Traditionally, the landing plutonium is located on a doped polycrystalline silicon layer, which includes a silicide layer formed thereon to reduce the sheet resistance to a tolerable level. For polycrystalline silicon, because the design guidelines for the space in contact with the gate are less stringent, the use of a landing pad can reduce the size of the cell (ce 11) region and improve the problem of alignment errors. The first A to D diagrams show a conventional method for forming a land pad < Please refer to FIG. A, forming a gate 12a and a spacer 1 12B on a substrate 100. Then, a silicon oxide layer 12 is formed on the substrate 100. A photoresist layer 14 is formed on the oxidative breakdown layer 120, and the photoresist layer 14 has a pattern of a landing pad structure. Then, the silicon oxide layer 1 20 is etched with the photoresist layer 1 40 as a mask to form a land opening. 1 30, and then remove the photoresist layer 4O, as shown in the first B diagram. Then, a polycrystalline silicon layer 150 is deposited in the landing pad opening i 30, as shown in the first C diagram. A step of etchback is performed to form a landing pad ′ as shown in the first D 圊.

The second figure shows the wafer land pad, the contact window, and the metal-oxide semiconductor conductive crystal. In this figure, the 'dashed line X-X' is perpendicular to the gate and the dotted line is parallel to the gate. According to the second figure, the size of the contact window area is smaller than the landing pad D

413902 V. Description of the invention (3) " --- However, a problem encountered by traditional landing pads is that the alignment adjustment shift (AA_shift; caused by alignment adjustment) will cause contact when forming the connection. The overlap of the window with the active region or the contact window with the gate electrode is shown in Figures A and B. The third diagram A is shown in the conventional technology: When the? N is touched, the alignment adjustment offset of the direction produces an alignment error, the schematic cross-sectional view of the land pad. The third diagram B in the conventional technology, 雔 = y], the alignment adjustment error caused by the alignment error: when the intention is to ... cause a short circuit between the contact window and the active area or a short circuit between the contact and the gate electrode . Furthermore, since the contact area of the land pad becomes smaller, the contact resistance is increased. / 、 5-3 Purpose and summary of the invention: = The above-mentioned invention background order, the traditional manufacturing process is guaranteed to be used for a form of land pad, which can be substantially separated from the active area or the gate electrode. 、 No contact when shifting = = When the contact window has a large alignment adjustment bias

Gold-oxygen semiconducting crystal 413902 V. Description of the invention (4) This combined layer includes _ the dielectric layer and the bottom dielectric layer; the top and bottom dielectric layers have a higher etch rate than the top dielectric layer. Isolate 'and the top of the contact portion of the bottom dielectric layer is low. Isotropic (etching) is etched to the contour A of the etched layer A: layer 'to form the contour of the side etched, which faces the opening in the top region of the side-etched-portion of the fresh ridge. The non-isotropic ground layer is the bottom of the second layer. The electrical layer and the bottom dielectric layer are used to form a land pad structure. A conductor layer is deposited in the opening of the landing pad to form a 5-4 diagram. Brief description: ^ The points will be shown in the following embodiment and the flow chart A: The drawing shows traditionally a kind of circular shape, a contact window, and an intraoperative 'when the contact window is in the second position. Schematic. … When the misalignment is adjusted to adjust the offset, the cross-section of the landing pad is directed to the conventional technology command ’when the contact window is in the second picture,“. When the alignment adjustment is offset, the cross-sectional schematic diagram of the landing pad is the fourth A to four {) 圏 'L · 〇α U is not a surface of the present invention forming a land pad structure. Page 7 413902 5 2. Description of the invention (5) Schematic sectional view of the manufacturing process. The fifth diagram A is a schematic cross-sectional view of the landing pad in the conventional technique when the alignment adjustment offset of the contact window in the x-x 'direction of the second diagram is shifted. Fig. 5B. In the conventional technique, when the contact window generates an alignment adjustment offset in the y-y 'direction of the second picture, the representative symbol of the main part of the cross-sectional schematic diagram of the landing pad: 10' 100 substrate 12A, 112A Gate 12B, 112B bulkhead 20 bottom layer 22 middle layer 24 top layer 40, 42, 140 photoresist layer 60, 160 landing pad 120 silicon oxide layer 130 landing pad opening 150 polycrystalline silicon layer 5-5 Detailed description of the invention: Hereinafter, several embodiments of the present invention will be listed in detail. However, the present invention

413㈣ V. Description of the invention (6) is still widely applicable to other embodiments, and the scope of the present invention is not limited thereto except as specifically indicated in the scope of patent application. Please refer to the fourth A to four D drawings', which show cross-sectional views of a manufacturing process for applying a combination layer to form a land pad. Referring to FIG. 4A, a substrate 10 is provided, which has a combination layer composed of a tri-layer dielectric insulating layer. The combination layer includes a top layer 24, a bottom layer 20, and an intermediate layer 22. A photoresist layer 40 is then formed on the combined layer.

Because the etching rate of the bottom layer 20 of the method of the present invention is lower than that of the top layer 24, the preferred material of the bottom insulating layer 20 is an oxide formed by using a conventional atmospheric chemical vapor deposition method or a low pressure chemical vapor deposition method. Broken, as long as the money engraving rate of the bottom layer 20 is lower than the top layer 24. The thickness of the bottom layer 20 is between about 4000 and 5000 angstroms. ~ B The intermediate layer 22 plays the role of an etching stop layer. The material is, for example, silicon nitride, to prevent the contact opening pattern on the top from being etched through, which may cause contact with the active area or the gate electrode below. As a combination layer (-part of the dielectric layer) and the etching characteristics of silicon nitride are different, so although other materials can also be used as the stop layer for money carving, the better material is still nitride nitride. In other words 'Using the nitrided sand material, a selective etching process can be applied to the substance selected in the underlying layer.

$ 9 页 413902 V. Description of the invention (7) ---- Cheng Yueying :: The best method for siliconizing the layer is plasma gain chemical vapor deposition, and its preferred thickness is between 60 and 90 angstroms. between. β because the method of the present invention 'the top layer 24 has a higher remaining rate than the bottom layer. A preferred material for the samarium insulation layer 24 is a samaritan fossil formed using a conventional plasma gain chemical vapor deposition method, as long as the surname engraving rate of the top layer 24 is south of the bottom layer 20. The thickness of the top layer 24 is between about 400 and 500 Angstroms. The pattern of a top area of the landing pad was then transferred to a photoresist 40. The size of the top area needs to be large enough so that the contact window can easily land on the landing pad. It is worth noting that in the fourth A picture, the elements including some substructures are located on or in the substrate 10 and / or the metal layer. The fourth A diagram of this embodiment shows the gate electrode 12A and the spacer 12B of the metal-oxide semi-conductive crystal (Mos). Then, 'the pattern of a landing pad is transferred to the photoresist layer 40 by any conventional method such as lithography. Then, using the photoresist layer 40 as a mask, the top dielectric layer 24 is isotropically etched by any conventional dry etching technique, as shown in the figure. Because the material of the top dielectric layer 24 is relatively loose, there will be side etching during the isotropic etching process. Page 10 413902 V. Description of the invention (8) ~ Next, 'the photoresist layer 40 is used as a mask', and the intermediate layer 22 is etched with a conventional vaporized silicon recipe. Subsequently, the bottom layer 20 is anisotropically etched with the photoresist layer 40 as a mask. This etching process is performed in an oxide etcher, and a traditional etching recipe is used. Then, “remove the photoresist layer 40 to form a land pad opening, and deposit a polycrystalline silicon layer 50 as shown in FIG. 4C” to fill the landing pad opening. Any conventional method for forming this polycrystalline silicon layer 50 is appropriate. Then, the polycrystalline silicon layer 50 is flattened to form a landing pad 60 as shown in the fourth D diagram. Please refer to Figure 5A and Figure 5. With the help of the silicon nitride layer, the silicon nitride layer will be used as the stop layer for the formation process of the contact window opening even if the alignment adjustment offset occurs in the subsequent process steps. . The above is only the preferred embodiment of the present invention & ™ determining the scope of patent application of the present invention. , And η patents. Any modification or modification shall be included in the following application

Claims (1)

413902 VI. Application for Patent Scope 1. A method for forming a part of a semiconductor integrated circuit, comprising: providing a substrate on which an insulating combination layer is deposited, the combination layer including a top dielectric layer, an intermediate dielectric An electrical layer and a bottom dielectric layer, wherein the top dielectric layer and the bottom dielectric layer are insulated from each other by the intermediate dielectric layer, and the bottom dielectric layer has a lower surname than the top dielectric layer Etch rate; isotropically etch a portion of the top dielectric layer to form a laterally etched contour that is an opening in a top area of a landing pad; etch a portion of the intermediate dielectric layer; and anisotropic A portion of the bottom dielectric layer is etched to form an opening in a bottom region of one of the landing pads. 2. The method according to item 1 of the scope of patent application, wherein the material of the top dielectric layer includes silicon oxide formed by atmospheric pressure chemical vapor deposition. 3. The method according to item 1 of the scope of patent application, wherein the material of the top dielectric layer includes silicon oxide formed by a low pressure chemical vapor deposition method. 4. The method according to item 1 of the scope of patent application, wherein the material of the bottom dielectric layer includes silicon oxide formed by a plasma gain chemical vapor deposition method. 5. The method as described in item 1 of the patent application scope, wherein the intermediate dielectric layer is a stop layer. Page 12 413802 6. Scope of patent application 6. The method described in the scope of patent application No. 1 and the material sentence of the interlayer dielectric. Including siliconized silicon, medium and medium 7. As described in scope of patent scope 1 In the method, the conductor layer is filled in the top area of the landing pad, and moreover, a deposit is included. In the bottom region of Xingyuan Kai 8, the method described in item 7 of the scope of patent application, Ganshan quality includes polycrystalline silicon. A material for the conductor layer 9. A method for forming a composite layer including a method in which the top portions are insulated from each other, an etching rate; an isotropic-part of a semiconductor integrated circuit substrate, a _ ^ is deposited on the substrate Insulated combination layer, the group of people; '•, an intermediate dielectric layer and a bottom dielectric layer, two electrical f /, the bottom dielectric layer is through the intermediate dielectric layer' and 4 bottom dielectric layers Has a lower engraved profile than the top dielectric layer, the money engraved is a non-isotropic land pad and a bottom region is opened at the bottom of the top dielectric layer to form a lateral etch profile as a landing A pad-top area opening; a portion of the intermediate dielectric layer; a portion of the bottom dielectric layer is etched to form the landing area opening; and a conductor layer is filled in the top area opening of the landing pad and the 〇 〇 Page 13 V V 6. Patent application scope 10. The method according to item 9 of the patent application scope, wherein the material of the top dielectric layer includes silicon oxide formed by atmospheric pressure chemical vapor deposition. 11. The method according to item 9 of the scope of patent application, wherein the material of the top dielectric layer includes silicon oxide formed by a low-pressure chemical vapor deposition method. 1 2. The method according to item 9 of the scope of patent application, wherein the material of the bottom dielectric layer includes silicon oxide formed by a plasma gain chemical vapor deposition method. 1 3. The method according to item 9 of the scope of patent application, wherein the material of the bottom dielectric layer includes silicon oxide. 14. The method according to item 9 of the scope of patent application, wherein the intermediate dielectric layer is a stop layer. 1 5. The method according to item 9 of the scope of patent application, wherein the material of the intermediate dielectric layer includes silicon nitride. 16. The method according to item 9 of the scope of patent application, wherein the material of the conductor layer comprises polycrystalline silicon. 17. A method of forming a part of a semiconductor integrated circuit, comprising: providing a substrate on which an insulating composite layer is deposited, the composite layer including a top dielectric layer, an intermediate dielectric layer, and a bottom dielectric Electrical layer, Page 14 413902 VI. Scope of patent application --- where the top dielectric layer and the bottom dielectric layer are insulated from each other, and the bottom dielectric layer has a lower etching rate than the top dielectric layer; the t layer has a lower A photoresist layer is formed on the combined sound, where β. = Li Shangdan τ reading photoresist layer has an opening of Ying Luying, or the isotropic etching of the part that is not covered by the photoresist layer a In order to form a lateral etching contour, the contour is two of one landing.卩 divided field openings; A ·-the top dielectric etches the intermediate dielectric layer not covered by the second photoresist layer; the anisotropic etch the bottom dielectric not covered by the second photoresist layer to form the landing A bottom region opening of one of the pads; and an electrical layer and the deposition-conductor layer are filled in the top region of the landing pad to open a bottom region opening. 18 'The method as described in item 17 of the scope of the patent application, wherein the material of the top dielectric includes silicon oxide formed by an atmospheric pressure chemical vapor deposition method. 19 ' The method as described in item 17 of the scope of patent application, wherein the material of the top dielectric comprises < silicon oxide in a low pressure chemical vapor deposition method. 2〇, ». Evening method’ wherein the bottom medium a 0 described in the scope of patent application No. 17 of the M method to form a 41 gas π electric layer holding layer includes oxidized hair formed by plasma gain chemical vapor deposition. 21. · + · Method, in which the intermediary Mi • If the scope of patent application No. 17 7 households ^ electricity 413802 16th I