TW413901B - Manufacturing method of self-aligned contact - Google Patents

Abstract

There is disclosed a method for forming openings in the DRAM device. The opening can be, for example, the self-aligned contact window. The method comprises: providing a dielectric layer; forming patterned photo-resist on the dielectric layer; using C5F8 etching agent to etch the dielectric layer; and removing the photo-resist. The opening has a perfect profile.

Description

413901 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a DRAM opening, and more particularly to a method for manufacturing a self-aligned contact (SAC). 5-2 Background of the Invention:

In the manufacturing process of the DRAM cell, the metal oxide semiconductor jMOS transistor is formed first, and then the formation process of the important insulating layer, the contact window for etching, and the interconnection structure is continued. Self-aligned contact window (SAC) is a well-known technique and is often used to form an opening that connects a substrate to a capacitor. _ Automatically align the dielectric gate (or top of the part to Pad). In addition, precision. In the above-mentioned moment, the residual of the reaction is 0 * 2 6 micrometers, and the capacitor is affected. Please refer to the engraving between two identical elements. The above-mentioned components such as the opening are usually made of the dielectric layer by Lu Yi (1 and ing. The formation process of the opening is more etched, which will cause the diameter of the opening to exceed the contour of the opening. Too much will not suffer too much when less than 0.26 microns,

The contact window uses an etching process, and the etching layer 'forms an opening. The bit line (bit-1 ine) β of this open substrate or is connected to the substrate through the guidance of the gap wall can make the traditional process containing C4H8 residues inside the opening during the etching process, this accumulated residue; = The first picture of the electrical contact of the landing pad under the shadow. When the diameter of SAC01 is 413901 V. Description of the invention (2), the outline of SAC01 will become a sharp opening. Therefore, the bottom of SAC (H has only a relatively small area. Even more unfortunate is that because SAC01 only has a small area bottom, the capacitors formed in subsequent processes can only connect the landing pads 02 through a small area. Therefore, the resistance value of mDRAM will be increased. 5-3 Invention Purpose and summary: In view of the above-mentioned background of the invention, the disadvantages caused by the traditional manufacturing process' require a method for forming SAC, so as to provide a good opening profile called ^ and make a good distance between the capacitor and the land pad of the conductive substrate. The electrical contact has proposed a door that can obtain a good profile in nature. Ϊ f contact window opening manufacturing method, and capacitors and landing pads, a good contact window The mouth is connected to the substrate. In one embodiment, a first dielectric layer is formed on the substrate, and then the first dielectric layer is leaned against the spacer. Then, a cfW pattern photoresist is formed on the second dielectric layer on the conductor. After the use of "inclusive" money etchants to etch the above two dielectric layers. Finally, the photoresist is removed. 5-Schematic illustration of the schematic diagram-The figure shows an automatic alignment with a sharp contour Difference of quasi-contact window

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Representative symbols of main parts: 01 contact window ^ landing pad 10 semiconductor substrate 11 source / drain structure 20 first dielectric layer landing pad 40 bit line structure 41 gap wall 42 isolation layer 43 conductive layer 44 polycrystalline silicon layer 50 The second dielectric layer 60, the photoresist layer 70, and the contact window openings 5 to 5 are described in detail in the invention: h Referring to the second figure, a first dielectric is deposited on the semiconductor substrate 10, where a landing pad 30 has been formed on the semiconductor substrate 10. A standard source / drain structure is formed on the bottom 10, and is connected to the road 413901. V. Description of the invention (4) Pad 30. The above-mentioned first dielectric layer 20 is used to isolate the substrate 10 from a bit line to be formed later, and the first dielectric layer 20 is generally used as an inner polycrystalline silicon dielectric layer (IPD). This first dielectric layer 20 can be fabricated by using any typical and well-known IPD dielectric material 'while silicon dioxide is used in this embodiment. In this embodiment, the thickness of the first dielectric layer 20 ranges from about 5000 angstroms to about 6000 angstroms, and is usually formed by a conventional chemical vapor deposition (CVD) process. Traditional technology, in the structure 40. The bit line junction stone layer 44 and the conductive layer 43 are tungsten silicide (WSi), and the spacer wall 41 in the bit line structure 40 is used for alignment. This gap is like silicon nitride, and this layer is then deposited on the redundant electrical layer 20-any typical and range of thickness of the material layer 50 used in the crystalline example. The deposition method is for the traditional electrical layer 50 system The structure 40 for isolating a dielectric layer 20 has a stack and an isolation layer 42. The material sidewalls of the isolation layer 42 are further shaped. The subsequent contact window wall 41 may be first etched by the gap wall 41. Next, a dielectric layer 50 is formed. Known for wafer manufacturing is silicon dioxide. A chemical vapor deposition of about 500 angstroms will be formed later. Please refer to the third figure. The structure of at least one-bit wire junction is formed on the surface. It usually includes a polycrystalline material such as the conductive layer 43. It is silicon nitride (S i N).成 sidewall gap wall 41. Here, when it is formed, it can be easily manufactured by any suitable material, which is more suitable for the dielectric layer structure 40 and the first dielectric layer 50 than the first dielectric layer 50, which is usually deposited by blanket deposition. Electrical material, and in this embodiment, in this embodiment, the second dielectric is between 6000 angstroms and its better CVD process. This second dielectric capacitor. 413901 V. Description of the invention (5) Using a known lithography technique 60, 70 in the second dielectric layer 50 extends down to the landing pad 30. The land pad 30 is electrically connected to the bottom using the second to Four pictures of conductive substances. The contact window opening is used to reach the contact window forming window opening 70 extending along the side wall gap portion ′ and thus forming the contact window opening (SAC). Operation and matching to form the contact surface. The window opening 70 on the wall 41 formed by the opening 70 shown in the base 10 'is the same as the fourth window opening 7 〇 As the contact will be familiar, it will be used during the contact period. The downward extension is usually regarded as shown in the figure. The contact window opening 7 〇 The artist window opening 7 〇 The above window is extended to the next time and then the photoresist layer window is automatically aligned. The contact window on the top of the contact pad of the full gap wall 41 is preferably “etched” to increase the last name of the nitrogen. The contact window is selected from 0.2 to 0.22. The contact window is filled with conductive 70 according to the book of the present invention. Guided integrity. The openings 70 are formed by dry etching using an anisotropic etching process, such as standard DSAC etching. The CSF8 in this agent replaces the conventional QF8 to etch the spacer 41 of the second dielectric silicon and the second dielectric layer 50 of the oxide. Especially for SACs with VLSI circuits having a diameter of less than 0.26 mm, the SAC formed according to the present invention has a contour, and the conventional spike-shaped contour can be avoided. Furthermore, the SAC formed by the method has no problem of the etchant remaining. Deposition, using a standard process to contact the window electrical material, this process is not described in detail here, but this does not affect the implementation of the layer between 50 and even necessary, root D to affect its

413901 V. Description of the invention (6) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; any other equivalent changes made without departing from the spirit disclosed by the present invention Or modifications should be included in the scope of patent application described below.

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Claims (1)

413901 VI. Application for Patent Scope 1. A method for forming an opening in a DRAM, comprising: providing a dielectric layer; forming a patterned photoresist on the dielectric layer; using a scriber containing C5F8 to etch the dielectric Electrical layer; and removing the photoresist. 2. The method of claim 1 in which the opening includes a via window opening. 3. The method of claim 1 in which the opening includes a contact window opening. 4. The method of claim 1, wherein the material of the dielectric layer includes an oxide. 5. A manufacturing method for automatically aligning a contact window opening, comprising: forming a first dielectric layer on a substrate; forming a conductive layer on the first dielectric layer, and forming a conductive layer against the conductive layer. A spacer; forming a second dielectric layer on the conductive layer; forming a patterned photoresist on the second dielectric layer; using a #etcher silver including C5 F8 to etch the first dielectric layer and the A second dielectric layer; and removing the photoresist. Page 10 413901 6. Scope of Patent Application 6. The method of claim 5 in which the material of the first dielectric layer includes an oxide. 7. The method of claim 5 in which the material of the conductive layer includes tungsten silicide (WSi). 8. The method of claim 5 in which the conductive layer includes a bit line. 9. The method of claim 5 in which the material of the conductive layer includes tungsten silicide (WSi). 10. The method according to item 5 of the scope of patent application, wherein the material of the conductive layer includes polycrystalline silicon. 11. The method of claim 5 in which the material of the spacer comprises silicon nitride (SiN). 1 2. The method of claim 5 in the patent application range, wherein a diameter of the opening of the self-aligning contact window ranges from 0.2 / zm to 0.22 / zm. 1 3. The method of claim 5 in which the material of the second dielectric layer includes an oxide · oxide. Page 11 413901 6. Application for Patent Scope 1 4. The method according to item 5 of the patent application, wherein the etchant includes argon (Ar). 15. The method of claim 14 in which the argon is used to impinge and remove the remainder of the etching reaction. 16. The method of claim 5 in which the first dielectric layer and the second dielectric layer are engraved with a dry name. Page 12