TW413875B - Pad structure of stacked chips - Google Patents
Pad structure of stacked chips Download PDFInfo
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- TW413875B TW413875B TW088105992A TW88105992A TW413875B TW 413875 B TW413875 B TW 413875B TW 088105992 A TW088105992 A TW 088105992A TW 88105992 A TW88105992 A TW 88105992A TW 413875 B TW413875 B TW 413875B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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Abstract
Description
413875 五、發明說明（1) 【發明領域】 有 :0 ^ Ϊ t ^係有關於一種堆疊晶片之焊墊構造，特別皋 於被堆疊晶片之焊墊構造。 【先前技術.】 習=曰曰片堆疊封裝體包含一第一晶片及一第二晶= ί二=姆堆叠於該第二晶片上，该木 =二晶片上時，必須將趙-m蠢控制 砮用# 少時’在該第—晶片及第二晶片 造成^ 程如封膠製裎之困*，並在第一晶片及j晶片有<能殘 ，氣泡〔V〇U〕或填不滿〔incompi ete pi 11 ing〕情況 若=膠量太多而使點膠塗佈區域過大，當該第一晶月及第 vfe & # ^ D時，使該第一晶片及第二晶片之間之膠溢出， 覆蓋或污染於該第二晶片之燁塾上，該被污染 塾上打線〔“rebonding〕的問題：：=無、 之焊墊遠離該第一晶片側邊之溢膠區以避面' 、=汰一晶 則該第二晶片之焊墊有被污染的可能。然而，豸：采，否 之焊墊遠離該第一晶片側邊之溢膠區往往有該第Λ f 了晶片 大及第二晶片過小的限制，因而無法達成該第二曰曰曰片過 塾無法遠離碑第一晶片侧邊溢膠區之目的。 日日之焊 19?8年_2月24白、頒予福格等人[F〇gal et ai.〕 專利弟5, 7 21，4i_2鸾揭示一基板！ 〇 Ο v，如第一圖所八，、國 板100至少包含一上晶片101 ，該上晶片1〇1寬度小^於’—該基 晶片102相對兩侧焊墊]〇4之距離。該上晶片1〇1以數個=413875 V. Description of the invention (1) [Field of invention] Yes: 0 ^ Ϊ t ^ relates to a pad structure for stacked wafers, especially for the pad structure of stacked wafers. [Prior art.] Xi = The chip stack package includes a first wafer and a second crystal = ί 二 = stacked on the second wafer, when the wood = two wafers, Zhao-m must be The control application # 时时 'creates a problem in the first wafer and the second wafer, such as the sealing process, and there is < capacity remaining, bubbles [V〇U] or filling in the first wafer and the j wafer. Dissatisfaction [incompi ete pi 11 ing] If the amount of glue is too large and the dispensing coating area is too large, when the first crystal moon and the vfe &# ^ D, make the first wafer and the second wafer Some glue overflows, covers or contaminates the second wafer, and the problem of "rebonding" on the contaminated wafer :: None, the solder pads are far away from the overflow area on the side of the first wafer. To avoid the surface, and to eliminate a crystal, the pad of the second wafer may be contaminated. However, 豸: minus, if the pad is away from the overflow area of the side of the first wafer, there is often the first wafer. The limitation of the large and the second wafer is too small, so that the purpose of the second wafer cannot be far away from the glue overflow area on the side of the first wafer of the tablet. Sun's welding 19-8 February 24th, awarded to Fogg et al. [F〇gal et ai.] Patent brother 5, 7 21, 4i_2 鸾 Reveals a substrate! 〇OV, as shown in Figure 8 The national board 100 includes at least one upper wafer 101, and the width of the upper wafer 101 is smaller than the distance between the pads on opposite sides of the base wafer 102. The upper wafer 101 has a number of =
C:\Prograni Files\patent\PK6669. ptd 第 4 頁 413875 五、發明說明（2) ' '~ 體103懸於該下晶片1〇2上，且該上晶片1〇1可旋轉一角度 仍使該上晶片101不會遮擋該下晶片1〇2之焊墊j 〇4，使該 焊墊1 0 4可供數條導線1 〇 5進行打線。該上晶片丨〇丨及下晶 片102之間則存在一膠層,，該膠層1〇6供該上晶片1〇1固 定於下晶片102上。另外ll 9 9 9年-泛月23日頒予福格等人 〔Fogal et al.〕之美國專利第5,8L4,78』號^示一4板 200 ’如第一圖所示’該基板2〇〇至少包含一上晶片2〇1， 該上晶片2 0 1寬度小於一下晶片2 〇 2相對兩侧焊墊2 〇 3之距 離。該上晶片2 0 1固定於該下晶片i 〇 2上，且該上晶片2 可旋轉一角度仍使該上晶片2〇1不會遮擋該下晶片2〇2之焊 塾203 ’使該焊墊2 03可供數條導線2 04進行打線。該上晶 片201及下晶片2 02之間則存在一膠層205，該膠層2 05供該 上晶片201固定於下晶片202上。按，該第5,721,452號之 膠層106可能污染焊墊1〇4及第5, 8 74, 781號之膠層205可虎 污染焊墊203 ’因而造成該焊塾1〇4，203無法進行打線 有鑑於此’本發明之堆疊晶片之焊墊構造改良上述之缺 點’其將在該焊塾上設一态权〔stud bump〕，由於該凸 柱凸出於溢膝體上而不被污染’因而使該導線打至該凸柱 上’因此’本發明可避免無顧^題。 【發明概要】 本發明主要目的係提供一種堆疊晶片之焊墊構造，其被 堆疊晶片設有避免被溢膠污染之焊塾，而具有較佳產品可 靠度之功效。 根據本發明之堆疊晶片封裝體，其主要包含一基板、一C: \ Prograni Files \ patent \ PK6669. Ptd page 4 413875 V. Description of the invention (2) '' ~ The body 103 is suspended on the lower wafer 102, and the upper wafer 101 can be rotated by an angle so that The upper wafer 101 does not cover the pad j 0 of the lower wafer 102, so that the pad 104 can be used for wiring of several wires 105. An adhesive layer exists between the upper wafer 丨 〇 丨 and the lower wafer 102, and the adhesive layer 10 is used for the upper wafer 101 to be fixed on the lower wafer 102. In addition, US Patent No. 5,8L4,78 issued to Fogg et al. [Fogal et al.] On September 23, 1999-shown on a 4 board 200 'as shown in the first figure' 2000 includes at least one upper wafer 201, and the width of the upper wafer 201 is smaller than the distance between the lower wafer 200 and the pads 203 on both sides. The upper wafer 201 is fixed on the lower wafer 〇2, and the upper wafer 2 can be rotated by an angle so that the upper wafer 021 does not block the welding pad 203 of the lower wafer 002 to make the welding Pad 2 03 can be used to wire several 04 2 wires. There is an adhesive layer 205 between the upper wafer 201 and the lower wafer 202, and the adhesive layer 205 is used for fixing the upper wafer 201 to the lower wafer 202. According to this, the adhesive layer 106 of No. 5,721,452 may contaminate the pad 104 and the adhesive layer 205 of No. 5, 8 74, 781 may contaminate the pad 203 ', thus making the solder pads 104, 203 unable to wire. In view of this, 'the pad structure of the stacked wafer of the present invention improves the above-mentioned disadvantages', it will set a stud bump on the welding pad, and the bump is not contaminated because it protrudes out of the overflow knee. Therefore, the wire is hit on the convex post 'so' the present invention can avoid no problem. [Summary of the Invention] The main object of the present invention is to provide a pad structure for stacked wafers. The stacked wafers are provided with welding pads to avoid contamination by overflowing glue, and have better reliability. The stacked chip package according to the present invention mainly includes a substrate, a
C:\Program Files\patent\PK6669.ptd 第 5 頁 413875C: \ Program Files \ patent \ PK6669.ptd page 5 413875
第 片 一 B 访楚第一晶片、一第一膠層及一第二膠層，該第 以；窠-：廢7膠層黏貼固定於該基板上，而該第二晶片 =第-J層黏貼堆疊於該第一晶片以形成一半導體堆疊 ^ 該 曰曰片及第二晶片各設有數個第一焊墊及第二 焊塾’該數個第一焊墊露出於該第二晶片兩侧且在該第一 知墊上各設有一感接供 導線打線，由於該免與之高度緣扃 站喑染。數條導線則連接該第一晶片 之第一焊墊與該基板之焊墊，及第二晶片之第二焊墊與該The first piece B visits the first wafer, a first adhesive layer, and a second adhesive layer. The first is: 窠-: the waste 7 adhesive layer is adhered and fixed on the substrate, and the second wafer = the -J layer Adhesively stacked on the first wafer to form a semiconductor stack ^ The first wafer and the second wafer are each provided with a plurality of first pads and second pads; the first pads are exposed on both sides of the second wafer In addition, each of the first sensing pads is provided with a sense contact for conducting wires, because the height of the contact pads is not affected by the height. Several wires connect the first pad of the first chip and the pad of the substrate, and the second pad of the second chip and the pad.
基板之焊墊以形成一通路。.The pads of the substrate form a via. .
由於本發明第一晶片之第一焊墊設有凸柱，因此，並不 需要顧慮第二膠層用膠量太多，因而一方面可避免用膠量 太少所造成在該第二膠層内殘留空隙或氣泡的問題，另一 方面避免溢膠污染該第一焊墊之凸拄，本發明具有提高g 品可靠度之功效ο I 【圖式說明】 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯特徵，下文特舉本發明較佳實施例，並配合所附圖式， 作詳細說明如下。 第1圖：美國專利第5, 72 1, 45 2號堆，晶片之示意圖； 第2圖：美國專利第5, 874, 781號堆疊晶片之示意圖； 第3圖：本發明較佳實施例堆疊晶月之上視圖；及 第4圖：本發明第3圖沿4 一 4線剖面圖。Because the first pad of the first wafer of the present invention is provided with a protruding post, there is no need to worry about the excessive amount of glue used in the second adhesive layer, and on the one hand, it can be avoided that the amount of glue used in the second adhesive layer is too small. The problem of remaining voids or air bubbles in the inner side, on the other hand, to avoid overflowing glue from contaminating the bumps of the first pad. The present invention has the effect of improving the reliability of the g product. I [Schematic description] In order to make the above and other purposes of the present invention , Characteristics, and advantages can be more obvious characteristics, the preferred embodiment of the present invention is given below, and in conjunction with the accompanying drawings, the detailed description is as follows. FIG. 1: Schematic diagram of US Pat. No. 5, 72 1, 45 2 stack, wafer; FIG. 2: Schematic diagram of US Pat. No. 5, 874, 781 stacked wafer; FIG. 3: Stacking of the preferred embodiment of the present invention A top view of the crystal moon; and FIG. 4: A sectional view taken along line 4-4 of FIG. 3 of the present invention.
【圖號說明JI 100基板 101第一晶片[Figure number illustrates the first wafer of JI 100 substrate 101
C:\Program Files\patent\PK6669. ptd 第 6 頁 413875 五、發明說明（4) 103 柱體 104 106 膠層 200 基板 201 203 焊塾 204 300 基板 301 303 第一膠層 304 306 凸柱 307 焊墊 105 導線 第一晶片 202 唆 一 承一 晶片 導線 205 膠層 第一晶片 302 第二 晶片 第二膠層 305 第一 焊墊 第二焊墊 308 導線 3 Ο 9 溢膠 31 Ο 焊墊 【實施例說明】 請參照第三及四圖所示，本發明較佳實施例主要包含一 基板30 0、一第一晶片301、一第二晶片302、一第一膠層 303及一第二膠層304，該第一晶片301以該第一膠層303黏 貼固定於該基板303上，而該第二晶片302以該第二膠層 304黏貼堆疊於該第一晶片301以形成一半導體堆疊構造。 該第一晶片301及第二晶_片302各設有數個第一焊 第二焊塾3〇7，該數個第一焊美^〇6熗出於該第二晶片3〇2 兩側且在該第一焊墊305上各設有一凸柱306供導線308打 …線，由於該凸柱30 6之高度凸出於該第一晶片1 〇 j之表面， --因而該凸柱3 06可避免沿該第一晶；（1〇丨’表面部溢之溢膠 30 9所造成的污染《該凸柱3 0 6之材料較佳採用為金。^數 個第二焊墊3 07則位於該第二晶片3 0 2四周供導線3〇8打/線 。位於該第一晶片301及第二晶片302所覆蓋範圍以.外之該 基板30 0上設有數個焊墊310供導線3 08打線。因此，該數/ 條導線308連接該第一晶片301之第一焊墊3〇5與該基板3〇〇C: \ Program Files \ patent \ PK6669. Pad 105 wire first wafer 202 one wafer wire 205 adhesive layer first wafer 302 second wafer second glue layer 305 first pad second pad 308 wire 3 Ο 9 overflow glue 31 Ο pad [Example Explanation] Please refer to the third and fourth figures. The preferred embodiment of the present invention mainly includes a substrate 300, a first wafer 301, a second wafer 302, a first adhesive layer 303, and a second adhesive layer 304. The first wafer 301 is adhered and fixed on the substrate 303 by the first adhesive layer 303, and the second wafer 302 is adhered and stacked on the first wafer 301 by the second adhesive layer 304 to form a semiconductor stacked structure. The first wafer 301 and the second wafer 302 are each provided with a plurality of first welding second welding pads 307, which are located on both sides of the second wafer 302 and Each of the first solder pads 305 is provided with a protruding post 306 for conducting the wire 308. Since the height of the protruding post 306 protrudes from the surface of the first wafer 10j, the protruding post 306 It can avoid the pollution caused by the overflow glue 30 9 on the surface of the first crystal; (the material of the protruding post 3 06 is preferably gold. ^ Several second pads 3 07 Located around the second wafer 300 is for conducting wires 308 beats / wires. It is located outside the coverage area of the first wafer 301 and the second wafer 302. On the substrate 300, there are several bonding pads 310 for the wires 3 08 wire. Therefore, the number / wire 308 connects the first pad 305 of the first chip 301 and the substrate 300.
413875 五、發明說明（5) 之焊整310，及第二晶片3〇2之第二焊墊307與該基板30 0之 焊墊310以形成一通路。本發明之晶片堆疊方式可採用美 國專利第5, 721, 452號及第5, 874, 78 1號等方式，該第二晶 片302可旋轉一角度而該第一晶片3〇1之第一焊墊305未被 該第二晶片3 〇 2之側面遮蓋即可。此外，本發明之第二晶 片302堆疊另一晶片而在該第二晶片3〇2之第二焊墊307上 另設有凸柱即可克服溢膠所造成的污染問題《本發明之該 第一晶片301及第二晶片302並非限定黏貼固定於該基板 300上’而該第一晶»301之第一焊墊305設有凸柱3 06之技 術内容可固定連接於承載體上，如一導線架^ 請再參照第一、二及四圖所示，美國專利第5, 721，452 號之膠層106可能產生溢膠而污染未設有凸柱之焊墊1〇4及 美國專利第5, 874, 78 1號之膠層2 05可能產生溢膠而污染未 設有凸柱之焊墊203，因而造成該焊墊1〇4，203無法進行& 打線。反觀’本發明之第一焊墊305設有遍1較高之一凸丨 柱3 06 ’因而一方面可避免用膠量太少所造成在該第二膠 層304内殘留空隙或氣泡的問題，另一方面避免溢膠3〇9污 染該第一焊墊305之凸柱306。此外，該第一焊墊305之凸 柱306不需遠離該第二晶片3〇2側邊之溢膠區。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明’任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。413875 V. The description of the invention (5) of the welding 310, and the second pad 307 of the second wafer 302 and the pad 310 of the substrate 300 to form a path. The wafer stacking method of the present invention can adopt the methods of US Pat. Nos. 5,721, 452 and 5,874, 78 1, etc., the second wafer 302 can be rotated by an angle and the first welding of the first wafer 301 It is sufficient that the pad 305 is not covered by the side surface of the second wafer 300. In addition, the second wafer 302 of the present invention is stacked with another wafer, and another protrusion is provided on the second pad 307 of the second wafer 302 to overcome the pollution problem caused by the overflow of the glue. A wafer 301 and a second wafer 302 are not limited to being adhered and fixed on the substrate 300, and the first pad 305 of the first crystal »301 is provided with protruding posts 3 06. The technical content can be fixedly connected to the carrier, such as a wire. ^ Please refer to the first, second, and fourth figures again. The adhesive layer 106 of US Patent No. 5,721,452 may produce glue overflow and contaminate the solder pads 104 which are not provided with studs, and US Patent No. 5 , 874, 78 The adhesive layer 2 05 of No. 1 may produce glue overflow and contaminate the solder pad 203 without a protruding post, thus making the solder pad 104, 203 unable to be & wired. In contrast, 'the first pad 305 of the present invention is provided with a higher one convex 1 pillar 3 06' so that on the one hand, the problem of remaining voids or air bubbles in the second adhesive layer 304 caused by using too little glue can be avoided. On the other hand, the overflow of the glue 309 to avoid contaminating the protrusion 306 of the first pad 305 is prevented. In addition, the protrusions 306 of the first pad 305 need not be far away from the overflow area on the side of the second wafer 302. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
C:\ProgramFiles\patent\PK6669.ptd 第 8 頁C: \ ProgramFiles \ patent \ PK6669.ptd page 8
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088105992A TW413875B (en) | 1999-04-14 | 1999-04-14 | Pad structure of stacked chips |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088105992A TW413875B (en) | 1999-04-14 | 1999-04-14 | Pad structure of stacked chips |
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| TW413875B true TW413875B (en) | 2000-12-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG97938A1 (en) * | 2000-09-21 | 2003-08-20 | Micron Technology Inc | Method to prevent die attach adhesive contamination in stacked chips |
-
1999
- 1999-04-14 TW TW088105992A patent/TW413875B/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG97938A1 (en) * | 2000-09-21 | 2003-08-20 | Micron Technology Inc | Method to prevent die attach adhesive contamination in stacked chips |
| US7078264B2 (en) | 2000-09-21 | 2006-07-18 | Micron Technology, Inc. | Stacked semiconductor die |
| US7224070B2 (en) | 2000-09-21 | 2007-05-29 | Micron Technology, Inc. | Plurality of semiconductor die in an assembly |
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