TW411511B - Self-aligned silicide technology - Google Patents

Abstract

A self-aligned silicide layer is manufactured on a substrate. A MOS device and a shallow trench isolation are provided on the substrate wherein the MOS device includes a gate, a spacer and a doped region and the shallow trench is filled with silicon oxide as insulator. A silicon layer is deposited on the surface of the gate, the spacer and the doped region by physical vapor deposition such as metal plasma. Such metal plasma of the sputter processes make the silicon or the metal to be ionized. The ionized silicon or metal are anisotropically deposited on the surface of the substrate and the silicon layer on the spacer is removed. A salicide layer is formed from a refractory metal layer on the silicon layer by two-step anneal such as rapid thermal anneal. Since the silicon layer is used as a source of self-aligned silicide layer, the silicide layer can be formed on the top of spacer and the silicon oxide layer above the trench. Photolithography is performed to remove the salicide layer on the trench isolation.

Description

Date of 411511 _ Amendment ---- Case No. 871081 V. Description of the invention (1) 5-1 Field of the invention:-The present invention is related to a sub-quarter-micron large plastic integrated circuit 1 = alignment chip Metallization technology 'especially relates to a self-aligned metallization technique' used to form interconnects of sub-quarter-micron large integrated circuits without narrow line width effects. S-2 Background of the Invention: ^ Self-aligned silicide (sal lcide) technology ’is used for metal contact of components, no additional military is required. A common self-aligned metal silicide technique is described in the following description 'and reference is made to the drawings of the first to third drawings. Please refer to the first figure, which shows a schematic cross-sectional view of a substrate 100. A metal oxide semiconductor field effect transistor (MOSFET) and a shallow trench 110 are fabricated in the substrate 100 and backfilled with silicon oxide material to the trench 110. Among them, it is used for insulation. The metal-oxide-semiconductor half field-effect transistor in the substrate 100 has a gate structure 120, a sidewall 14o of the gate structure 120, and a doped region 13o. Drain region. The substrate 100 is-the material of the side wall of the Shixi substrate is a silicon dioxide material. β As shown in the first figure, the metal layer 150 is uniformly deposited on the metal-oxide-semiconductor field-effect transistor and the substrate. 00 is a physical vapor deposition (PVD) process, such as a sputtering method. The constituent material of the metal layer is refractory metai, which is one of titanium metal, platinum and cobalt metal. 411511 --- ^^ 87108124 V. Description of the invention (2) Year, month, and year_ 一 _ ^ t 忐 Use two-stage rapid heating and annealing treatment to the substrate 1 00 and the process will react the metal layer 15 to The dream metal layer 16 ° metal. 0 /] atoms react to form a silicide metal layer 1 60 »The silicide metal layer is formed on the top surface of the gate structure 120, and the doped region 130 and the substrate 100 ^, Moreover, the metal layer 150 is not made of silicon dioxide material. For example, the sidewall 140 of the gate structure 120 and the trench insulation material can avoid the bridging phenomenon between the gate structure 120 and the doped region 130 (^ 1M) without any etch-back process. After the formation of the petrified metal, the residual metal layer 150 on the side wall 140 and the shallow trench 1 10 is removed by an etching solution, and this etching solution does not have any effect on the silicided metal layer 16 . The self-aligned petrified metal technology is used to make the metal contact in the active area of the component very easy to manufacture. Therefore, when the size of the component is reduced to a size smaller than a quarter micron, the naHow linewidth effect will occur in the self-aligning process of the Shixihua metal process. Refer to the third figure again. In a quarter-micron integrated circuit, the width W2 of the gate structure 120 is approximately 0.25 micrometers, and the width W1 of the gate structure 120 having the side wall 140 is approximately 0.4 micrometers. The width W2 is too small, making it difficult to form the silicided metal layer 160 on the gate structure 12. Based on the above discussion, a new self-aligned metal silicide technology is needed to form a silicon silicide layer on a sub-quarter-micron integrated circuit, on a device with a narrow gate structure. 5-3 Purpose and summary of the invention:

411511 _ Case number 87ί) 8124 V. Description of the invention (3) The present invention discloses a method for making petrified metal on a substrate: a substrate, on which a metal-oxide half-field-effect transistor and a wall-lift half-field-effect transistor have Open pole structure, two hybrids: and =, two gold; on the use of ionic metal electricity. : Above the surface and the substrate. After the silicon layer and the metal layer are formed, the silicon layer accumulated on the silicon layer is removed, so that the gate layer and the gf surface layer are not connected to each other. Then two steps are performed; = = two-stage rapid heating and annealing process to form a petrified metal layer. Processes such as a silicided metal layer are formed on the top surface of the element, and the beauty is that the lithographic metal layer is formed on the top surface of the side wall and the channel material Shi Xisheng is composed of a self-emulsifying lithographic material, because the silicided metal layer Silicon source, so the silicided metal layer can be formed on the silicon dioxide material. 7 chemical metals

fIn addition to the above advantages, the present invention also has several points that are the best quarter-micron integrated circuit. The narrow line width phenomenon is eliminated first; excellent: in the line alignment-metalization process, the shape = two IT = = = Can be used in the second quarter of the "doped polarity of the active area of the circuit. In addition to the other two = two metallized layers, will not reduce the source " and pole 122: minus the source, draw Leakage at the junction of the polar area ... Page 7 411511 _ Case No. 87108124_ Year Month Day __ V. Description of the invention (4) 5-4 Schematic illustration: Many of the objects and advantages of the present invention will be referred to the following The detailed description becomes easier to appreciate and understand, while referring to the following drawings to illustrate, the first diagram is a schematic cross-sectional view of a substrate in the conventional technology, which has a shallow trench isolation and a component; The second figure shows that in the conventional technique, a metal layer is uniformly deposited on a substrate; the third figure shows that in the conventional technique, a self-aligned silicide metal film is formed; the fourth figure shows a cross section of the substrate in the present invention Schematic diagram with a shallow trench isolation and a component; The fifth figure shows that in the present invention, a silicon layer is formed on the top surface of the device and the substrate; the sixth figure shows that the metal layer is formed on the silicon layer in the present invention; the seventh figure shows the invention In the figure, a silicided metal layer is formed on a top surface of a device and a substrate; the eighth figure is to etch the silicided metal layer over a shallow trench in the present invention; and the ninth figure is to show the present invention Among them, in the dielectric layer, a contact hole of a silicided metal layer is formed. Representative symbols of the main part:

^ ^ 87108124 The main month is __Revision V. Description of the invention (5) 100 substrate 110 trench 120 gate structure 130 doped region 140 sidewall 15 0 metal layer 16 0 ^ metallization layer 17 0 silicon layer 18 0 deposition Metal layer 19 0 silicided metal layer 200 intermediate metal dielectric layer 5-5 Detailed description of the invention: In the present invention, 'disclose the self-aligned metallization metal technology of the sub-quarter micron integrated circuit. The primary chemical layer can be formed on the oxidized stone layer and there is no bridging effect between the active areas of the elements, because the silicidated metal layer is formed on the silicon oxide material, so the local interconnects Local interconnection lines can be formed over shallow trench isolation. The element metal contact 'made by the present invention' has a larger area than the metal contact made by the conventional self-aligned metal silicide technology, so that in the present invention, the contact holes in the active area of the element can be easily aligned. . Please refer to the fourth figure, a single crystal silicon substrate having a direction of <100> crystal axis 100

For a preferred embodiment. A component is fabricated on a substrate 100

411511 _Case No. 87108124__Year Month Chromium π: _ V. Description of the Invention C6), this element has a gate structure 1 2 0, a doped region 1 3 0, and a sidewall 140 of the gate structure 1 2 0. # 杂 区130 is the source / dead region of the device, and

A shallow trench isolation (STI) is formed next to the substrate as an insulation between the components. Shallow trench insulation 11 〇 is a shallow trench ’sidewall 1 4 0 filled with oxidized stone material. The composition material is a dream dioxide material. The silicon layer is laminated on the gate structure 12. Please refer to the fifth figure for deposition. _ Above the top surface, above the doped region 130 and above the substrate 100. The silicon layer 17 is deposited using an ion metal plasma sputtering technique, which is a physical vapor deposition process (PVD). The silicon atoms of a target are dissociated into The silicon ions are then accelerated by the bias voltage between the target and the substrate 100, and the silicon ions are deposited anisotropically on the substrate 100. Therefore, the silicon layer 170 is formed only on the surface of the element on the substrate, and on the surface of the substrate 100, the silicon layer 170 is only slightly covered on the surface of the sidewall 14o, and the thickness of the silicon layer 170 is 300 to 300 Between 70 angstroms. After the silicon layer 170 is deposited, an isotropic silicon etching process is used to remove most of the silicon dioxide layer on the surface of the sidewall, or a short-time thermal oxidation process is performed to remove the silicon layer m. ^ / Both are oxidized into silicon dioxide material, so that the silicon layer 1 70 is basically only on the surface of the free-electrode structure 120 and the doped region 13 and is located at the interelectrode junction. The 170 is located on the doped region 130. The Shi Xi layers m work with each other. Then, the surface of the substrate 100 is cleaned to remove the oxidized chemical reaction between the Xi layer 170 and the surface of the substrate. The silicon 411511 _ by Ye Danjin _Case number 87108124__ 年月 日 傣 正 _ V. Description of the invention (7) Please refer to the sixth figure. The deposited metal layer 180 covers the silicon layer 170, which is made by an ion metal plasma process. The metal layer 180 is selected from Titanium, platinum, cobalt, and other materials. In a preferred embodiment, the thickness of the metal layer 10 is between about 200 and 500 angstroms. The metal layer immediately above the deposited silicon layer 170 After 180, a two-stage thermal process is performed on the substrate 100. The metal layer 180 and the silicon layer 170 Instead, a silicided metal layer 190 should be formed. In the first-stage thermal annealing process, the process temperature is maintained between 600 and 70 ° C, and in the second-stage thermal annealing process, the process temperature is maintained between 750 and 850 ° C. Decrease the sheet resistance of the silicided metal layer 190. In addition, for the thermal process method, a two-stage rapid heating annealing process (tw 〇- steprapid the rm a 1 a η nea 1 ing) can be used, and the first stage rapid heating annealing The process is performed between 600 and 800 ° C in Argon gas (choose a specific reaction time according to the reaction temperature) to produce a wonderful metal layer 1 90. After the silicidated metal layer 1 90 is formed, a stable rock is formed. The annealing process of the constituent phases of the metal layer is performed for about 30 seconds between 950 and 500 ° 'reaction in Argon gas to reduce the resistance of the silicided metal layer. Please refer to the seventh figure again' The silicided metal layer 19 is formed on the top surface of the substrate 100 and the components on the substrate 100 because the silicon layer 170 covers the top surface. The broken layer 170 is used as a self-aligned gold silicide. The silicon source of the process, so the top surface of the side wall 1 40 will be covered by the silicide metal layer 丨 〇, because the silicide metal layer 190 can be formed on the top surface of the gate structure 12 〇 and the sidewall 丨 4 〇 The 'top' is wider than the top surface of the gate structure 120, so the narrow line width phenomenon is eliminated. In addition, the silicide metal layer 19 covers the shallow trench isolation.

Page 11 411511 ^ —---- Sez 87] 081¾¼_ year a a__ V. Description of the hairpin ^ ^ a above 'as a local interconnecting line, even if the shallow trench is isolated from the 1 10 by the rule of dioxide Made of silicon material. _ If the element array is defined above the substrate 100, the interconnections of the components on the substrate 100 may be opened, as opposed to the situation shown in the seventh figure. That is, 'the etched metal layer 190 over the shallow trench isolation 110 is etched back' to form a situation as shown in FIG. In the present invention, 'because the wider metal of the metal-oxide half-field effect transistor is formed,' a contact hole that is not too wide can be used for the active region of the metal-oxide half-field transistor. Please refer to the ninth figure, 'showing a contact hole in the intermediate gold dielectric layer 2000, using general chemical vapor deposition' to form the intermediate metal dielectric layer 2000, which is composed of a silicon dioxide material . The middle metal dielectric layer 2000 is engraved on the back surface, and the shape of the middle metal dielectric layer 2000 = the contact hole of the doped region 130 'because of the metal contact of the doped region in the present invention' is also The metal layer 190 is wider than the metal contact formed by the conventional technology. The contact hole can be easily aligned with the doped region 13 without using a wide contact hole. If the contact hole of the component has a smaller diameter, there will be no loss of area in the integrated circuit. According to the above discussion, there are several advantages in the present invention. The first advantage is that the narrow line width phenomenon of the sub-quarter-micron integrated circuit is eliminated. The second advantage is that in the self-aligned metal silicide process, Among them, the formation of local interconnecting lines; the third advantage is that in the next quarter-micron integrated circuit, a narrower contact hole is used; the fourth advantage is that the silicided metal process will not be affected by the integrated circuit Its active region is affected by the doping polarity. In addition, a dream metal layer is formed on the source / drain region to a depth such that the leakage current at the junction between the source / inverted region does not reduce the source / inverted region (junction 1 eakag 411511 _ case number 8Ή08124_ Year month and month revision_ V. The description of the invention (9) is reduced. The present invention has been described above with reference to the preferred embodiment, and those skilled in the art-without departing from the spirit of the present invention, can make a little Change the retouching, the scope of its patent protection depends on the scope of the attached patent application and its equivalent fields.

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Claims (1)

411511-No. 871 read 4__year month g amendment_ 6. Application for Patent Scope 1, a method for manufacturing self-aligned silicided metal layer, at least includes: providing a substrate, at least one element is isolated from a shallow trench and is formed on this substrate The element has a gate structure with side walls on both sides of the gate structure, and the substrate on both sides of the gate structure has a doped region; forming a silicon layer covering the surface of the substrate; Except for most of the silicon layer, the silicon layer on the gate structure and the silicon layer on the doped region are not connected to each other; a metal layer is formed to cover the silicon layer; and A two-stage thermal annealing process is performed to form a silicided metal layer on the surface of the substrate. 2 _ The method described in item 1 of the scope of patent application, wherein the silicon layer is deposited by using ion plasma sputtering technology. 3. The method described in item 1 of the scope of patent application ' The thickness of the silicon layer is about 300 to 700 angstroms. 4. The method described in item 1 of the scope of the patent application, 'After depositing the Shi Xi layer', the surface of the remaining substrate is cleaned to remove the oxide material. 5. The method according to item 1 of the scope of patent application, wherein the metal layer is deposited using an ion metal plasma sputtering technique. 6. The method according to item 1 of the scope of patent application, wherein the metal layer is selected Page 411511 __ 二 索 号 耵 丨 shape? Force f 6. Scope of patent application Since one of the group consisting of Qin metal, Ming metal and platinum-. 7. The degree as described in item i of the patent application range is between about 200 and 500 Angstroms. / ', Μ The thickness of the metal layer is performed in these two stages. 8. The method described in item 1 of the scope of patent application. The thermal annealing process is a two-stage rapid thermal annealing process. 9. A method of manufacturing a self-aligned silicided metal layer on a substrate. The method includes: forming an element on a substrate with a gate structure, having a gate structure on both sides of the intermediate structure, and having a doped region on the base on both sides of the gate structure; Forming a silicon layer on the gate structure, the sidewall and the surface 9 of the doped region; removing the silicon layer on the surface of the sidewall; forming a metal layer covering the silicon layer; and performing two-stage rapid heating The annealing process reacts the silicon layer and the metal layer to form a silicided metal layer. 10. The method according to item 9 of the scope of the patent application, wherein the silicon layer is deposited using an ion metal plasma sputtering technology. 11. The method according to item 9 of the scope of patent application, wherein the thickness of the silicon layer 411511 Cable number 87108124 said Amendment 6. The scope of patent application is between 300 and 700 Angstroms. 1 2. The method according to item 9 of the application, wherein the metal layer is deposited using an ion metal plasma sputtering technique. 1 3. The method according to item 9 of the scope of patent application, wherein the silicon layer on the surface of the sidewall is removed by using a thermal oxidation method to oxidize the silicon layer into a silicon oxide material. 14. The method according to item 9 of the scope of patent application, wherein the step of removing the stone layer on the surface of the side wall uses an isotropic process. 1 5. According to the method of claim 9 in the scope of patent application, after removing the stone layer on the surface of the side wall, the surface of the substrate is cleaned. 16. The method according to item 9 of the scope of patent application, wherein the metal layer is one selected from the group consisting of titanium metal, diamond metal and platinum. 17. The method according to item 9 of the scope of the patent application, wherein the thickness of the metal layer is between about 200 and 500 angstroms. Page 16