TW410453B - Manufacturing process for multilevel plating Cu damascene wires - Google Patents

Abstract

The present invention provides an improved process for Cu damascene wires which employs multilevel plating process to grow the Cu metal layer to improve the flatness and reduce the total growth depth so as to reduce the following planarization polishing time and increase the productivity. First, using normal plating liquid composition to conduct the first stage plating process to grow the first Cu metal layer that the depth is just enough for filling the wire trench; next, conducting the second stage plating process to grow the second Cu metal layer that intentionally increasing the amount of leveler in the plating liquid to reduce the growth rate of the second Cu metal layer at the edges and protrusions of the first Cu metal layer so that it can have smoother surface structure; then, removing the surface portion of the second Cu metal layer and the first Cu metal layer with shorter polishing time to form the required Cu damascene wire structure.

Description

41015 V. Description of the invention (1) '— [Field of invention] The present invention relates to the manufacture of semiconductor integrated circuits, and more particularly to a sound-improving process suitable for steel metal-clad (Cu damascene) wires. The multi-stage electroplating process is used to grow the copper metal layer, which can improve the flatness and shorten the time of subsequent planarization polishing treatment. ", [Learning skills]

The structure of the metal wire is an indispensable part of the semiconductor integrated circuit—some of the electronic components must be electrically connected by appropriate interconnecting wires in order to perform the desired function. Generally speaking, the methods of making metal wires are nothing more than the following two methods: two edges are firstly subjected to a deposition and etching process to form a metal wire pattern ', and then a dielectric layer is provided to provide isolation; the other is to first A groove for forming a metal wire is formed in the dielectric layer, and then a deposition and planarization polishing process is performed to form a metal wire pattern in the groove. Among them, since the latter process is to form a groove first and then make the metal wire in it, just like gem setting on a pedestal, it is also called a "damascene" metal wire process.

Because the skinned wire process has the characteristics of flattening the substrate surface, which is conducive to the implementation of subsequent optical lithography processes, its role has become increasingly important as the integrated circuit process moves towards density and multi-layer development. Firstly, a wire groove and a contact window opening are defined in the dielectric layer, and then a double inlay wire process with a metal wire and a contact plug structure is formed together, and it has a greatly simplified process steps and improved production efficiency. The advantages have also become the eager adopters of the semiconductor manufacturing industry. Therefore, the inlay wire technology has been

Page 4 41 41 V. Description of the invention (2) It has gradually become a semi-conductor. The factory must actively invest. In the past, it has benefited from a relatively fast and finer wire technology. Its advantages have been viewed as increasing the growth of the plating process. The copper metal required to remove the copper metal layer is subject to excessive grinding and the thicker copper metal is conducive to subsequent flattening. In order to penetrate the surface, it is not intended. For details, as circled in Figure 1A, It can be overlaid with a dielectric layer on the top of the diagram to simplify the diagram, or a low dielectric image and an etching process as the metal wire, and the aluminum metal material used in the research and development for the body metal wire has a good effect. Metal is the future semiconductor. At present, the surface layer of the steel-steel metal layer is partially lined. However, the generation of the shallow disk structure layer 'not only enhances the polishing process, but it also provides a detailed description of the problem, and provides a conventional layer for forming any' only-level layer 11 ', such as a dielectric constant, used in the dielectric layer. The mainstream of the above-mentioned tank cleaning process is mainly made by various manufacturers all over the world in order to be more advanced. It is necessary to manufacture the above-mentioned inlay-type interconnected wires, but in order to respond to the faster orientation of semiconductor devices _ Many researchers are still striving to develop better mainstream technologies due to their high conductivity, high ductility and other institutional processes. The damascene conductor process is mainly performed by 'then performing a planarization polishing process' so that the portion remaining in the trench is formed. In order to avoid copper metal layer (dishing) in the wider trench, it is necessary to grow The execution time of the electroplating procedure is not. In the following, the steel wire inlay type wire manufacturing process with reference to Figs. 1A and 1B is shown. First, a semiconductor substrate 10, such as a semiconductor element required for a silicon crystal, is represented here for the entire substrate 10. On the surface of the substrate 10 is a layer of a silica organic polymer material formed by a suitable deposition process. A plurality of trenches i 2 are formed in an appropriate lithographic formation 11 for subsequent fabrication and sequentially on the surface of the dielectric layer 11 to form Θ

Page 5 _410453__ V. Description of the invention (3) A barrier / Cu seed layer 13 and a steel metal layer 14. The barrier layer is made of a material whose polishing rate is lower than that of the copper metal layer 14, such as tantalum (Ta), nitride button (TaN), titanium (τ i), titanium nitride (TiN), silicon oxide, or Materials such as silicon nitride are used as a polishing stop layer in subsequent polishing processes. As for the copper metal layer 14 is grown by the plating process, in addition to filling the above-mentioned trench 12, and extending over the dielectric layer 11. Since the substrate 10 has a raised dielectric layer 11 and a recessed trench pattern 12 ', the surface of the copper metal layer 14 grown by the electric shovel also has a raised structure. Next, as shown in the figure, a chemical mechanical polishing process is performed on the steel metal layer 14 and the barrier / Cu seed layer 13 to remove the two higher than the dielectric layer 丨丨 The part on the upper surface, and the part filled in the trench 12 ′ is made into the desired copper metal inlay wire structure 15. As mentioned before, in order to avoid the copper metal layer 14 in the trench 12 from over-grinding the shallow disk structure, it is common to increase the thickness of the copper metal layer 14; The length of time has also been lengthened; in order to continue the flattening grinding process, Yoshisha is not conducive to improving the production rate. This problem has been improved by half a dozen people. By increasing the leveling agent Uevele in the plating solution, a ^ improved plating process' borrowing the growth of the layer in the corners and protruding parts can reduce the effect of copper metal flatness, so as to enhance the same function of the copper metal layer overall process With the development of 7 thinner steel metal layers and the conventional _ 410453_____ V. Description of the invention (4) The time of frank grinding is shortened accordingly. However, from the results of experiments, I found that if the conventional plating process is completely replaced by the above-mentioned improved plating process, although the flatness of the copper metal layer can be improved, the amount of leveling agent is increased during electroplating; but it also causes impurities in the copper metal layer Increased content changes the conductive properties. Therefore, in order to improve the practicality of the steel-metal inlaid conductive process, it is necessary to continue to improve on this point.

[Summary of the Invention] In view of this, it is an object of the present invention to provide a copper metal

The improved manufacturing process of the inlay wire can improve the flatness of the copper metal layer and reduce the total growth thickness, so as to shorten the time of subsequent planarization and polishing. Another object of the present invention is to provide an improved manufacturing process of copper metal inlaid wires, which can improve the flatness of the copper metal layer to shorten the time of subsequent planarization and polishing processing without changing the conductive properties of the wires. In order to achieve the above and other objectives, the present invention proposes an improved manufacturing process of copper metal inlaid conductors, which uses a multi-stage electroplating process to grow a copper metal layer to improve the flatness of the copper metal layer and reduce the total growth thickness, thereby enabling Shorten the time of subsequent flattening and polishing processes and improve production efficiency. Firstly, the first phase of the plating process is performed with a general plating solution composition to grow the first—

The thickness of the metal layer only needs to be sufficient to fill the f-line grooves. Then, the second stage of the steel plating process is applied to grow the second copper metal layer, which deliberately adds the leveler amount in the electric fluid. 'In order to reduce the potential of the second copper metal ^-the formation rate of the edges and protrusions of the copper metal layer, so as to obtain a relatively flat surface structure;

Page 7 1 410453 V. Description of the invention (5) The short grinding treatment time removes the surface layer part of the second copper metal layer and the first copper metal layer to form the required steel metal inlay wire structure.

In detail, the present invention proposes a multi-stage electroplated copper metal inlay type · conductor process, which is used to improve the flatness of the copper metal layer and reduce the time of subsequent planarization and polishing processes, including the following steps: forming a dielectric layer Overlying a semiconductor substrate and forming a plurality of trenches in the dielectric layer to expose a part of the surface of the semiconductor substrate for use in making metal wires; forming a barrier / copper seed coating to cover the trenches and the dielectric On the surface of the electrical layer; the first-stage plating process is performed to form a first steel metal layer along the undulating surface of the barrier / copper seed layer, the thickness of which is approximately equal to the depth of the above-mentioned trench, thereby filling the trench Implement a second-stage electroplating procedure to grow a second steel metal layer on the first steel metal layer, where the amount of leveler in the plating solution is deliberately increased to reduce the The growth rate of the corners and protruding parts of the first copper metal layer is obtained—a relatively flat surface structure; and a chemical mechanical polishing sequence is performed to completely remove the second copper metal layer 'and remove the barrier / The copper seed layer and the first copper metal layer are higher than the upper surface of the dielectric layer ’, leaving a portion filled in the trench by the copper seed layer and the copper metal inlay-type conductor structure.

According to a preferred embodiment of the present invention, the above-mentioned dielectric layer may be a silicon oxide layer formed by an appropriate deposition process, or a low-dielectric constant organic polymer material layer, and the above-mentioned barrier layer is selected with a polishing rate lower than that of copper. The material of the metal layer includes materials such as group (Ta), tantalum nitride (TaN), hafnium (Ti), titanium nitride (TiN), oxide, or nitride.

Page 8 ------- A10453 V. Description of the invention ------------ $ Schematic description of the diagram] In order to make the present invention clearly understandable, the following series I escape and other purposes and features And the advantages can be more detailed. The detailed description is as follows: 1. Give a preferred embodiment and cooperate with the accompanying drawings to show the conventional production of copper metal to show the improved 1A and 1B diagrams according to the present invention are both 丨& m flow of inlay wire ^ and Figures 2A and 2B are cross-sectional views, the manufacturing flow of a preferred embodiment [Example] =, as shown in Figure 2A, provided-semiconductor substrate 2 〇, such as # 曰 曰 circle, any desired semiconductor element can be formed on it, so == in order to! The pattern is represented by a flat substrate 20 only. In: = Covers a dielectric layer 21, such as a silicon layer with an appropriate deposition procedure, or an organic polymer material layer with a low dielectric constant (10w_k). A plurality of trenches 22 are then formed in the dielectric layer 2 丨 with appropriate lithographic imaging and etching procedures to expose a portion of the surface of the semiconductor substrate 20 for subsequent use as a metal wire. Then "cover the above exposed surfaces of the trench 22 and the dielectric layer 21-barrier / copper seed layer 23, wherein the barrier layer is made of a material whose polishing rate is lower than that of steel metal", for example, group (Ta) , Nitride button (TaN), titanium (Ti), titanium nitride (TiN), silicon oxide, or silicon nitride and other materials, in order to facilitate the subsequent polishing process as a polishing stop layer. Next, a multi-stage plating process according to the present invention is performed. First, use the conventional plating solution

No. 9 X 410453 V. Description of the invention (7) Stage electric clock program 'is used to grow the first copper metal layer 24a along the undulated surface of the above barrier / copper seed layer 23, and its thickness only needs to be sufficient to fill the above groove 22, as shown in Figure 2A. Then, a second-stage electroplating process is performed to grow a second copper metal layer 24b on the first copper metal 24a, wherein the amount of leveler in the plating solution is deliberately increased, for example, 1%, etc. , The growth rate of the corners and protrusions of the second first copper metal layer can be reduced, and a second copper metal layer 24b with a flat surface can be formed. So, although lacking

The total thickness of the mth copper metal layer 24a and the second steel metal layer 24b and the thickness 1 of the copper metal layer 14 in the H figure, but the thickness of the copper metal layer filled with 2 in FIG. 2A can maintain the same thickness as in FIG. 1A. The copper metal layer filled above the trench 12 is equivalent, or even slightly thicker. Next, as shown in FIG. 2B, 煸 t—a copper metal layer 24a and barrier / copper seed layer 23—b, and the first part is removed, leaving the two filled in the trench m] 21 The surface is made of inlay-type wire structure 25. Compared with the conventional technology, the steel and gold required for the blade attack are improved in the present invention and the first-stage electroplating process only grows thick enough to fill the layer 24a. Therefore, the time required for electroplating growth is- The second phase of the electric power mining process can be performed at the same time. In addition, the leveling agent is used to grow the first steel metal layer 24a on the first steel metal layer 24a. In other words, the second copper metal layer T is on the first The thickness of the copper metal layer 24a growing at the depression is greater than that at the protrusion, so there is no need to prolong the time of electro-forging growth as in the conventional process.

Page 10 ^ 10453 V. Description of the invention (8) It is known above the groove 22 that a sufficient thickness of steel metal layer is provided for grinding and buffering. In this way, not only the total thickness of the first copper metal layer 24a and the second copper metal layer 24b can be reduced, but also the undulations of the surface structure of the substrate can be smoothed. At the same time, the time required for the subsequent planarization polishing process can be shortened. Helps improve production efficiency. Although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

6. Scope of patent application: 丄. A multi-stage electroplated copper metal inlaid (Cll damascene) wire process' to improve the flatness of the copper metal layer and reduce the time of subsequent planarization grinding processing, including the following steps:, forming A dielectric layer covers a semiconductor substrate, and a plurality of trenches are formed in the dielectric layer to expose a part of the surface of the semiconductor substrate for use in making gold wires; forming a barrier / copper seed layer ( barrier / Cu seed layer), covering the trenches and the surface of the dielectric layer; performing a first-stage plating process to form a first copper metal layer along the undulating surface of the barrier / copper seed layer , Whose thickness is approximately equal to the depth of the trenches, thereby filling the trenches; performing a second-stage electroplating procedure to grow a second copper metal layer on the first steel metal layer, where 'by deliberately increasing The amount of leveler in the plating solution is used to reduce the growth rate of the second copper metal layer at the edges and protrusions of the first copper metal layer, so as to obtain a relatively flat surface structure; A chemical mechanical polishing (CMP) process is performed to completely remove the second copper metal layer, and remove the barrier / copper seed layer and the first copper metal layer above the upper surface of the dielectric layer while leaving The next two are filled in the grooves to form a copper metal inlaid conductor structure. 2. A multi-stage electroplated steel metal inlay wire process as described in item 1 of the scope of the patent application, wherein the dielectric layer is a silicon oxide layer reported by an appropriate deposition process. 7 3. A multi-stage electroplated steel as described in item 1 of the scope of patent application Page 12 410453 VI. Scope of patent application It belongs to the inlay wire process, in which the dielectric layer is an organic polymer material layer with a low dielectric constant. 4. A multi-stage electroplated copper-metal inlaid wire process as described in item 1 of the scope of the patent application, wherein the barrier layer is made of a material whose polishing rate is lower than that of the copper metal layer. 5. A multi-stage electroplated copper metal inlaid conductor process as described in item 4 of the scope of the patent application, wherein the material of the barrier layer is one selected from the group consisting of tantalum (Ta), nitride button (TaN), and titanium (Ti), titanium nitride (TiN), silicon oxide, and silicon nitride.