TWI238461B - Preparation method of planar electroplated metal layer and electroplating solution therefore - Google Patents

Abstract

A preparation method of a planar electroplated metal layer and the electroplating solution applicable therefore. The preparation method includes providing a semiconductor substrate having a trench, bathing the substrate in a first electroplating solution and depositing a first electroplated metal layer on the trench, and bathing the substrate in a second electroplating solution and depositing a planarizing second electroplated metal layer on the trench such that the second electroplated metal layer forms a planar electroplated metal layer together with the first electroplated metal layer.

Description

1238461_____ V. Description of the invention (ll " " " 'S' --- the technical field to which the invention belongs ^ The present invention relates to a method for preparing a flat electroplated metal layer and a damascene structure and a metal suitable for these methods The electroplating composition, in particular, relates to a preparation method for avoiding the formation of uneven electroplated copper surface after electrochemical electroplating and a metal electroplating composition suitable for the method. Two # The prior art metal wire structure is used in semiconductor integrated circuits. An indispensable part, each electronic component must be electrically connected through appropriate internal connecting wires to perform the desired function. In general, the methods of making metal wires are nothing more than the following two : One is to perform a deposition and engraving process to form a metal wire pattern, and then to form a dielectric layer to provide isolation; the other is to first form a groove in the dielectric layer for making metal wires, and then Those who apply a deposition and planarization polishing process to form a metal wire pattern in the groove. Among them, since the latter process is to form the groove before The metal wire is made in it and is called "damascene" metal wire process. Because the wire process has the property of flattening the substrate surface, it is beneficial to the subsequent optical lithography process. The circuit process is becoming denser and multi-layered, and its role has become increasingly important. The wire grooves and contact window openings are first defined in the dielectric layer, and then they are opened into a double structure of metal wires and contact plugs. The carbon-inlaid wire process has the advantages of greatly simplifying the process steps and improving the production efficiency. It has also become an eager adopter in the semiconductor manufacturing industry. Therefore, the inlay wire technology has been

0503-8173twf (nl); TSMC2001-1503; Renee.ptd Page 5 1238461 V. Description of the invention (2) ~ -----------! Will gradually become a semiconductor metal wire manufacturing plant, actively invest in related research In the mainstream of the world, major manufacturers all over the world made the past, using Shao metal; more sophisticated. It is possible to obtain a fairly good effect to produce the above-mentioned inlay-type interconnecting wires, and the development trend has been faster and finer, in response to the trend of semiconductor devices toward faster wire technology. Among them, copper metal researchers are still striving to develop better advantages, and it has been considered that future semiconductivity = high conductivity, high ductility, etc. are increasing. At present, the mainstream technology of steel, the scope of application of plating process growth-copper metal ^ ^ & wire process is mainly to remove the surface part of the copper metal layer, = ^ target line a flattening and polishing copper metal wire required . The portions where the transfer remains in the trench are formed. Figures 1a to 1c show cross-sectional views of the process using transfer. Please refer to Section 1H, 5! The plating solution is used to plate a copper substrate in the trench, such as a silicon wafer, on which a nubuck substrate (not shown) can be mounted. … Bulk substrate 10: 2; any semiconductor elements required for oxidation formed by vapor deposition (CVD); 1 electrical layer 12, such as a layer of chemical organic polymer material. Formed with lithography and ', or low dielectric constant-trench 14' for subsequent fabrication of copper conductor II. Insert copper connector II in dielectric layer 12 = ore 2 for steel electricity. The square side wall has a large mass transfer space, so, ☆ trench wall; the deposition rate of copper on the faster, slower at the bottom of the trench 14, because: resulting in the pattern of the copper layer 16 in Figure lb. With the electric clock ;, Before the copper has completely filled the trench 14, 'copper will seal the top of the trench

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1 m ^ copper can no longer be plated into the trench 14. In this way, a copper layer pattern 18 such as No. 2 and No. 2 is formed, such as a dog bone-b, and a void 19 is generated in the medium. For trenches with a high depth-to-width ratio (asPeci ratio), the trench filling capability will be worse. Focusing on the conductor structure entering the sub-micron era, the challenges for copper electroplating technology are also increasing day by day; for example, in order to avoid voids in the deposition process of lines (Hnes) or conductors (γ as), these trenches are filled. The grooves must be processed from bottom to top; and the thin film 'deposited on the wafer surface' must also be very uniform, and the thickness difference must be controlled within a percentage point (a sigma) or less; on the other hand, For electrochemical dry plating4, the deposition rate of copper must be precisely controlled to meet the economic benefits of mass production by wafer manufacturers. Electrochemical Piping (ECP) is a process that transfers copper in a chemical solution electrolyte to the surface of the wafer (cathode), making a thin film that is repetitive, void-free, and can be immediately chemically and mechanically polished to provide maximum manufacturing quality. Rate and productivity. Figures 2a to 2d show cross-sectional views of the process of electroplating copper from bottom to top in a trench using electrochemical plating. Referring to FIG. 23, reference numeral 20 represents a semiconductor substrate, such as a silicon wafer. A dielectric layer M, such as a stone oxide layer, is formed on the semiconductor substrate 20. Next, using a lithography and etching process, a first trench 24 and a second trench 25 are formed in the dielectric acoustic 2 2. The first trench & line width is larger than the second trench 25. small. Then copper plating is performed, and the beans are deposited as shown in Figs. 2b and 2c. The copper layer 26 is filled from the bottom of the trench ^^ First, a copper layer 26 is formed as shown in Fig. 2b, and then the via window 24 is filled to form a first layer.

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In the copper recording solution, when there is no void, the line is flattened due to the small first line width of the copper. The ical polishing is shown in the figure. In the first case, the ion is emitted in the groove 24 and the second line is flat. An obvious treatment is in the trench copper layer 28. First of all, the grooves 2 and 5 need to be polished in this step. 5. The invention is explained in (4) 2c copper layer 28. As above, the trench is sealed and recorded in the same way, so that the line width is 80, and the copper layer after electroplating on the surface of the original trench is applied. 2d is filled with copper. Due to the above-mentioned copper dissociation, the image obtained after electroplating has the following disadvantages: a plating layer on the surface of the dielectric layer 22 is used to determine the excess copper in the second trench plating, and the waste of the process. Added post-processing, such as the traditional mechanical and electrical research contents. The groove above the groove is passed through the recessed portion 8 1 of the groove 2 5. For example, CMP) 〇 The surface type of the groove 2 4 and the deposition rate above the groove is not high. The state generation recess is because the second trench is larger than the second trench 25 and is filled with copper. However, in the next step, the formed dielectric layer 22 is removed from the burden of surface treatment, and the throughput is 〇 The deposition rate is poor for electroplating and convex electroplated surfaces are smoother. Therefore, it is necessary to mechanically grind a second groove 25, which is the same as that of the electroplating machine 25, which is the same as the electroplating machine. The surface of the copper dielectric layer 22 of the key bond is also required, so the surface electric chain is redundant. Reduction of planarization: In order to solve the above problem, the main purpose of the present invention is to provide a method for preparing a planarized metal layer. The metal plating composition can be formed after the plating process is completed.

0503-8173twf (nl); TSMC200M503; Renee.ptd Page 8 1238461 V. Description of the invention (5) '' 'm electroplated metal layer' can simplify the subsequent removal of metal clothing on the surface of the dielectric layer (such as chemical mechanical polishing) And effectively increase the yield of the process. ^ According to the above-mentioned object, the present invention proposes a method for flattening electroplated gold. The method includes the following steps: forming a dielectric layer at-semiconducting transition, forming a first trench and a second trench. Within the dielectric layer, the width of a 2 trench is smaller than that of the second trench; the semiconductor substrate is placed in a first metal bond solution, and a voltage is applied to deposit a first electrical metal layer in the above dielectric. The electrical layer, the first trench, and the surface of the second trench, wherein the second metal plating solution includes a first inhibitor and a first accelerator; and the semiconductor substrate is placed in a second metal plating solution and applied The voltage = sink = the second electroplated metal layer is on the surface of the first electroplated metal layer. The second electroplating solution includes a second inhibitor and a second accelerator. The polymer bond as the first inhibitor is relatively Short, molecular weight is relatively ^ the overall effect of the electric bond 卩 the effect of the first accelerator is the main body, so that the metal as the bottom of the A deposition from bottom to top 'suitable to fill the first trench', is the polymer bond of the second inhibitor Relatively long and relatively molecular weight The concentration is relatively high, so the overall effect of the plating is the second inhibitor effect = the main body, which is conducive to the filling and flattening of the metal ions in the second trench =, and together with the above-mentioned first plating metal layer, a planarized plating metal layer is formed. . The present invention also proposes a method for preparing a planarized electroplated metal layer & including the following steps: forming a dielectric layer on a semiconductor substrate; forming a first trench: and a second trench in the dielectric layer, The line width of the first trench is smaller than that of the second trench; a barrier layer is formed on the dielectric layer;

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Description of the invention (6): a metal seed layer is on the barrier layer; the semiconductor substrate is placed in a first metal plating solution, and a voltage is applied to deposit a first electroplated metal layer on the "electrical layer and the first trench" And a second trench surface, wherein the first gold plating solution includes at least a first electrolyte containing the metal, a first accelerator 'and a first ~ inhibitor, mainly to accelerate the first electroplated metal layer on the first Deposition over a trench, so that a first electroplated copper layer is deposited in a bottom-up manner to fill the first trench; and the semiconductor substrate is placed in a second gold f-electric ore solution, and a voltage is applied to deposit A second electroplated metal layer is on the surface of the first key metal layer. The second metal electroplating solution includes at least: a second electrolyte containing the metal, a second accelerator, and a second inhibitor. The deposition of two electroplated metal layers over the second trench, so that the second electric ship steel layer is deposited from bottom to top, fills the second trench, and forms a planarization with the first electroplated metal layer. Electroplated metal layer. A method for preparing a planarized electric ore metal layer is provided. The method includes the following steps: providing a semiconductor substrate having a trench; placing the substrate into a first metal plating solution, and applying a voltage to deposit a first electro-metallic layer on the trench; In the trench, the first electroplated metal layer is filled into the trench in a bottom-to-top manner; and the substrate is placed in a second metal electroplating solution, and a voltage is applied to perform planarization to deposit the second electroplated metal layer. In the trench, the second electroplated metal layer and the first electroplated metal layer together constitute two planarized electroplated metal layers. The present invention also provides a metal electric money composition including: a metal t plating solution having the metal Ion; an inhibitor, which is polyalkylene glycols, polyoxyalkylene glycols

0503-8173twf (nl); TSMC2001-1503 · Renee.ptd Page 10 1238461 V. Description of the invention (7) Copolymers of polyoxyalkyene glycols or polyoxyalkyenes, the content of the inhibitor is 20 0 -1 OOOppm; and an accelerator, the accelerator is sul f opropy 1 disul f ide, sulfonated acetylthiourea, 3-thiol l-propionite Salt (3-mercapto-l-propanesulfonate), dibenzyl-dithio-carbamate, 2-mercapto-ethanesulfonate or η, η -Dimethyl dithiouric acid- (3-sulfopropyl) ester (n, n-dimethyl-dithiocabamic acid- (3-sulfopropyl) ester), the content of which is 5-50 ppm. The method and metal ore composition of the present invention are particularly suitable when the line width of the first trench is less than 1 micron and the line width of the second trench is greater than 2 micron. The invention also provides a method for preparing a silver embedded structure, which includes the following steps: providing a substrate having a plurality of grooves formed on an upper surface thereof, the grooves having at least two different line widths, and the grooves respectively having A conductive surface; a first electrolytic solution and a second electrolytic solution are provided, wherein the composition of the first electrolytic solution is an optimized composition for filling trenches with a line width less than ϋ 2 micrometers, and the The composition of the second electrolyte is an optimized composition for filling trenches with a line width greater than 1 micron; the first electrolyte is used to plate a layer of a metal of an appropriate thickness on the substrate to fill all of the substrate. Trenches with a line width of less than 0.2 micrometers, while filling the bottom of the trenches with a line width of more than 1 micron on the substrate; and using the second electrolyte to plate another layer of a metal with a proper abundance on the substrate to fill it All lines on this substrate see grooves greater than 1 micron

0503-8173twf (nl); TSMC2001-1503; Renee.ptd Page 11 1238461 V. Description of the invention (8) Slot. According to the method for manufacturing a mosaic structure, the first electrolyte preferably further includes a short-chain polymer having a relatively low molecular weight; and the = electrolyte preferably further includes a long-chain south having a relatively high molecular weight. molecule. Detailed Description of the Invention In the conventional metal ore solution, additives such as accelerators, inhibitors, leveling agents and the like are generally added. Accelerators are generally small organic molecular compounds containing s, 0 polar functional groups, which are usually added to the recording solution with low-concentration yields to accelerate the rate of X-ion deposition during electroplating and promote nucleation reactions to become poorer. , The slippery grain structure; the inhibitor is generally larger: grows flatter = alcohol ·, whose f is formed on the surface of the power ore; the molecular weight of the resistance is generally at a higher concentration (200-2000ppn. The deposition rate of the substrate, and in the present invention, the two Γ sections are used in the electric ore solution. The metal layer is deposited. A The two-stage electroplating used = Hiragaki's difference is that the-metal electric ore solution = = = [The most important difference is the short molecular bond, molecular weight,], so it is added; the effect of the Titanium 2 inhibitor is mainly to help the copper ion implantation should be accelerated, which is suitable for filling smaller line widths. In the bottom-up cleaning additive of the groove / slot ^ portion, it is used as an inhibitor to reduce the length of the ten-bond and high molecular weight contained in the metal plating solution.

im 0503-8173twf (nl); TSMC2001-1503; Renee.ptd 1238461 V. Description of the invention (9) Adding a high concentration of 5 will help to reduce the deposition of the first metal by using an accelerator, because of the presence of voids The degree of plating is conformed to the original groove shape. In order to make the following special mention: 'Therefore, the overall effect of the additive metal ions filled in the larger line described the choice of the first metal plating solution preparation, and the electric ore in its electric ore solution can avoid the use of traditional metal electricity At the same time, it is possible to avoid the generation of online protrusions and the surface shape of the line width to form a preferred embodiment of the above-mentioned purpose and features of the invention, and cooperate with the effect of the inhibitor to fill and flat the main wide trench. The concentration of the second metal plating solution is controlled so that the bottom of the trench can be successively moved to the top of the trench. When the plating solution is over, the smaller width of the trench is sealed above the trench. The advantages and advantages can be more clearly understood. The drawings are described in detail. For example, Figures 3a to 3c of the embodiment show the preparation method according to the present invention. In the trench, please refer to the section "Danning electroplated metal layer". Figure 3a is a sectional view of the manufacturing process of the rod ^ 2 () 0 ^ steel. A wafer can be formed thereon; = a bulk substrate, for example, 1 a semiconductor substrate 20 has a dielectric layer 22 on it, and a substrate (not shown). The silicon oxide layer formed by (CVD) is made of a chemically-deposited chemical vapor deposition method: silicon, nitrogen cutting, glass, and a glass structure composed of two layers of glass early layers. Next, with lithography and low 503-8173twf (nl); TSMC2001-1503; Renee. Ptd page 131233841 V. Description of the invention (10) '---- 2 layers 42] ^ H-second trench " And a second groove 25, in which the first groove is and the right ^ / second e 1 car parent second groove 25 is small. The above grooves can also be used; For the purpose of making copper wires, a single damascene trench is used as an example. Next, as shown in Figure 3b, the dielectric layer 22 and the first trench 24 and the second trench 25 can be formed on the surface— The barrier layer 52 and the -Cu seed layer 54. The barrier layer 52 may be made of a material whose polishing rate is lower than that of a copper metal, such as titanium hafnium, tantalum (Ta), or tantalum nitride (TaN), to facilitate subsequent grinding. Where = At first, it is used for polishing the stop layer. The deposition method can use chemical vapor deposition (CVD) or sputtering. The thickness of the barrier layer can be between 50 and 500a. Copper seed layer 54 It can be deposited by immersion plating or ionized metal electroplating (IMp; ionized metal Plasma), and the thickness can be from 50 (500) to 50000. First, then, two-stage copper plating is performed. To first The trench and a first trench 25 are filled with copper. For the convenience of description below, the barrier layer 5 2 and the copper seed layer 54 are not shown again. Please refer to FIG. 3c, first, the semiconductor substrate 2 〇 Place in a first copper plating solution (not shown) and apply a voltage to deposit a first copper plating layer 29 on the surface of the dielectric layer 22 and the first trench 24 and the second trench 25. This first copper plating solution is at least It includes a copper-containing first electrolyte, a first accelerator, and a first inhibitor 'mainly to accelerate the deposition of the first copper plating layer 29 over the first trench 24, so that the first copper plating layer 29 is formed from below. It is deposited in an upward manner to fill the first trench 24. The above-mentioned first copper plating solution is preferably between 0.5 and 1. The first electrolyte containing copper may be a copper sulfate (CuS04) solution; The first accelerator may be

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Organic sulfur compounds, such as 3-sulfopropyl disulfide, 3-mercapto-1-propanesulfonate, etc .; the first inhibitor It may be a copolymer of polyalkylene giycolls, polyoxyalkyene glycols, or polyoxyalkyenes. The amount of accelerator can be 10-100 ppm, preferably 10-30 ppm, and the amount of inhibitor can be 50-200 ppm. ○ Please refer to Figure 3d. Secondly, the first copper electroplating is formed as described above. The semiconductor substrate 20 of layer 29 is placed in a second copper electroplating solution (not shown), and a voltage is applied to deposit a second electrical copper layer 30 on the surface of the first electrical copper layer 29, wherein the second copper electrical bond solution includes at least copper The second electrolyte, the second accelerator, and the second inhibitor are mainly used to accelerate the deposition of the second electroplated copper layer 30 above the second trench 25, so that the second electroplated copper layer 30 moves from bottom to top. Deposition 'fills the second trench 25 and forms a planarized electroplated copper layer with the first copper bell layer 29 described above. The pH of the second copper plating solution is preferably between 0.5 and 2. The second electrolyte containing copper may be a copper sulfate (CuS04) solution; the first accelerator may be sulfopropyl disu 1 fide, but other accelerators, such as ethyl sulfide, may also be used. Sulfonated acetyl thiourea, 3-mercapto-l-propanesulfonate, dibenzyl-dithio-carbamate, 2-sulfur 2-mercapto-ethanesulfonate or n, n-dimethyldithiouric acid- (3-Luteolinate propyl) acetate (n, n-dimethyl-dithiocabamic

0503-8173twf (nl); TSMC200M503; Renee.ptd page 15 1238461 V. Description of the invention (12) acid- (3-sulfopropyl) ester) etc .; the second inhibitor may be polyalkylene glycols ), Polyoxyalkyene glycols (polyoxyalkyene glycols) or polyoxyalkyenes (polyoxyalkyenes) copolymers, and the like. In addition to accelerators and inhibitors, a flattening agent can be added to promote the flatness of the electroplated surface β. The leveling agent is, for example, alkylated polyimide (alkylated ^ po1ya 1 ky1ene imi ne), 2-thiol sulrin (2-11 ^ 1 ^ &01; 〇1 ± 1 & 2〇111 ^), etc. . The amount of the accelerator can be 5-50 ppm, preferably 5-1 Oppm, the amount of the inhibitor can be 2000-1OO (^ 0111, the amount of the flattening agent can be 1-20) 1) 111. Figure 4 shows the ratio of the first copper plating solution and the second copper plating solution used to form the copper layer from bottom to top in the copper plating steps of the above two stages. The inspection coordinate represents time. The vertical coordinate represents over-potential, [over-potential], and the larger ΔΕ indicates the plating rate. It shows that a copper layer is formed from bottom to top of the selected second copper plating solution. The rate is faster than that of the copper electro-hydraulic liquid. "The first and last of the invention are also referred to in Fig. 3e, which can be re-done + + 4 丁 ^ H. Dan on the flattened electroplated copper layer. A further planarization process is performed, for example, the method such as 'chemical mechanical polishing or electropolishing' is used to remove the dirty layer. g 'Xunwan style' integrates the copper above the dielectric layer 20 '. The planarization plating method provided by the present invention can be formed after the plating process is completed-a surface-type layer to simplify / eliminate subsequent finer planarization processes. And—effectively improve

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1238461_ Brief Description of Drawings Figures la to lc show cross-sectional views of a process for electroplating copper in a trench using a conventional copper plating solution. Figures 2a to 2d show cross-sections of a copper plating process from bottom to top in a trench using electrochemical plating. Figures 3a to 3e are cross-sectional views showing a process of plating copper from bottom to top in a trench according to the method for preparing a planarized copper layer according to an embodiment of the present invention. FIG. 4 shows the rate ratio of the first copper plating solution and the second copper plating solution used to form the copper layer from the bottom to the top in the method for preparing the planarized copper plating layer according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 10 to semiconductor substrate; 12 to dielectric layer; 14 to trench; 16 to copper layer; 18 to copper layer; 19 to void; 20 to semiconductor substrate; 22 to dielectric layer; 24 to first trench; 25 to second trench; 26 to copper layer; 28 to copper layer; 29 to first electroplated copper layer; 30 to second electroplated copper layer 52 to barrier layer; 54 to copper seed layer; 80 to convex 8 0; 81 to recess.

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Claims (1)

1238461 l A method for preparing a planarized electroplated metal layer, comprising: forming a dielectric layer on a semiconductor substrate; a first trench and a second trench in the dielectric layer, wherein the first trench is a trench The line width is smaller than that of the second trench; the reed is placed in a first metal plating solution with a half-V body substrate, and the applied electric power is accumulated on the above dielectric layer and the first trench and a ^ The surface of the trench, wherein the first metal ore solution includes a first inhibitor 4 /, a first accelerator; and placing the semiconductor substrate in a second metal plating solution, and applying electrodeposition to a second plating metal The layer is on the surface of the first electroplated metal layer, and the k-metal plating solution contains a second inhibitor and a second accelerator. Among them, the polymer bond as the first inhibitor is relatively short and the molecular weight is relatively small. The overall effect of electroplating is mainly based on the effect of the first accelerator, so that metal ions are deposited from the bottom to the bottom of the trench, which is suitable for filling the first trench. As a second inhibitor, the polymer bond is relatively long and the molecular weight is relatively long. Relatively large and add The degree is relatively high, so the overall effect of electroplating is mainly based on the effect of the second inhibitor, which is beneficial to the filling and planarization of metal ions in the second trench, and forms a planarized electroplated metal layer together with the first electroplated metal layer. . 2. The method for preparing a planarized electroplated metal layer according to item 1 of the scope of patent application, wherein the metal is copper. 3. The method for preparing a planarized electroplated metal layer according to item 1 of the scope of patent application, wherein the line width of the first trench is less than 1 micrometer, and the line width of the second trench is greater than 2 micrometers. 0503-8173twf (nl); TSMC2001-1503; Renee.ptd page 19 1238461 4. The method for preparing a planarized electroplated metal layer according to item 2 of the scope of the patent application, wherein the first and second metal electroplating solutions include a copper sulfate solution. 5. The method for preparing a planarized electroplated metal layer as described in item 1 of the scope of patent application, wherein 3-sulfopropyl disulfide or 3-sulfopropyl disulfide or 3-sulfur is added to the first metal plating solution. 3-mercapto-1-propanesulfonate as the first accelerator. 6. The method for preparing a planarized electroplated metal layer according to item 5 of the scope of the patent application, wherein the content of the first accelerator contained in the first metal electroplating solution is 1 to 100 ppm. 7. The method for preparing a planarized electroplated metal layer according to item 1 of the scope of patent application, wherein polyalkylene glycols and polyoxyalkylene glycols are added to the first metal plating solution. (polyoxyalkyene glycols) or copolymers of po 1 yoxya 1 kyenes as the first inhibitor. 8. The method for preparing a planarized electroplated metal layer as described in item 7 of the scope of the patent application, wherein the content of the first inhibitor contained in the first metal plating solution is 50 to 200 p p m. 9. The method for preparing a planarized electroplated metal layer as described in item 1 of the scope of patent application, wherein the second metal electroplating solution contains sulfopropyl disulfide and sulfonated acetylthiourea ), 3-mercapto-l-propanesulfonate, benzhydryl-diphenylalcohol ammonia 0503-8173twf (nl); TSMC2001-1503; Renee.ptd page 20 1238461 Sixth, the scope of application for patents: dibenzyl-dithio-carbamate, 2 · merapto-ethanesulfonate or n, n-difluorenyl two furnace f undersalt '~ ;, L-( 3-Acid propyl) § (11,11- (11111611171-(^ 1: 111〇〇 & 6 & 11 ^ acid- (3-sulfopropyl) ester) as the second accelerator. 1 0 · The flattened electric clock metal exhibition and preparation method as described in item 9 of the scope of patent application, wherein the second metal plating solution contains a content of second addition & 5-50 ppm. 1 1 · As patent application The method for preparing and flattening electroplated metal described in the first item of the scope, wherein the second metal electroplating solution contains polyalkylene glycols, polyalkylene glycols, and polyoxyalkylene glycols. Polyoxyalkyene glycols or polyoxyalkyenes copolymers are used as the second inhibitor. 1 2 · The method for preparing a flattened electromechanical metal exhibition as described in item 11 of the patent application scope, wherein The content of the second suppression in the second metal plating solution is 200-1000 ppm. 1 3 · If the patent application The method for preparing a planarized electroplated metal layer as described in item 1 ', wherein the second metal plating solution further includes a planarizing agent to promote the leveling of the electroplated surface. 1 4 · As described in item 13 of the scope of patent application A method for preparing a planarized electroplated metal layer, wherein the planarizer is an alkylated polyeneimine (alky la ted ρ ο 1 ya 1 ky 1 eneimine) or 2-mercaptothiazoline. 1 5. The method for preparing a planarized electroplated metal layer according to item 13 of the scope of the patent application, wherein the content of the flattening agent is 1-20 ppm. 0503-8173twf (nl). TSMC2001-1503 »Renee.ptd Page 21 1238461 6. Application for Patent Scope 1 6. The method for preparing a flat plated metal layer as described in Item 1 of the scope of application for patents, including the deposition of metal After the layer, the metal layer is planarized. 17. A method for preparing a planarized electroplated metal layer, comprising: forming a dielectric layer on a semiconductor substrate; forming a first trench and a second trench in the dielectric layer, wherein the first trench The line width of the trench is smaller than that of the second trench; a barrier layer is formed on the dielectric layer; a metal seed layer is formed on the barrier layer; the semiconductor substrate is placed in a first metal plating solution Applying a voltage to deposit a first electro-mineral metal layer on the surface of the dielectric layer, the first trench, and a second trench, wherein the first metal plating solution includes at least a first electrolyte containing the metal, a first An accelerator and a first inhibitor mainly accelerate the deposition of the first electroplated metal layer above the first trench, so that the first electroplated copper layer is deposited from the bottom to the top, and fills the first trench. And placing the semiconductor substrate in a second metal plating solution and applying a voltage to deposit a second plating metal layer on the surface of the first clock metal layer, wherein the second metal plating solution includes at least one metal containing the metal Second electrolyte, one A second accelerator and a second inhibitor are mainly used to accelerate the deposition of the second electroplated metal layer above the second trench, so that the second electroplated copper layer is deposited from bottom to top to fill the second trench. And forming a planarized electroplated metal layer together with the first electroplated metal layer. 1 8 · The method for preparing a planarized electroplated metal layer as described in item 17 of the scope of patent application, wherein the metal is copper. 1 9. The planarized metal plating layer described in item 17 of the scope of patent application 0503-8173twf (nl); TSMC2001-1503; Renee.ptd Page 22 1238461 _------- VI. Preparation method of patent application scope γ, wherein the line width of the first trench is less than 1 micron, and the first The line width of the two trenches is greater than 2 microns. 20 • The method for preparing a planarized recording metal layer as described in item 18 of the scope of patent application, wherein the first and second electrolytes containing the metal are copper sulfate solutions. 2 1 · The method for preparing a flattened bond metal layer as described in item 17 of the scope of patent application, wherein the first accelerator is 3-sulfopropyl disulfide or 3-monothiol 1 Propionite (3-mercapto-1-propanesulfonate ° 2 2) The method for preparing a planarized electroplated metal layer as described in item 17 of the patent application scope, wherein the first metal plating solution contains a first The content of the accelerator is 10-100 ppm. 2 3 · The method for preparing a planarized electroplated metal layer as described in item 17 of the scope of the patent application, wherein the first inhibitor is polyalkylene glycols, Copolymers of polyoxyalkyene glycols or polyoxyalkyenes 〇 2 4 · The method for preparing a planarized electroplated metal layer as described in item 17 of the scope of patent application, wherein the first The content of the first inhibitor contained in a metal electroplating solution is 50-200 ppm. 2 5 · The method for preparing a planarized electroplated metal layer as described in item 17 of the patent application scope, wherein the second accelerator is sulfonate Acid propyl disulfide pyl disulfide), sulfonated acetylthiourea, 3-thiol 1-propioxanthate 0503-8173twf (nl): TSMC2001-1503: Renee.ptd, page 23, 1238461___ 6. Scope of patent application ^-(3-mercapto-l-propanesul f onate), dibenzyl-dipropanolyl carboxylic acid -dithio-carbamate), 2-mercaptoethyl sulfite yellow | 2- (3-mercapto-ethanesulfonate) or n, n-dimethyldithiourea- (3-sulfopropyl) S (n, n -dimethyl-dithiocabamic acid- (3-sulfopropyl) ester) ° 2 6 · The method for preparing a planarized electroplated metal layer as described in item 17 of the patent application scope, wherein the second metal plating solution contains a second force The content of σ is 5-50 ppm. 27. The method for preparing a planarized electroplated metal layer as described in item 17 of the scope of patent application, wherein the second inhibitor is polyalkylene glycols (polyalkylene glycols), polyoxyalkylene glycols (Polyoxyalkyene glycols) or copolymers of po 1 yoxya 1 ky enes ° 2 8 · A method for preparing a planarized electroplated metal as described in item 17 of the patent application scope, wherein the second The content of the second inhibition% contained in the metal plating solution is 200-1000 ppm. 2 9. The method for preparing a planarized electroplated metal layer according to item 17 of the scope of the patent application, wherein the second metal electroplating solution further comprises a leveling agent to promote the leveling of the electroplated surface. 30. The method for preparing a planarized electroplated metal layer as described in item 29 of the scope of patent application, wherein the planarizer is a 1 ky 1 at ed polyalkyleneimine or 2-thiol. (2-mercaptothiazline). 3 1 · The planarized metal plating layer described in item 29 of the patent application scope 0503-8173twf (nl); TSMC2001-1503; Renee.ptd page 24 1238461_ VI. Preparation method for patent application, wherein the content of the flattening agent is 20 ppm. 3 2. The method for preparing a planarized electroplated metal layer as described in item 17 of the scope of patent application, further comprising planarizing the metal layer after depositing the metal layer. 3 3. A method for preparing a flattened clock metal layer, including the following steps: providing a semiconductor substrate with a trench; placing the substrate in a first metal plating solution, and applying a voltage to deposit the first plating metal layer on the substrate; In the trench, the first electroplated metal layer is filled into the trench in a bottom-up manner; and the substrate is placed in a second metal plating solution, and voltage is applied for planarization plating to deposit a second electroplated metal. Layer in the trench, so that the second electroplated metal layer and the first electroplated metal layer together form a planarized electroplated metal layer. 3 4. The method for preparing a planarized electroplated metal layer according to item 33 of the scope of patent application, wherein the first metal plating solution includes at least a first electrolyte containing the metal, a first accelerator, and a first The inhibitor is mainly used for depositing the first electroplated metal layer from bottom to top to fill the trench. 3 5. The method for preparing a planarized electroplated metal layer according to item 33 of the scope of the patent application, wherein the second metal plating solution includes at least a second electrolyte containing the metal, a second accelerator, and a first Two inhibitors are mainly used to help level the plating and fill the trench with metal. 3 6. The method for preparing a planarized electroplated metal layer as described in item 34 of the scope of patent application, wherein the first accelerator is 3-dicarboxylic acid propyl disulfide 0503-8173twf (nl); TSMC2001-1503; Renee.ptd, page 25, 1238461 VI. Application scope of patent (3-sulfopropyl disulfide) or 3-mercapto-l-propanesulfonate ° 3 7. The method for preparing a planarized electroplated metal layer according to item 34 of the scope of the patent application, wherein the content of the first accelerated sword contained in the first metal electroplating solution is 10-100 ppm. 38. The method for preparing a planarized electroplated metal layer according to item 34 of the scope of patent application, wherein the first inhibitor may be polyalkylene glycols, polyoxyfluorenyl glycols (polyoxyalkyene glycols) or polyoxyolefins (po 1 yoxya 1 kyenes) copolymers. 39. The method for preparing a planarized electroplated metal layer as described in item 34 of the scope of patent application, wherein the content of the first inhibitor contained in the first metal plating solution is 50-200 ppm. 40. The method for preparing a planarized electroplated metal layer as described in item 35 of the scope of the patent application, wherein the second accelerator is sulfopropyl disulfide, sulfopropyl disulfide, sulfo nated acetylthiourea), 3-thiol 1-propanxanthate (3-1 ^ 1 ^ 301〇-1-01'00031165111 € 〇11377), dibenzyl-dithiol carbamate (dibenzyl -dithio-carbamate), 2-mercapto-ethanesulfonate or η, η-dimethyldithiouric acid- (3-sulfopropyl) acetate (η, η -dimethyl- dithiocabamic acid- (3-sulfopropyl) ester) ° 4 1 · The method for preparing a planarized electroplated metal layer as described in item 35 of the patent application scope, wherein the second metal plating solution contains a second accelerator 0503-8173twf (nl); TSMC200M503; Renee.ptd page 26 1238461 6. The scope of patent application is 5-50ppm. 4 2 · The method for preparing a flattened clock metal layer as described in item 35 of the scope of patent application, wherein the second inhibitor is polyalkylene glycols, polyoxyalkylene glycols Copolymers of polyoxyalkyene glycols or polyoxyalkyenes. 43. The method for preparing a planarized electroplated metal layer as described in item 35 of the scope of the patent application, wherein the content of the second inhibitor contained in the second metal electromine solution is 200-1000 ppm. 44. The method for preparing a planarized electro-mineral metal layer according to item 35 of the patent application, wherein the second metal plating solution further comprises a leveling agent to promote the leveling of the electroplated surface. 4 5. The method for preparing a planarized electroplated metal layer as described in item 44 of the scope of the patent application, wherein the flattening agent is an alkylated polyalky leneimine or 2-thiol 2-mercaptothiazoline). 46. The method for preparing a planarized electroplated metal layer according to item 44 of the scope of the patent application, wherein the content of the planarizer is 1 to 2 p p m. 47. The method for preparing a planarized electroplated metal layer as described in item 33 of the scope of the patent application, further comprising planarizing the metal layer after depositing the metal layer. 48. The method for preparing a planarized electroplated metal layer according to item 33 of the application, wherein the trench is a single damascene trench. 49 · The planarized electroplated metal layer as described in item 33 of the scope of patent application 0503-8173twf (nl); TSMC200M503; Renee.ptd page 27 1238461 6. The method of preparing a patent application, wherein the groove is a double damascene groove. 50. —Metal electric boat composition, comprising: a metal plating solution having the metal ion; an inhibitor, which are polya Iky lene glycols, polyoxyl diols ( p〇ly〇xyaikyene glycols) or copolymers of polyoxylans (ρ ο 1 yoxya 1 kyenes), the content of the inhibitor is 20 0- 1 0 0 0ρρπι; and an accelerator, the accelerator is a sulfonic acid Sulfopropyl disulfide, sulfonated acetyl thiourea, 3-prcapto-1 -propanesulfonate, diphenylmethyl-dithiol amino group Dibenzyl-dithio-carbamate, 2-mercapto-ethanesulfonate or n, n-dimethyldithiouric acid- (3-Shi Yin, acid propyl) from Purpose (η, η-dimethyl-dithiocabamic acid- (3-sulfopropyl) ester), its content is 5-50ppm. 5 1 · The metal plating composition as described in claim 50 of the scope of patent application, wherein the metal is copper. 52. The metal electroplating composition according to item 50 of the scope of application for a patent, wherein the metal ore solution is a copper sulfate solution. 53 · —A method for preparing a mosaic structure, comprising: providing a substrate with a plurality of grooves formed on an upper surface thereof, the grooves having at least two different line widths, and the grooves each having a conductive Surface; providing a first electrolyte and a second electrolyte, wherein the first electrolyte 0503-8173twf (nl); TSMC200M503; Renee.ptd, page 28, 1238461_ VI. The composition of the patent application liquid is an optimized composition for filling trenches with a line width of less than 0.2 microns, and the second electrolytic The composition of the liquid is an optimized composition for filling the trenches with a line width θ greater than 1 micron. The first electrolyte of 5 MH is used to deposit a layer of a suitably thick metal on the substrate to fill the substrate. All trenches with a line width less than 0.2 micrometers, while simultaneously filling the bottom of the trenches with a line width greater than 1 micron on the substrate; and using the second electrolyte to electrically bond another layer of the metal with an appropriate thickness on the substrate to fill the All trenches with a line width greater than 1 micron on the substrate. 54. The method for preparing a mosaic structure according to item 53 of the scope of patent application, wherein the first electrolyte further includes a short-chain polymer having a relatively low molecular weight. 5 5 · The method for preparing a mosaic structure according to item 53 of the scope of patent application, wherein the second electrolyte further includes a long-chain polymer having a relatively high molecular weight. __ 0503-8173twf (nl); TSMC200M503; Renee.ptd page 29