TW410338B - High yield semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device includes a first semiconductor body, a diffusion layer in the first semiconductor body, and a laminated structure of an insulating layer on the first semiconductor body adjacent to the diffusion layer and a conductive layer on the insulating layer. An insulating spacer having a width W is formed on a sidewall of the laminated structure. A second semiconductor body is provided having a shared contact hole for establishing an ohmic contact between the diffusion layer and the conductive layer. The shared contact hole has a center axis located a distance W/2 from an edge of the conductive layer so that portions of the diffusion layer and the conductive layer which are exposed to the outside through the shared contact hole have substantially equal areas.

Description

410338 V. Description of the invention Cl) [Background of the invention] Field of the invention The present invention relates generally to semiconductors, and more specifically, it relates to a semiconductor device and a method for manufacturing the same, which cannot improve the yield of such a semiconductor device. Description of Conventional Technology In a conventional semiconductor device, a stacked structure and a conductive layer are formed on a first semiconductor body as an insulating layer. A plurality of spacers are provided on the sidewall of the stacked structure, and then the first A diffusion layer is formed on the semiconductor body, and one edge of the diffusion layer can be adjacent to one of the spacers. After the formation of a second semiconductor body, a common contact hole is constructed in the second semiconductor body to establish an Ohm contact between the diffusion layer and the conductive layer. It is a common practice to place the common contact holes in place so that their vertical center axis is aligned with the edge of the conductive layer. However, the yield of conventional semiconductor devices is low due to device failures revealed during the inspection stage of manufacturing. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to increase the yield of a semiconductor device. The invention is based on the finding that the opening contact resistance is asymmetric to the central axis, wherein the opening contact resistance changes as a function of the distance from the opening to the central axis of the opening. According to a first aspect of the present invention, a semiconductor device is provided.

Page 5 410338 V. Description of the invention (2) Including: a first body; an insulation layer and an adjacent layer; an insulating spacer having a common contact hole ohmic contact, and one of the conductive layers is exposed to the same body: The silicon layer has a wide hole, and the contact is a semiconductor body exposed by the same silicon; a diffusion layer is located in a stacked structure of the first semiconductor edge layer, and the first semiconductor body is located in the diffusion layer and the diffusion layer. A conductive spacer on the insulating layer, a width W on a side wall of the laminated structure, and a second semiconductor body having one for establishing between the diffusion layer and the conductive layer The common contact hole has a central axis and is located at a distance from the edge W / 2, so that a portion of the diffusion layer and the conductive layer exposed through the common contact hole has a substantially external area. According to the first first semiconductor of the present invention; an insulating layer is one of the above-mentioned extensions, and is located adjacent to and adjacent to each other, and the edge interval is silicified. The above-mentioned edge is used to build an area outside the compound layer. The first aspect of the present invention is to provide a semiconductor device including a multi-body stack j * located in a first semiconductor body and a first semiconductor body; a a plurality of the above-mentioned structure-like junctions; and a first The crystal dream stack is described with an enlarged edge, two halves, and a connecting edge. The first phase in the contact hole and the first and first have equidistant two gold and one middle distance. It belongs to the silicon diffusion structure. / Γ 6? _ Dare layer separates the conductor and the gold mandrel energy layer, which is located in the upper structure. A body is silicon, so that the warp layer is insulated with a metal and a side wall with the second gold and the above. It has a silicide layer on the conductor layer from the common part. Above: It is an ohmic second gold contact hole which is in equal contact with the first silicon layer layer and is connected to the silicon space. Photogenic

410338 V. Description of the invention (3) According to a third aspect of the present invention, a method for manufacturing a semiconductor device is provided, including the following steps: forming a first semiconductor body; and forming a stack of an insulating layer on the first semiconductor body. A layered structure, and a conductive layer formed on the insulating layer; insulating spacers are formed on the side walls of the laminated structure, and each of the spacers has a width W; in the first semiconductor body, a diffusion layer is formed,俾 can make one edge of the enlarged layer adjacent to one of the above-mentioned spacers; form a second semiconductor body; and form a common contact hole in the second semiconductor body for establishing a For the ohmic contact between the conductive layers, a central axis of the common contact hole is located at a distance of W / 2 from an edge of the laminated structure, so that the diffusion layer and the above-mentioned diffusion layer exposed to the outside through the common contact hole can be Parts of the conductive layer have substantially the same area. According to a fourth aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a first semiconductor body; forming a stacked structure of an insulating layer on the first semiconductor body, and the insulating layer A polycrystalline silicon layer is formed on the polycrystalline silicon layer, and a first metal silicide layer is formed on the polycrystalline silicon layer; an insulating spacer is formed on the sidewall of the above-mentioned stacked structure; a diffusion layer is formed in the first semiconductor body, so that this An edge of a diffusion layer is adjacent to one of the spacers; a second metal silicide layer is formed in the diffusion layer, so that an edge of the second metal silicide layer is adjacent to one of the spacers Forming a second semiconductor body; and forming a common contact hole in the second semiconductor body to establish an ohmic contact between the first and second metal silicide layers, one central axis of the common contact hole is located at From the first and second metal silicide layers

Page 7 410338 V. Description of the invention (4) The equal distance between the edges of the invention makes it possible for the diffusion layer and the part of the conductive layer that are exposed to the outside through this common contact hole to have substantially the same area. [Brief description of the diagram] The present invention will be described in more detail with reference to the drawings, wherein: FIG. 1 is a circuit diagram of a unit cell of a conventional static random access memory; t FIG. 2 is a unit cell of FIG. 1 3A and 3B are cross-sectional views of a part of the unit cell along line 3-3 of FIG. 1 to explain the continuous process of forming the unit cell; FIG. 4 is a common contact resistance The representative diagram is a function of the eccentric displacement of the contact hole of a unit cell of a conventional technology from a predetermined reference point; FIG. 5 is a layout diagram of a unit cell according to the present invention; FIG. 6 is a view along FIG. 5 7 is a cross-sectional view of line 6-6; FIG. 7 is a representative diagram of a common contact resistance, which is a function of eccentric displacement of a contact hole of a unit cell of the present invention from a predetermined reference point; A modified embodiment of the invention is a cross-sectional view taken along line 6-6 of FIG. 5. [Symbol description] VDD ~ voltage source

410338 V. Description of the invention (5) 0 ~ reference point 1, 1 '~ drive gate 1 η, Γ η ~ NMOS transistor 1ρ, 1' ρ ~ PM0S transistor 3, 3 '~ transmission gate 3n, 3' η ~ NM0S transistors 5 ', 5, 30Common contacts 7, 8, 8' ~ word line 11, 11 '~ 卩 -type diffusion layer 12, 12' ~ η-type diffusion layer 1 3, 1 3 '~ polycrystalline silicon gate 9, 1 5, 1 6, 1 7, 9 ', 1 5', 16 ', 1 7' ~ contact 1 8, 1 8 '~ metal layer 2 1 ~ p type silicon substrate 22 ~ p type well 2 3 to channel stopper 2 4 to silicon dioxide layer 25 to first metal silicide layer 2 6 a, 2 6 b to sidewall spacer 2 7 to second metal silicide layer 28 to interlayer film 2 9-• photoresist 3 b n-type diffusion region

Page 9_ 410338 V. Description of the invention (6) ~ '[Detailed description of the preferred embodiment] Before carrying out the detailed description of the present invention, a static RAM is used as a typical example (refer to Figures 1 to 4), which can be proved The problem description of conventional technology is helpful r °, as shown in Figure 1, a 6-transistor unit cell of conventional static RAM is composed of a pair of driving gates 1 and 丨 'and a pair of transmission gates 3 and 3, Composed of. Each of the driving gates 1 and Γ is composed of a PM0S transistor "p" and an NM0S transistor "n'_. The driving gate transistor 1? Is connected to the gate electrode system 2 and cross-coupled A circuit node, or cross-coupled to a common contact 5 connecting the driving gate transistor p and the drain of 1 ′ η, and the driving gate transistor 1 P and the gate electrode system of 1 η are connected together and cross-coupled to A circuit node or cross-consumption is connected to a common connection point 5 that connects the drain electrode of the driving gate transistor 1 ρ and η. The sources of the two driving gates PM0S transistors lp and 丨, ρ are connected to a voltage supply VDD 'and the sources of the two driving gates NM0s transistors η and 丨' ^ are grounded. Each transmission gate 3 and 3 'is composed of a NM0S transistor connected to a word line 7. The transmission gate NM0S transistor 3η connects its source to a circuit node 9 to a bit line 8' and makes Its drain is connected to circuit node 5; and the transmission gate NM 0 S transistor 3 ′ η makes its source to a circuit node 9 to a bit line 8 ′ and its drain to a common contact 5 '. The layout of the unit memory cell is shown in FIG. 2. In the driving gate, the PM0S transistor lp is formed by a p-type diffusion layer. The source region of the transistor 1 ρ is connected to the voltage source Vdd via a contact 15 and the drain region is Connected to a metal layer 8 through a contact 17. The NMOS transistor is formed by a horizontal extension of an inverse L-shaped n-type diffusion layer 12. Transistor

Page 10 410338 V. Description of the invention (7) The source region of 1 η is grounded via -contact 丨 6, and its drain region is connected to metal layer 1 via a contact forming one of the circuit nodes 5 of Fig. 1 8. The channel regions of the transistors 1 P and 1 η are both connected to a polysilicon gate 3. The layout of the driving switch Γ is similar to that of the driving gate 1 ^ The PM0S transistor Γρ is formed by a ρ-type diffusion layer 11 ′, and the source region of the transistor 丨, ^ is connected through a contact 15 is connected to the voltage source Vdd, and the drain region is connected to a metal layer 18 through a contact 17 ′. The nmOs transistor Γ η is formed by a horizontal extension of an inverse L-shaped η-type diffusion layer 12. The source region of the transistor 1 'π is grounded via a contact 16', and its drain region is connected via a common contact 5 '. The channel regions of the transistor 丨 'ρ and 1, η are all connected to a polysilicon gate 丨 3'. The polycrystalline silicon gate 1 3 connecting the transistor 1 ρ and the drain of 1 η is made into a shape so that it can be horizontally extended into the area of the other driving gate 1 ′ and connected to the common contact 5. . Similarly, the polycrystalline silicon gates 13 connecting the transistors i 'ρ and the terminals of 丨' η have a horizontally extending portion connected to the common connection 45. The NM0S transistor transistor 3η is formed by a vertical extension of the η-type diffusion layer 12, wherein the source region of the transistor 3η is connected to the word line 7 via a contact 9, and the drain region is Connect to common contact 5 and contact 1 7. Similarly, the NMOS transmission transistor 3, η is formed by the vertical extension of the η-type diffusion layer 12, wherein the source region of the transistor 3 'II is connected to the word line 7 via a contact 9 . In this transistor 3 η, the pole region is connected to the contact 1 7 ′ and the common contact 5 ′. As shown in Figs. 3A and 3B, one of the unit cells surrounding the common contact point 5 is-

Page 11 410338 V. Description of Invention (8) A vertical section is formed in successive stages. As shown in FIG. 3A, the section section has a P-type well 22 formed on a P-type silicon substrate 21 and a 22-type well 2 2 is ion-implanted to form an 11-type diffusion layer 12 and a local oxidation technique is used to A channel stop 23 is formed in 22, and then a silicon dioxide layer 24 'is formed on the p-well 22, which can cover an area of 丼 22, which extends from the edge of the n-type diffusion layer 12 to A point on the edge of the passage stop 23. A part of the polycrystalline silicon gate 1 3 'is formed on the dioxide layer 24. / In order to reduce the sheet resistance of the memory cell, the surface of the polysilicon gate 1 3 ′ and the n-type diffusion layer are coated with a metal silicide layer. The polysilicon gate 1 3 ′ is first coated with a metal silicide layer 25, and the insulating sidewall spacers 2 6 a and 2 6 b are deposited on the sidewalls of the laminated structure of the layers 2 4, 1 3 ′ and 25 . Then, a metal silicide layer 27 is deposited on the n-type diffusion layer 12 and the p-type diffusion layer 11. The side wall spacers 2 6 a and 2 6 b insulate the metal silicide layer in all regions of the diffusion layer from the polysilicon gate 1 3 '. Then, the memory unit is covered with an interlayer film 28, and a photoresist 29 is set to expose a part of the interlayer prelayer 28. Next, the memory unit is irradiated through the optical nozzle 29 and etched to form a common contact hole 'which is a common contact 5' as shown in FIG. 3B. With this etching process, the sidewall spacer 26a is also removed, and a part of the n-type diffusion layer 12 and a part of the metal silicide layers 25, 27 are left for passing through the common contact 5. The opening is exposed to the outside. Then, the opening of the common contact 5 is filled with a conductive material, so that the drain region of the n-type diffusion layer 12 can be brought into ohmic contact with the polysilicon gate 1 3 '. The photoresist 2 9 is usually placed in an appropriate position so that the common contact hole 5

Page 12

5 'Explanation (9) ______

Center car by ^ & H

The anchor of Γ is at the edge of the dry metal silicide layer 25. Because A 囹 M's + conductor structure system and Yau Tongyun Zhuo, because the structure surrounding the common contact point and the structure surrounding the common contact point 5 is JJ :, it is said that the area of the metallization layers 25 and 27 is equal to, and exposed in the common The resistance of the contact hole 5 shows a significant asymmetric characteristic. The common contact 5 is shown in FIG. 4 as a function of the eccentric displacement.) ^^^ ® ^ / Λ shows a significant ϋ! One on the right side, 0.05 ㈣ contact The displacement of hole 5 shows the increased resistance of c. However, until the distance of opening 5 from the reference point to the left is 0.14 micrometers, an almost stable displacement can be maintained. Due to the inherent manufacturing tolerances, this asymmetric contact The cause of the failure of the resistance characteristic t, resulting in a low yield a, "" In addition, it is found that the surface of the diffusion layer 丨 2 existing in the sidewall spacer 26a is depleted of necessary impurities, and due to the lack of metal The broken material layer 27 is prone to physical abrasion. Therefore, the memory cell generates an undesired leakage current. FIG. 5 is a layout diagram of a static RAM unit cell according to the present invention. In FIG. 5, the important parts corresponding to those in FIG. 2 are designated by the same numbers as those used in FIG. In the present invention, the contacts 30 and 30 'are provided to correspond to the common contacts 5 and 5' of the conventional technology. The common contacts .30 and 30 'are placed at appropriate positions 1 3' and 1, 3 respectively slightly away from the polysilicon gate. Fig. 6 shows a detailed structure around the common contact point 30. It can be seen that the common contact hole 30 is placed in a proper position ’, so that its center is located at the silicon silicide

Page 13 410338 V. Description of the Invention (ίο) The distance of the edge W / 2 of the object layer 25 ′ is the width of each of the sidewall spacers 26a and 26b. Please note that this width is the same as the width of the removed sidewall spacer 26a, and therefore the same as the spacing between the edges of the metal silicide layers 25 and 27. Therefore, the present invention intends to make the center of the contact hole 30 at an equal distance from the edges of the two metal silicide layers. The areas of the metal silicide layers 25 and 27 exposed to the outside through the common contact hole 30 are the same size. The resistance curve of one unit cell of FIG. 5 is plotted as a function of the eccentric displacement shown in FIG. The expected center of the opening (ie, the edge W / 2 away from both the metal silicide layers 25 and 27) is represented by reference point 0 on the horizontal axis of this figure. We can see that the eccentric displacement of the common contact hole 30 shows a generally symmetrical ohmic relationship with a distance of 0.09 micrometers to the left and right of the reference point. Therefore, the position of the common contact hole 30 can allow a range of ± 0.09 m. In one embodiment, it is useful to implant n-type impurities, for example, doping phosphorus into the common contact hole 30 at an energy level of 30 to 70 keV and a dose of 5 X 1 014cnr2 to 5 X 1 015cnT2. This impurity doping results in the formation of an n-type diffusion region 31. In fact, the π-type diffusion region 31 can increase the impurity concentration in the n-type diffusion layer 12 region, and the n-type diffusion layer 12 is not The metal gauze layer 27 is covered. Unwanted leakage current is removed in this way. Therefore, the resistance at the common contacts 30 and 30 'is reduced, which may achieve a high-speed read / write operation mode of the static RAM. The problem of leakage current can also be solved by an embodiment shown in FIG. 8. In this embodiment, when the sidewall spacers 26a and 26b are formed before the common contact hole 30 is formed, an anti-etching material is used, so that the spacer 26a can be etched with a material to resist corrosion and remain intact (such as 32). this

Page 14 41G338_ V. Description of the invention (11) The anti-etching material may be a substance different from the interlayer film 28. If silicon dioxide is used as the interlayer film 28, silicon nitride can be used as the sidewall spacers 26a and 26b, and the interlayer film 28 is processed by using a process using a 20% oxide-to-nitride selection ratio. Etching.

Claims (1)

410338 VI. Scope of patent application 1. A semiconductor device comprising: a first semiconductor body (21, 22, 23); a diffusion layer (12; 1 factory) located in the first semiconductor body; an insulating layer (2 4) a laminated structure, located on the first semiconductor body, adjacent to the diffusion layer and a conductive layer (13 ,; 13) on the insulating layer; an insulating spacer (2 6 b) Is located on one side wall of the laminated structure, the spacer has a width W; and a second semiconductor body (28) has a common contact hole (30; 30 ') for establishing in the diffusion layer ( 12; 1Γ) and ohmic contact between the conductive layer (13 '; 13), the common contact hole has a central axis, is located at a distance W / 2 from one edge of the conductive layer, and can pass through the common layer Portions of the diffusion layer and the conductive layer where the contact holes are exposed to the outside have substantially the same area. 2. A semiconductor device comprising: a first semiconductor body (21, 22, 23); a diffusion layer (12; 1Γ) provided in the first semiconductor body; a stack of an insulating layer (24) Structure, located on the first semiconductor body and adjacent to the diffusion layer, a polycrystalline silicon layer (1 3 ′; 1 3) on the insulating layer, and a polycrystalline silicon layer (1 3 ^; 1 3 ) —Metal silicide layer (2 5); an insulating spacer (2 6 b) located on one side wall of the laminated structure; a second metal silicide layer (27) located on the diffusion layer The first Page 16 410338 VI. Patent Application Range The distance between the edge of the metal silicide layer and the edge of the laminated structure is equal to the width of the spacer; and a second semiconductor body (28) with a common contact hole (30; 30 ') for establishing an ohmic contact between the first and second metal silicide layers (25, 27), the common contact hole having a central axis located between the first and second metal silicide layers The equal distances between the edges of the metal silicide layer enable the portions of the first and second metal silicide layers exposed to the outside through the common contact hole to have substantially the same area. 3. The semiconductor device according to item 2 of the application, wherein the second metal silicide layer (27) and the diffusion layer (12; 11 ') share an impurity having the same conductivity type as the diffusion layer. Part of the doping (31). 4. A semiconductor device comprising: a first car conductor body (2 1, 2 2, 2 3); a diffusion layer (12; 11 ') located in the first semiconductor body; an insulating layer (2 4 ) Is a stacked structure, which is located on the first semiconductor body and is adjacent to the diffusion layer, a polycrystalline silicon layer (1 3 ′; 1 3) on the insulating layer, and a polycrystalline silicon layer ( 1 3; 1 3) a first metal silicide layer (25); insulating spacers (2 6 a, 2 6 b) are respectively located on the side walls of the laminated structure; a second metal silicide layer (27) In the diffusion layer, the second metal silicide layer has an edge adjacent to one (2 6 a) of the space and the partition; and a second semiconductor body (28) having a Common contact hole (30; Page 17 410338 VI. Application for patent scope 30 '), used to establish an ohmic contact between the first metal silicide layer (27) and the second metal silicide layer (13'; 13), the common The contact hole has a central axis located at an equal distance from the edges of the first and second metal silicide layers, so that portions of the first and second metal silicide layers exposed to the outside through the common contact hole have Substantially the same area. 5. A unit cell or a static random access memory, comprising: a first semiconductor body (21, 22, 23); a diffusion layer (12; 11 ') located in the first semiconductor body; an insulation A layered structure of layer (24), located on the first semiconductor body, adjacent to the diffusion layer and a conductive layer (1 3 '; 1 3) on the insulating layer; an insulating spacer ( 2 6 b), which is located on one side wall of the laminated structure, the spacer has a width W; and a second semiconductor body (28), which has a common contact hole (30; 30 ′), for An ohmic contact is established between a portion of the diffusion layer (1 2; 1 1 ') and the conductive layer (1 3'; 1 3), and the common contact hole has a center draw, located from the conductive layer A distance of one edge W / 2 enables the diffusion layer and the portion of the conductive layer exposed to the outside through the common contact hole to have substantially the same area. 6. A unit cell of a static random access memory, comprising: a first semiconductor body (21, 22, 23); a diffusion layer (12; 1Γ) located in the first semiconductor body; Page 18 410338 VI. Patent application scope A laminated structure of an insulating layer (24) is located on the first semiconductor body and is adjacent to the diffusion layer and a polycrystalline silicon layer (1 3) on the insulating layer 1; 1), and a first metal petroxide layer (25) on the polycrystalline silicon layer (1 3 1; 1 3); an insulating spacer (2 6 b) in the laminated structure On a side wall; a second metal silicide layer (27) located in the diffusion layer, the distance between the edge of the second metal silicide layer and the edge of the first metal silicide layer is equal to the width of the spacer And a second semiconductor body (28) having a common contact hole (30; 30 ') for establishing an ohmic contact between the first and second metal silicide layers (25, 27), The common contact hole has a central axis located at an equal distance from the edges of the first and second metal silicide layers, so that the first and second metal silicide layers exposed to the outside through the common contact hole can Parts have substantially the same area. 7. For example, the sixth unit B of the scope of the patent application, wherein the second metal silicide layer (2 7) and the diffusion layer (1 2; 1 1 ′) share the same conductivity as the diffusion layer. Part of the type of impurity doping (31). 8. — A unit cell of static random access memory, comprising: a first semiconductor body (21, 22, 23); a diffusion layer (12; 11 ') located in the first semiconductor body; an insulation A layered structure of layer (24) on the first semiconductor body, adjacent to the diffusion layer, a polycrystalline silicon layer (1 3 '; 1 3) on the insulating layer, and a layer The first layer on the polycrystalline silicon layer (1 3 '; 1 3) Page 19, 410338 VI. Patent application scope-a metal dream layer (2 5); insulating spacers (2 6 a, 2 6 b) are respectively located on each side wall of the laminated structure; a second metal silicide A layer (27) in the diffusion layer, the second metal silicide layer having an edge adjacent to one (2 6 a) of the spacer; and a second semiconductor body (28) having a common feature A contact hole (30; 30 ') for establishing an ohmic contact between the first metal silicide layer (27) and the second metal silicide layer (13'; 13); the common contact hole has a The central axis is located at an equal distance from the edges of the first and second metal silicide layers, so that portions of the first and second metal silicide layers exposed to the outside through the common contact hole have substantially the same region. 9. A method for manufacturing a semiconductor device, comprising the following steps: a) forming a first semiconductor body (21, 22, 23); b) forming a laminated shape of an insulating layer (24) on the first semiconductor body A buckle structure, and forming a conductive layer (1 3 ′; 1 3) on the insulating layer; c) forming an insulating interlayer (2 6 a, 2 6b) on the sidewall of the laminated structure, each of which The spacer has a width W; d) In the first semiconductor body, a diffusion layer (12; 1 1 ') is formed, so that one edge of the diffusion layer is adjacent to one of the spacers (2 6 a); e) forming a second semiconductor body (28) and f) forming a common contact hole (30; 30 ') in the second semiconductor body for establishing a diffusion layer (12; 1Γ) And the conductive layer Page 20 4IG338 6. Ohm contact between patent applications (1 3 '; 1 3). One of the common contact holes has a central axis located at a distance of W / 2 from one edge of the laminated structure. A portion of the diffusion layer and the conductive layer exposed to the outside through the common contact hole have substantially the same area. 10. The method according to item 9 of the scope of patent application, further comprising the step of removing one of the spacers (26a) located within the common contact hole. 11. The method of claim 10, further comprising the step of doping an impurity of the same conductivity type as the diffusion layer through the common contact hole. 12. A method for manufacturing a semiconductor device, comprising the following steps: a) forming a first semiconductor body (21, 22, 23); b) forming a laminated shape of an insulating layer (24) on the first semiconductor body Structure, forming a polycrystalline silicon layer (1 3 '; 1 3) on the insulating layer, and forming a first metal petrochemical layer (25) on the polycrystalline silicon layer; c) in the laminated structure An insulating spacer (2 6 a, 2 6b) is formed on the sidewall of the substrate; d) a diffusion layer (12; 1Γ) is formed in the first vertical conductor body, i 俾 can make one edge of the diffusion layer adjacent to One of the spacers (26a); e) forming a second metal silicide layer (27) in the diffusion layer, so that an edge of the second metal silicide layer is adjacent to one of the spacers (2 6 a) ;, f) forming a second semiconductor body (28); and g) forming a common contact hole (30;) in the second semiconductor body Page 21, 410338 VI. Application for patent scope 30 '), used to establish an ohmic contact between the first and second metal silicide layers (25, 27), one of the common contact holes is located at the central axis The equal distance between the edges of the first and second metal silicide layers enables the portions of the diffusion layer and the conductive layer that are exposed to the outside through the common contact hole to have substantially the same area. 13. The method of claim 12 further includes the step of removing one of the spacers (26a) located within the common contact hole. 14. The method according to item 13 of the patent application scope, further comprising the step of doping an impurity of the same conductivity type as the diffusion layer through the common contact hole. Page 22