TW409380B - Integrated circuit package with uncut chip and its manufacture method - Google Patents

Integrated circuit package with uncut chip and its manufacture method Download PDF

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Publication number
TW409380B
TW409380B TW088107665A TW88107665A TW409380B TW 409380 B TW409380 B TW 409380B TW 088107665 A TW088107665 A TW 088107665A TW 88107665 A TW88107665 A TW 88107665A TW 409380 B TW409380 B TW 409380B
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Taiwan
Prior art keywords
wafer
lead
uncut
integrated circuit
patent application
Prior art date
Application number
TW088107665A
Other languages
Chinese (zh)
Inventor
John Liu
Original Assignee
Chipmos Technologies Inc
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Priority to TW088107665A priority Critical patent/TW409380B/en
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Publication of TW409380B publication Critical patent/TW409380B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

An integrated circuit package with uncut chip has at least two uncut integrated circuit chips. On the upper surface of said integrated circuit chip, there are a plurality of chip welding pads. A tape having a plurality of bonding leads is pasted on the upper surface of said chip so that a plurality of bonding leads will be sited above said welding pad. The bonding lead on said tape is wire bonded on said chip welding pad so that the chip welding pad and the bonding lead on said tape will be electrically connected. An encapsulation material is to encapsulate the connection place of said welding pad and said bonding lead. A plurality of solder balls are formed on said tape. This invention could package several uncut low volume DRAM into the integrated circuit package of one high volume DRAM.

Description

40938Q 五、發明說明（1) 【發明領域】 本發明係有關於一種具有未切割晶片之積體電路封裝體 及其製造方法’特別是有關於一種將數顆未切割之低容量 動態隨機存取記憶體封裝為一顆高容量動態隨機存取記憶 體之積體電路封裝體及其製造方法。 【先前技術】40938Q V. Description of the Invention (1) [Field of the Invention] The present invention relates to an integrated circuit package with an uncut wafer and a method for manufacturing the same. The memory package is an integrated circuit package of a high-capacity dynamic random access memory and a manufacturing method thereof. [Prior art]

目前之1 28百萬位元（Mega Byte)動態隨機存取記憶體封 裝主要採用一顆單一 1 2 8百萬位元動態隨機存取記憶體晶 片配合引線（wire bonding)封裝或其他習用之封裝方式製 成。相較於128百萬位元動態隨機存取記憶體，較低容量 之64百萬位元動態隨機存取記憶體之技術已臻純熟，發展 中之128百萬位元動態隨機存取記憶體其成本及晶片面積 均高於64百萬位元動態隨機存取記憶體之兩倍以上。是以 ’在單晶片之1 28百萬位元動態隨機存取記憶體技術未躁气 成熟之際，其成本並不具市場競爭力〇此外，一顆128百 萬位元動態隨機存取記憶體之晶片面積為150nim2而兩顆6 4 百萬位元動態隨機存取記憶體晶片之總面積僅1 24mm2，利 ^ 用晶片尺寸封裝（Chip Scale Package)技術可使兩顆64百 萬位元動態隨機存取記憶體晶片封裝體之總面積僅較小於 一顆1 28百萬位元動態隨機存取記憶體晶片封裝體之面積 Q 。此外，採用引線封裝方式之記憶體’由於引線長度之下 -限無法降低，此長引線在高頻操作下將產生雜訊而限制系 統外頻之高頻要求。 ' 再者，針對較小面積晶片之封裝，習用技術中採用加上At present, the 1 28 million-bit (Mega Byte) dynamic random access memory package mainly uses a single 128-bit DRAM chip with wire bonding package or other conventional packages. Way made. Compared with 128Mbit DRAM, the technology of 64Mbit DRAM with lower capacity has matured, and 128Mbit DRAM is under development Its cost and chip area are more than twice that of 64 million bits of dynamic random access memory. Therefore, at the time when the single 28-bit dynamic random access memory technology is not mature enough, its cost is not competitive in the market. In addition, a 128 million-bit dynamic random access memory The chip area is 150nim2 and the total area of two 64 Mbit DRAM chips is only 1 24mm2. Using Chip Scale Package technology can make two 64 Mbit dynamic The total area of the random access memory chip package is only smaller than the area Q of a 128-bit dynamic random access memory chip package. In addition, the memory of the lead package method cannot be reduced due to the lower limit of the lead length. This long lead will generate noise under high frequency operation and limit the high frequency requirements of the system's external frequency. '' Furthermore, for small-area chip packages,

409380 五、發明 ~ % m,, 。然 Uxtensi0n ring)之方式’以增加錫球 過複中’ ΐ於延伸環與晶片間之熱膨脹係數不同409380 V. Invention ~% m ,,. However, the Uxtensi0n ring) method is used to increase the solder ball. The thermal expansion coefficient between the extension ring and the wafer is different.

Ue U之高溫處理後’會影響到封裝體之穩定性 由於曰111七Υ ) °此外’由0 . 2 5微米製程到0. 2微 習早晶f之面積縮小，會影響到延伸環之使用 之g用堆疊封裝技術利用三度空間堆疊技術可將 方=片封裝於一單一封裝體中。堆疊封裝技術提 以增加動態隨機存取記憶體（DRAM)之記憶容 =半導體封裴裝置之厚度與須不同形狀之導線 生雜訊，已無法符合半導體業者之未 【發明目的】 =2明之主要目的在提供一種具有未切割晶片 ^震體及其製造方法，將複數未切割之晶片封 封裝體中以提升封裝效率。 路在提供一種具有未切割晶片 封裝體及其製造方法，將複數未切割之低容量 圭:Ϊ ΐ憶體晶片封裝為一顆高容量動態隨機存取 ’裝體，藉封裝複數低成本之低容量記憶體之方 相同高容量但成本高之記憶體以降低生產成本。 本發明之另一目的在提供一種具有未切 路封裝體及其製造方法，在針對較小面積之晶片 =須使用延伸環，以避免面積縮小之晶片不$用 情事。 本發明之再一目的在提供一種具有未切割晶片 置放面積 ，於封裝 米製程， ΰ 兩個以上 供一有效 量°但堆 架製程容 求。 之積體電 裝於一單 之積體電 動態隨機 記憶體之 式，取代 之積體電 封裝時， 延伸環之 之積體電After Ue U's high temperature treatment, it will affect the stability of the package due to 111 Υ) ° In addition, the area of the premature crystal f will shrink from 0.25 micron process to 0.2 micron, which will affect the extension ring. The stacking packaging technology used uses three-dimensional space stacking technology to package square chips in a single package. Stacked packaging technology is proposed to increase the memory capacity of dynamic random access memory (DRAM) = the thickness of semiconductor packaging devices and the need for different shapes of wires to generate noise, which is no longer in line with the semiconductor industry's [inventive purpose] = 2 The object is to provide a vibrating body with uncut wafers and a method for manufacturing the same, encapsulating a plurality of uncut wafers into a package to improve packaging efficiency. Lu Zai provides an uncut chip package and a manufacturing method thereof. The uncut low-capacity chip can be packaged into a high-capacity dynamic random access package with a low cost. The capacity of the memory is the same as the high-capacity but high-cost memory to reduce production costs. Another object of the present invention is to provide an uncut package and a method for manufacturing the same. For a wafer with a small area, an extension ring must be used to avoid the use of a wafer with a reduced area. Yet another object of the present invention is to provide an uncut wafer placement area in a packaged rice manufacturing process, providing more than two for an effective amount but a stacking process capacity requirement. The product of the integrated circuit is assembled in a single integrated circuit of dynamic random memory, which replaces the integrated circuit of the extension ring when it is packaged.

C:\Program Files\Patent\PK6684.ptd 第 5 頁 4 409380 五、發明說明（3) 其製造其封裝體之引線較習用引線封裝 線；；免引線過長而會在高頻操作下引起雜 ，而可增加系統外頻之高頻要求。 封裝體具有一包含至少兩具有未切割晶片之積體電路 體電路丄體電路晶片，該積 ί Ϊ 引線帶(t_)站設於該晶片上表 接引綠ϊί連接引線位於該焊墊上方，·引線帶上之連 該晶片焊塾上，使晶片焊塾與該引線帶上之 後遠拉電性連接’―封膠物質於該焊塾與該連接引 處予以密封；及複數錫球形成於該引線帶上。 體曰Ϊ :::兩塊未切割之64百萬位元動態隨機存取記憶 =封”一！28百萬位元動態隨機存取記憶體積體電 ^封裝，以k供較低之晶片製作成本及較小之面積。此< 2本發明中採用引 '線帶自動封裝技術（TAB)，利用一引 未切割晶片上之焊塾進行封裝，可在不須採 Ιϊίίί下’得到面積小之封裝體，並利用引線帶 接引線接近晶片焊塾之㈣，可直接在焊塾位置悍接 3 $線，藉此短引線之結構有效降低引線長度，而 佳之外頻要求。 付平乂 讓本發明其上述和其他之目的、特徵與優點能更明 顯被揭二，下文特舉本發明之較佳實施例，並配合所附圖 示’作詳細說明如下。 【圖式說明】C: \ Program Files \ Patent \ PK6684.ptd Page 5 4 409380 V. Description of the invention (3) The lead used to make its package is more than the conventional lead packaging wire; free lead is too long and it will cause noise under high frequency operation. , And can increase the high frequency requirements of the system's external frequency. The package has an integrated circuit body circuit chip including at least two uncut chips. The integrated lead wire strip (t_) is located on the wafer and the lead wire is connected above the bonding pad. · The wafer solder pad on the lead strip is connected to the wafer pad and the lead strip is electrically connected at a distance after the wafer is sealed—the sealing material is sealed at the solder pad and the connection lead; and a plurality of solder balls are formed on The lead is on.体 说 ::: Two uncut 64 Mbits of dynamic random access memory = encapsulation! One 28 Mbits of dynamic random access memory volume is electrically packaged, and k is used for lower chip production Cost and smaller area. This < 2 in the present invention adopts the lead wire automatic packaging technology (TAB), using a lead on the uncut wafer for packaging, can be obtained without the need of Ιϊίίί ′ The package body, and the use of lead strips to connect the leads to the wafer pads, can directly connect 3 $ wires at the position of the solder pads, so that the short lead structure can effectively reduce the length of the leads, and the best external frequency requirements. The above and other objects, features, and advantages of the present invention can be more clearly disclosed. The preferred embodiments of the present invention will be described below, and the accompanying drawings will be described in detail below. [Schematic description]

40988G 五、發明說明（4) ---- 第1圖：.本發明中未切割晶片之透視圖； 第2圖：本發明中未切柯晶只命2丨祕掷 , .引線帶下方設m 片與⑽帶之剖視圖’其中 第3圖·第2圖中未切割晶#加上填充踢後之剖視圖； 第^圖：本發明中未切割晶片與引線帶藉塗佈填充膠貼 合之不意圖， 第5 ® :本發明中未切割晶片與弓丨線帶藉彈性膠钻合之 示意圖； 第6圖：本發明甲將貼合之弓丨線帶打線至晶片之剖視 圖， 第7圖··本發明中導線帶内電路佈局之俯視圖； 第8圖.本發明中將打線部位封膠後之剖視圖； 第9圖.本發明中將封膠後之封裝體加上錫球後之剖視 圖； 第1 0圖：本發明中藉真空吸著方式置放錫球之示意< 圖。 【圖號說明】 2 引線帶 23 凸塊 31 彈性膠 1 晶片 11 焊墊 21 連接引線 22 本體 24焊墊 3 填充膠 4 封膠材料 5 錫球 【發明說明】 本發明之具有未切割晶片之積體電路封裝體及其製造方 法主要利用引線帶自_動焊接（Tape Automated Bonding，40988G V. Description of the invention (4) ---- Figure 1: Perspective view of the uncut wafer in the present invention; Figure 2: Uncut Ke Jing in the present invention will only die 2 丨 secret throw,. A cross-sectional view of the m piece and the ribbon. Among them, FIG. 3 and FIG. 2 are the uncut crystals and the cross-sectional view after the filling kick. FIG. No intention, 5th: schematic diagram of the uncut wafer and the bow 丨 wire band drilled by elastic glue in the present invention; FIG. 6: the cross-sectional view of the present invention wire bonding the bow 丨 wire band to the wafer, FIG. 7 ·· Top view of the circuit layout of the lead wire in the present invention; Figure 8: A cross-sectional view of the present invention after the wire bonding portion is sealed; Figure 9: A cross-sectional view of the present invention after the encapsulated body is added with a solder ball Figure 10: Schematic diagram of placing a solder ball by vacuum suction in the present invention < [Illustration of the drawing number] 2 lead strips 23 bumps 31 elastic glue 1 wafer 11 solder pads 21 connecting leads 22 body 24 solder pads 3 filling glue 4 sealing material 5 solder balls [Explanation of the invention] The product with uncut wafers Body circuit package and manufacturing method thereof mainly use tape auto bonding (Tape Automated Bonding,

C:\Prograra F iles\Patent\PK6684. ptd 第 7 頁 409380C: \ Prograra Files \ Patent \ PK6684.ptd p. 7 409380

五、發明說明（5) TAB)結合球格陣列（BGA)技術，將兩顆未切割之低容量動 態隨機存取記憶體晶片封裝為一顆高容量動態隨機存取記 憶體’例如將兩顆未切割之64百萬位元動態隨機存取記^ ^(64M DRAM) ’封裝形成一128百萬位元之記憶體 DRAM)封裝體。 ~ 請參考第1圖’圖中顯示一待封裝之未切割晶片^，該晶 片中包含兩顆未切割之64百萬位元動態隨機存取記憶體 (64M DRAM)晶片。圖中虛線為預定形成以百萬位元動態隨 機存取記憶體晶片之切割道（S c r i b e 1 i n e )，每一個別之 64百萬位元動態隨機存取記憶體晶片均含有複數個焊墊 (bonding pad)ll形成晶片與外界之電性接觸點。本發明 中雖以兩顆未切割64百萬位元動態隨機存取記憶體封裝為 一顆128百萬位元動態隨機存取記憶體為較佳實施例’然 此僅係供說明用’而非用以限定本發明，晃封裝方式亦^^ 應用於將其他容量之複數顆未切割晶片封裝為一顆高容量 動態隨機存取記憶體。另、焊墊11之分佈亦不限於圖中之 中央焊墊（central bonding pad)形式，而可應用於其他V. Description of the invention (5) TAB) combined with ball grid array (BGA) technology, packaging two uncut low-capacity dynamic random access memory chips into a high-capacity dynamic random access memory chip, such as two Uncut 64 million-bit dynamic random access memory ^ ^ (64M DRAM) 'package forms a 128-megabit memory DRAM) package. ~ Please refer to Figure 1 ′, which shows an uncut wafer to be packaged ^, which contains two uncut 64 Mbit dynamic random access memory (64M DRAM) chips. The dashed line in the figure is a scribe line (Scribe 1 ine) that is planned to form a megabit dynamic random access memory chip. Each individual 64 megabit dynamic random access memory chip contains a plurality of pads. (bonding pad) 11 forms an electrical contact point between the wafer and the outside. In the present invention, although two uncut 64 million-bit dynamic random access memories are packaged into one 128 million-bit dynamic random access memory, it is a preferred embodiment, but this is for illustration only. It is not intended to limit the present invention, and the package packaging method is also applied to package a plurality of uncut chips with other capacities into a high-capacity dynamic random access memory. In addition, the distribution of the bonding pads 11 is not limited to the form of the central bonding pad in the figure, but can be applied to other

習用之焊墊分佈形式，如分佈於晶片兩側之周緣焊勢 (peripheral bonding pad)形式等。雖然下文主要以動w 隨機存取記憶體晶片為本發明之較佳具體實施例加以説 明’然而本發明之具有複數未切割晶片之積體電路封装體 及其製造方法並不限於動態隨機存取記憶體晶>1封裝體’ 其他形式及種類之晶片封裝體亦可由本發明達成° 再請參照第2圖，圖中所示為一未切割晶片1及/引線Conventional bonding pad distribution patterns, such as peripheral bonding pad patterns distributed on both sides of the wafer. Although the following mainly describes a dynamic w random access memory chip as a preferred embodiment of the present invention, 'the integrated circuit package with a plurality of uncut chips of the present invention and its manufacturing method are not limited to dynamic random access Memory chip > 1 package 'Other types and types of chip packages can also be achieved by the present invention. Please refer to FIG. 2 again, which shows an uncut chip 1 and / lead

40938C 五、發明說明（6) (TAB tape)2之剖視圖。圖中晶片1上之虚線為切割線，焊 墊11形成於晶片1之上表面，用以供引線將焊墊電性連接 .至外部元件》引線帶2設於晶片1上表面上方，其組成及結 構係習知技術，主要係將導線（如鋼線）結合聚合物材料之 本體22，其結構主要係將印刷電路佈局設於聚合物本體22 中（圖中未示出）再引出連接引線（bonding lead)21至聚合 物本體22外。引線帶2下方設有凸塊23用以提供較佳之機 械強度。 再請參考第3圖及第4圖，此為將引線帶2貼合至晶片1之 示意圖。在第4圖中顯示，在晶片1上方非焊堅之部位先塗 伟一層填充膠（underfill) 3作為附著劑（attachment agent) ’再將引線帶2貼合至填充膠3而黏贴至晶片1上。 填充膠3除可提供黏著之作用外’另可降低晶片1與引線帶（ 2間由於熱膨脹係數差而在溫差變化率大時產生之位差效 應（TCE mismatch)。將引線帶2黏貼至晶片1上之方式並不 限於前述方式，亦可以其他習用或變化之黏貼方式達成， 如將附者劑.製於引線帶2下方再進行貼合，_即先將彈性璆 31製於引線帶2下方（可不設凸塊23)，並直接黏貼於晶片i 上（如第5圖中所示）。 再請參考第6圖與第7圖，將引線帶2上之連接引線21打 線（bonding)至晶片1之焊塾11上可將晶片1上之焊塾接點 引接至引線帶2上’經引線帶2上之印刷電 '路佈局導引，即 可將晶片1上之焊塑* 11接點位置重新排列而於引線帶2上重 新引出接點位置》由於連接引線21係直接位於焊塾11上方40938C V. Sectional view of invention description (6) (TAB tape) 2. The dashed line on the wafer 1 in the figure is a cutting line. A solder pad 11 is formed on the upper surface of the wafer 1 for the leads to electrically connect the solder pads to external components. The lead strip 2 is provided above the upper surface of the wafer 1, and The composition and structure is a conventional technology, which is mainly a conductor (such as steel wire) combined with the polymer material body 22, and the structure is mainly a printed circuit layout in the polymer body 22 (not shown in the figure) and then led out and connected The bonding leads 21 are outside the polymer body 22. A bump 23 is provided under the lead strip 2 to provide better mechanical strength. Please refer to FIG. 3 and FIG. 4 again, which are schematic diagrams of bonding the lead tape 2 to the wafer 1. It is shown in FIG. 4 that the non-soldering part above the wafer 1 is firstly coated with a layer of underfill 3 as an attachment agent, and then the lead tape 2 is attached to the filler 3 and adhered to the wafer. 1 on. In addition to providing the adhesive effect, the filler 3 can also reduce the TCE mismatch when the temperature difference change rate is large due to the difference in thermal expansion coefficient between the chip 1 and the lead tape. The lead tape 2 is pasted to the wafer. The method of 1 is not limited to the foregoing method, and can also be achieved by other conventional or changed adhesive methods. For example, the attachment agent is made under the lead strip 2 and then bonded, that is, the elastic 璆 31 is first made on the lead strip 2 Underneath (bumps 23 may not be provided), and directly adhere to the chip i (as shown in Fig. 5). Please refer to Fig. 6 and Fig. 7 to bond the connecting leads 21 on the lead strip 2 (bonding). The solder joints on wafer 1 can be connected to the solder joints 11 on wafer 1 to the lead strip 2 'through the printed circuit on the lead strip 2'. The contact positions are rearranged and the contact positions are re-extracted on the lead strip 2. As the connection lead 21 is directly above the welding pad 11

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409380 、發明說明（7) 且間距小於焊墊1丨附著劑厚度加上導線帶厚，度，是以可直 接在原處進行打線，相較於將引線打線至導線架（丨ead 之引線封裝（wire bonding)方式，焊墊11接點處之 丨4長度較短，可得到較佳之電性特性及較佳之高頻傳輸 第了圖中所示為引線帶2上印刷電路佈局之—實施例，斧 ，印刷電路佈局之導引’可將個別之未切割晶片上單行^ 焊塾U重新排列為間距較大之雙行排列焊墊24，然亦可以 其他佈線方式形成其他排列形態（如多行陣列）之焊塾。有 關如何將兩晶片與引線帶2之電路佈局之電性連接以構成 一 128MDRAM之技術已於美國專利第5, 332, 922號「多晶片 半導體封裝裝置」與美國專利第5, 804,874號「具有2數 ，LOC型態半導體晶片之堆疊式晶片封裝裝置」兩專利案 詳細說明’於此將兩專利案併入本案參考，而不贅述/ 再請參考第8圖，為使連接引線21及晶片上焊墊u之部< 位與外界絕緣’必須將打線完成之晶片1封膠，由於晶片1 上表面非焊墊Π之部位已黏貼引線帶形成保護，是以封膠 只需在打線完成之連接引線2 I處進行。將聚合物封膠村料 4施配（dispensing)密封於連接引線21處，即可保/護晶 片1與引線帶2之導體接點處使其與外界絕緣。封膠材料4 可選擇習用隔絕水氣滲透之高密度材質，如石夕膠 (silicons)、環氧樹脂（ep0Xies)、聚醯胺類 (polyamide)、聚苯二曱基類（p〇iyXylylene)或矽聚醯胺 類（s i 1 i c ο η - ρ ο 1 y a m i d e )。409380, the description of the invention (7), and the pitch is smaller than the thickness of the bonding pad 1 丨 the thickness of the adhesive and the thickness of the lead wire, so that the wire can be directly wired in situ, compared with the lead wire to the lead frame (丨 ead's lead package ( wire bonding) method, the length of the 4 at the contact of the pad 11 is shorter, can obtain better electrical characteristics and better high frequency transmission. The figure shows the printed circuit layout on the lead strip 2-Example, Axe, guide to printed circuit layout 'can re-arrange a single row on individual uncut wafers ^ The solder joints U are re-arranged into a two-row arrangement of pads 24 with a larger pitch, but other arrangements can also be used to form other arrangements (such as multiple rows Array). The technology of how to electrically connect the two chips to the circuit layout of the lead strip 2 to form a 128MDRAM has been described in US Patent No. 5,332,922 "Multi-chip Semiconductor Packaging Device" and US Patent No. No. 5, 804,874 "stacked chip packaging device with two-digit, LOC type semiconductor wafer" detailed description of the two patents' herein the two patents are incorporated into this case reference, without repeating / please refer to Figure 8 for, Make The connection lead 21 and the portion of the pad u on the wafer < the bit is insulated from the outside 'must be sealed to the completed wafer 1 because the non-pad Π on the upper surface of the wafer 1 has been attached to the lead strip to form a protection. It only needs to be performed at the connection lead 2 I after the bonding is completed. Dispensing the polymer sealant 4 at the connection lead 21 can protect / protect the conductor contact points of the chip 1 and the lead strip 2 It is insulated from the outside world. The sealing material 4 can be selected from high-density materials that are commonly used to block water vapor, such as silicons, ep0Xies, polyamides, and polyphenylene diphenyls. (P〇iyXylylene) or silamines (si 1 ic ο η-ρ ο 1 yamide).

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再請參考第9圖與第10圖’配勝密封完成之晶片封裝須 以錫球（solder ball)5作為引接至外部之接點，以形成球" 格陣列結構。錫球5係設於第7圖中引線帶焊墊24上β本發 明中先將焊墊24上塗佈助焊劑（s〇Uer flux)後，利用真 空吸著固體錫球5至焊墊24上方之定位，再將錫球5置於焊 墊24上。置放於焊墊24上之錫球5須經回焊（reflow)處 理’以使錫球5與焊塾24充分鍵結。錫球5材料可選擇錫# 合金’亦可選用其他習用之錫、錯、金、銀、銦或其部分 組成所形成之合金。為配合不耐高溫處理之引線帶2聚合 物本體22，本發明中採用較佳之混合比為63/3?之錫鉛合 金為錫球材料，以得到較低之熔點（183。c)而可在較低之 溫度（熔點附近）進行回焊。將錫球5定位於焊墊24上之方 式亦可採用其他習用之方式，如喷射（jet)熔融之焊料微、 液滴或塗佈錫膏等。設置錫球5完成之晶片封裝，即形成 一球格陣列（BGA)積體電路封裝，而可直接與外部電路連Please refer to FIG. 9 and FIG. 10 again. The chip package completed with matching sealing must use solder ball 5 as a contact point to the outside to form a ball " lattice array structure. The solder ball 5 is provided on the lead strip solder pad 24 in FIG. 7. In the present invention, the solder pad 24 is coated with a solder flux (solder flux), and then the solid solder ball 5 is sucked to the solder pad 24 by vacuum. Position the upper part, and then place the solder ball 5 on the solder pad 24. The solder ball 5 placed on the solder pad 24 must be subjected to reflow treatment 'so that the solder ball 5 and the solder pad 24 are sufficiently bonded. The material of the solder ball 5 can be selected from the alloy of tin #, or other conventional alloys formed of tin, copper, gold, silver, indium, or a part thereof. In order to cooperate with the polymer body 22 of the lead tape 2 which is not resistant to high temperature treatment, a tin-lead alloy with a preferable mixing ratio of 63/3? Is used as the tin ball material in order to obtain a lower melting point (183.c). Reflow at lower temperatures (near the melting point). The method for positioning the solder ball 5 on the solder pad 24 can also adopt other conventional methods, such as jetting molten solder micro, liquid droplets, or applying solder paste. The chip package completed with the solder ball 5 is formed into a ball grid array (BGA) integrated circuit package, which can be directly connected to external circuits.

由上說明，本發明之具有複數未切割晶片之積體電路封 裝體及其製造方法，將複數未切割之低容量動態隨機存 記憶體晶片封裝為一顆高容量動態隨機存取記憶體之封 ，二，封裝複數低成本之低容量記憶體之方式，取代相同 高容量但成本高之記憶體以降低生產成本。本發明針對較 小面積之晶片封裝時，不須使用延伸環以避免晶片收縮， 以提升較小面積之晶片封裝之穩定性。再者，本發明封 體之引線較習用引線封裝方式之引線短，以避免引線過長From the above description, the integrated circuit package with a plurality of uncut wafers and a manufacturing method thereof according to the present invention encapsulate a plurality of uncut low-capacity dynamic random access memory chips into a high-capacity dynamic random access memory package. Second, the method of packaging multiple low-cost low-capacity memories replaces the same high-capacity but high-cost memories to reduce production costs. When the present invention is directed to a small-area chip package, it is not necessary to use an extension ring to avoid chip shrinkage, so as to improve the stability of a small-area chip package. Furthermore, the leads of the package of the present invention are shorter than those of the conventional lead packaging method, so as to avoid the leads being too long.

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409380 五、發明說明（9) 而會在高頻操作下引起雜訊之狀況，而可增加系統外頻之 高頻要求。 雖然本發明已以前述之較佳實施例揭示，然其並非用以 限定本發明，任何熟悉此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與修改，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。409380 V. Description of the invention (9) It will cause noise under high-frequency operation, which can increase the high-frequency requirements of the system's external frequency. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

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Claims (1)

409380409380 '，具有未切割晶片之積體電路封裝體之製造方法， 係包含下列步驟： ，，一包含至少兩顆未切割之積體電路晶片，該積體 電路晶片之上表面設有複數晶片焊墊； 將具有複數條連接引線（bonding 1 ead)之引線帶 ja^e)貝占5又於該晶片± I面，使複數條連接引線位於 該焊墊上方； 將該引線帶上之連接引線打線至該晶片焊墊上，使晶 片焊墊與該引線帶上之連接引線構成電性連接； 施配一封膠物質於該焊墊與該連接引線連接處予以密 封；及 將複數錫球形成於該引線帶上。 2、 依申請專利範圍第丨項所述之方法，其中該引線帶中 含一印刷電路佈局。 < 3、 依申請專利範圍第丨項所述之方法，其中該將複數錫 球形成於該引線帶上之步驟另包含下列子步驟： 鍍上助焊劑於引線帶中預定製作錫球之部位； 將錫球設於該助焊劑上；及 對該錫球進行回焊（ren〇w)。 4、 依申请專利範圍第3項所述之方法，其中將錫球設於 該助焊劑上之步驟為利用一真空吸引裝置吸引該錫球 ，再將該錫球釋放至該預定製作錫球之部位。 5、 依申請專利範圍第1項所述之方法，其中該引線帶上 設有彈性膠’而該引線帶藉該彈性膠貼設於該晶片上 ΗΙΊΗΓ C:\Program Files\Patent\PK6684‘ptd 第 13 頁 ___409380 六、申請專利範圍 表面。 6、 依申請專利範圍第1項所述之方法，其中該引線帶上 設有凸塊’將引線帶貼設於該晶片上表面之步驟另包 含下列子步驟： 於該晶片上表面塗佈填充膠；及 將該引線帶藉凸塊與填充膠貼設於該晶片上表面。 7、 依申請專利範圍第1項所述之方法，其中該至少兩顆 未切割之積體電路晶片係為動態隨機存取記憶體晶片 〇 8、 一種具有未切割晶片之積體電路封裝體，係包含： —包含至少兩顆未切割之積體電路晶片，該積體電路 晶片之上表面設有複數晶片焊墊； 一具有複數條連接引線（bond i ng 1 ead)之引線帶 < (tape)貼設於該晶片上表面，使複數條連接引線位於 該焊墊上方，該引線帶上之連接引線打線至該晶片焊 塾上’使晶片焊墊與該引線帶上之連接引線構成電性 連接； 一封膠物質於該焊墊與該連接引線連接處予以密封； 及 複數錫球形成於該引線帶上。 9、 依申請專利範圍第8項所述之具有未切割晶片之積體 電路封裝體，其中該未切割晶片為兩顆未切割之動態 隨機:存取記憶體晶片。 1 〇、依申請專利範圍第8項所述之具有未切割晶片之積體', A method for manufacturing an integrated circuit package with an uncut wafer, includes the following steps: ,, an integrated circuit wafer including at least two uncut wafers, and a plurality of wafer bonding pads are provided on the upper surface of the integrated circuit wafer ; The lead strip with a plurality of connection leads (bonding 1 ead) ja ^ e) is 5 on the ± I side of the wafer, so that the plurality of connection leads are located above the bonding pad; the connection leads on the lead strip are wired To the wafer bonding pad, so that the wafer bonding pad and the connection lead on the lead strip form an electrical connection; dispense a glue substance at the connection between the bonding pad and the connection lead to seal; and forming a plurality of solder balls on the Lead on. 2. The method according to item 丨 of the scope of patent application, wherein the lead strip includes a printed circuit layout. < 3. The method according to item 丨 of the scope of the patent application, wherein the step of forming a plurality of solder balls on the lead strip further includes the following sub-steps: Plating a flux on a portion of the lead strip where the solder balls are to be prepared ; Placing a solder ball on the flux; and re-welding the solder ball (ren0w). 4. The method according to item 3 of the scope of patent application, wherein the step of setting the solder ball on the flux is to attract the solder ball with a vacuum suction device, and then release the solder ball to the solder ball that is scheduled to be produced. Parts. 5. The method according to item 1 of the scope of the patent application, wherein the lead tape is provided with an elastic glue, and the lead tape is attached to the chip by the elastic glue ΗΙΊΗΓ C: \ Program Files \ Patent \ PK6684'ptd ___409380 on page 13 6. The scope of patent application. 6. The method according to item 1 of the scope of the patent application, wherein the lead strip is provided with bumps, and the step of attaching the lead strip to the upper surface of the wafer further includes the following sub-steps: coating and filling the upper surface of the wafer Glue; and attaching the lead tape to the upper surface of the wafer by bumps and filling glue. 7. The method according to item 1 of the scope of patent application, wherein the at least two uncut integrated circuit chips are dynamic random access memory chips. 0. An integrated circuit package with uncut chips. It contains:-Contains at least two uncut integrated circuit wafers, the upper surface of the integrated circuit wafer is provided with a plurality of wafer pads; a lead strip with a plurality of connection leads (bond ng 1 ead) < ( tape) is attached to the upper surface of the wafer, so that a plurality of connection leads are located above the bonding pad, and the connection leads on the lead strip are wired to the wafer pad; A piece of adhesive material is sealed at the connection place between the bonding pad and the connection lead; and a plurality of solder balls are formed on the lead strip. 9. The integrated circuit package with an uncut wafer according to item 8 of the scope of the patent application, wherein the uncut wafer is two uncut dynamic random: access memory chips. 10. The product with uncut wafers as described in item 8 of the scope of patent application C:\PrOgram Files\patent\pK6684 ptd 第 14 頁 -----409380 ______ 1 ，、、申請專利軸 電路封裝體，其另包含一彈性膠（elastomor)設於該 引線帶及該晶片上表面間’利該用彈性膠將該引線帶' 貼設於該晶片上表面。 11、依申請專利範.圍第8頊所述之具有未切割晶片之積體 電路封裝體，其中該引線帶設有複數凸塊。 1 2、依申請專利範圍第8項所述之具有未切割晶片之積體 電路封裝體，其中該引線帶中含—印刷電路佈局。 1 3、依申請專利範圍第8項所述之具有未切割晶片之積體 電路封裝體，其中該錫球與該引線帶接點間另包含有 助焊劑。 1 4、依申請專利範圍第8項所述之具有未切割晶片之積體 電路封襞體，其中該封膠材料係選自矽膠、攀氧樹脂 、聚酿胺類、聚苯二甲基類及；5夕聚醯胺類所組成之群、 組。. 臂 1 5、依申請專利範圍第8項所述之具有未切割晶片之積體 電路封裝體，其中該錫球為組成比例63/37之錫鉛合 金。C: \ PrOgram Files \ patent \ pK6684 ptd page 14 ---- 409380 ______ 1, patent application shaft circuit package, which also contains an elastic glue (elastomor) on the lead strip and the upper surface of the chip At the same time, the lead tape is attached to the upper surface of the chip with an elastic glue. 11. The integrated circuit package with an uncut wafer as described in the patent application No. 8), wherein the lead strip is provided with a plurality of bumps. 1 2. The integrated circuit package with an uncut wafer according to item 8 of the scope of the patent application, wherein the lead strip contains a printed circuit layout. 1 3. The integrated circuit package with an uncut wafer as described in item 8 of the scope of the patent application, wherein the solder ball and the lead strip contact further include a flux. 14. The integrated circuit enclosure with an uncut wafer as described in item 8 of the scope of the patent application, wherein the sealant material is selected from the group consisting of silicone, epoxy resin, polyamines, and polyxylylenes. And; groups and groups consisting of polyamines. Arm 15 5. The integrated circuit package with an uncut wafer as described in item 8 of the scope of the patent application, wherein the solder ball is a tin-lead alloy with a composition ratio of 63/37. C:\ProgramFiles\Patent\PK6684.ptd 第 15 頁C: \ ProgramFiles \ Patent \ PK6684.ptd page 15
TW088107665A 1999-05-12 1999-05-12 Integrated circuit package with uncut chip and its manufacture method TW409380B (en)

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