408502 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明说明（） 5-1發明領域： 本發明係有關於一種非揮發性記憶體，特别是一種具 高電容耦合率的高密度非揮發性記憶體。 5-2發明背景： 非揮發性記憶體（nonvolatile, memory)包含罩幕式 唯讀記憶體（Mask ROM)、可程式唯讀記憶體（PROM)、可 抹除且可程式唯讀記憶體（EPROM)、可電除且可程式唯 讀記憶體（EEPROM or E2PR〇M)、以及快閃記憶體（flash memory)等，可以在電源移除後仍保留住所儲存的資料， 在電子及計算機工業中應用非常廣泛。A. Bergemont等 人在其論文"Low Voltage NVG™: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications ApplicationM (in IEEE Trans. Electron Devices Vol. 43, p. 1510、1996)之 中陳述，近幾年來，由於市場的發展快速，可攜式電腦與 電信工業已成爲半導體積體電路設計技術的主要驅動 力，因此對於低功率、高密度且可重複讀寫的非揮發性記 憶體產生了大量的需求。這些可程式且可抹除的記憶體如 EPROM ' E2PROM 、與flash memory等可以儲存上述 系統中的作業系統以及應用軟體，是不可或缺的基本元件 之一0 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） ------------------1T------i (請先閣讀背面之注意填寫本頁) 經濟部中央標準局員工消资合作社印製 408502 A7 ________ B7 ___ 五、發明说明（） 可抹除且可程式的唯讀記憶體的基本儲存胞包含一 個具有雙重閘極的儲存電晶體，其令懸浮閘極（fl〇ating gate)由介電質所包圍’而與堆疊於其上的控制閘極 (control gate)電容耦合。可電除且可程式唯讀記憶體則 更包含一個存取電晶體’或稱選擇電晶體，作爲控制元 件。在這些可抹除且可程式的記憶體中，資料的存入（稱 爲程式化）與抹除是以懸浮閘極充放電的方式來達成。例 如，可抹除且可程式唯讀記憶體將選定的記憶胞的汲極熱 電子流注入懸浮閘極來進行資料的寫入，而以紫外光或X 光加速懸浮閘極中的電荷使之脱離來將寫入的資料抹 除。而可電除且可程式唯讀記憶體以及大部分的快閃記憶 體則可以採熱電子流注’或是採稱爲F1 o w e r - N o r d h e i ηι 穿隧的冷電子穿隧效應，來進行資料的寫入，而主要以 Flower-N〇rdheim穿隧將電子由懸浮閘極驅入源極來執 行資料抹除的動作。408502 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (5) Field of the invention: The present invention relates to a non-volatile memory, especially a high-density non-volatile with high capacitive coupling rate. Sexual memory. 5-2 Background of the Invention: Nonvolatile memory includes non-volatile memory (Mask ROM), programmable read-only memory (PROM), erasable and programmable read-only memory ( EPROM), programmable and read-only memory (EEPROM or E2PROM), and flash memory, etc., can retain the stored data after power is removed, in the electronics and computer industry The application is very extensive. A. Bergemont et al. In their thesis "Low Voltage NVG ™: A New High Performance 3 V / 5 V Flash Technology for Portable Computing and Telecommunications ApplicationM (in IEEE Trans. Electron Devices Vol. 43, p. 1510, 1996) According to the statement, in recent years, due to the rapid development of the market, the portable computer and telecommunications industry have become the main driving force of semiconductor integrated circuit design technology. Therefore, for low power, high density, and non-volatile memory that can be read and written repeatedly The body generates a lot of demand. These programmable and erasable memories, such as EPROM 'E2PROM, and flash memory, can store the operating system and application software in the above systems. They are one of the indispensable basic components. 0 This paper size applies to Chinese national standards (CNS ) Α4 size (210 X 297 mm) ------------------ 1T ------ i (please read the note on the back first and fill in this page) Ministry of Economy Printed by the Central Standards Bureau's Consumer Cooperatives 408502 A7 ________ B7 ___ 5. Description of the invention () The basic storage cell of the erasable and programmable read-only memory contains a storage transistor with a double gate, which makes the floating gate The floating gate is surrounded by a dielectric, and is capacitively coupled to a control gate stacked thereon. The erasable and programmable read-only memory further includes an access transistor 'or a selection transistor as a control element. In these erasable and programmable memories, data storage (called programming) and erasure are achieved by charging and discharging the floating gate. For example, erasable and programmable read-only memory injects the hot electrons from the drain of selected memory cells into the floating gate for data writing, and accelerates the charge in the floating gate with ultraviolet or X-rays to make it Exit to erase the written data. The erasable, programmable read-only memory and most flash memory can use hot electron flow injection or cold electron tunneling effect called F1 ower-Norddhei η tunneling for data The data is erased by using a Flower-Nordheim tunneling to drive electrons from the floating gate to the source.
Flower-Nordheim穿隧效應，或稱冷電子穿隧效應， 是一種量子效應，容許具有較低能量的電子穿越位能障較 高的石夕與氧化梦界面。H. Shirai等人在其論文 "A 0.54μιη2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memories" (in IEDM Tech. Dig. Vol‘ 95, p. 653, 1995)中述及，由於採用 Flower-Nordheim 穿隧效應來進行記憶胞之程式化與資料抹 除，具有較低的電流消耗率，因此已成爲製造低功率之可 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） {請先閲讀背面之注意填寫本頁) 裝' 訂 4085G2 經濟部中先標準局員工消費合作社印製 _B7_ 五、發明説明（） 電除且可程式唯讀記.憶體《及快閃記憶體不可或缺的設 計體系。但是要以F1 〇 w e r - N 〇 r d h e i m穿隨來進行資料寫 入與抹除，需要在基板與懸浮閘極間的介電層提供可反轉 的強電場，因此必須施加高供應電壓於記憶胞的控制閘 極。而爲了要降低此控制閘極偏壓，則必須要提高記憶胞 結構的電容耦合率。 Y. S. Hisamune等人 Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories" ( IEDM Tech. Dig. Vol. 93, p. 19, 1993)中提出一個製造快閃記憶體的方法，採無接點 的記憶胞陣列並具有高電容耦合率。然而爲了要達到高電 容耦合率的目標，此一方法施行了四次的多晶矽沈積，製 程十分複雜。此外，如 C. J. Hegarty 等人在論文 "Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates" (Solid-State Electronics, Vol. 34, p. 1207, 1991)中所提及，要在低功 率非揮發性記憶體中重摻雜的基板上製造薄的穿隧氧化 層以南電子流注政率及電荷崩潰（charge-to-breakdown)，是極不容易的。因此，以簡單的製程來達 到高電容耦合率、高電子流注效率以及高電荷崩潰，已成 爲今曰製造高密度、低功率之非揮發性記憶體的重要課 题。 5 - 3發明目的及概述： (請先閲讀背面之注意填寫本買) .裝' 訂 線- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 五、發明説明（ 鑒於 易以簡單 電荷崩溃 糙表面穿 一非穿' 随 穿隧氧化 於半導體 浮閘極形 層形成於 之上。其 408502 A7 B7 沾I (發明背景中’傳統的非揮發性記憶體不容 的i1達到鬲電容耦合率、高電子流注效率及高 隧氣::L根據以上的目❺，本發明提供-具有粗 .„a义非揮發性記憶體《此記憶體結構包含 氧化層形成於半導 1 、十導姐基板<上；具有粗糙表面的/於非穿随氧化層的兩側，錐質摻雜區形成 穿隧氧化層的下方作爲源極與汲極；一懸 」非穿随氧化層與穿隧氧化層之上；—内介電 =洋閉極之上；以及-控制w極形成於内介電層 I程敘述如下。 請先閱讀背面之注意填寫本育) -装. 經濟部中央標準局負工消費合作社印製 首先7、t板上形成場氧化隔離層並定義主動區域。沈 s氧化矽與氮化矽堆疊層然後定義穿隧氧化區。以高溫氧 化法形成非穿隧氣仆爲，y + s人β 層在去1氮化矽層後，植入磷離子 雜質於基板中以形威雜皙换独π y, . !>战雜質掺雜區，作爲源極與汲極。以熱 退火製程修護基板的損害並驅入雜質離子。去徐氧化梦層 並形成一未捧雜的薄半球形珍晶粒層，然後採用 HN〇3/CH3C〇〇H/HF/DI 溶液或是溫度約 14〇到 170<>C 之間的熱鱗酸（则3)溶液作爲触刻劑”x濕式保刻法回 独半球型m層以及基'板中的雜w择雜區域。由於麟離 子雜質#雜n的關率較未摻雜的半球型W粒廢爲 高4於是蝕刻後的雜質摻雜區將具有更粗糙的表面形狀β 接著形成具有粗糙表面之穿隧氧化層於雜質摻雜區上。最 本紙張尺度適用t國國家標準（CNS ) Α4規格（210Χ 297公釐 訂Ί 408502 A7 B7 五、發明説明（ 高 ' 度 密 高 0 極 閘 制。 控成 與形 層焉 電於 介體 内憶 、 記 極性 閘發 浮揮 懸非 成的 形度 序速 依作 後運 明 説 單 簡 式 圖 4 t 5 下 以 輔 中 字 文 明 説 之 後 往 於 將 例 ： 施述 實闡 佳的 較細 的詳 明更 發做 本形 圖 列 基 於 層 矽 化 氣 與 層 矽 化 氧 成 述形 _ m 闡H/ 的發 細本 詳據 更根 做爲 形圖 圖一 列第 的 上 板 基 於 區 化 氧 隧 穿 義 • 1定 圖明 面發 刻本 圓據 晶根 體爲 導圖 半二 的第 上 板 的 上 板 基 於 層 化 氧 熱 後 一 成 形 明 發 本 ; 據 圖根 面爲 .-glif一 圓三 晶第 體 導 的 中 板 基 於 區 極 汲 與 極 源 成 形 明 發 .，本 圖據 面根 Ασ 爲 圓圖 晶四 體第 導 半 化 氧 墊 除 去 並 火 退 熱 溫 古问 施 實 明 發 ; 本 圖據 面根 ,*'爲 圓獨 晶五 體第 導 晶 矽 形 球 薄 的 ί 摻 未。 一圖 成面 形剖 •，明 ^ 圖發晶 面本體 剖據導 圓根半 晶爲的 體圖上 導六板 半第基 的 於 Μ 層 (請先聞讀背面之注意女 j裝— ί填寫本頁) 訂 線 經濟部中央標準局貝工消費合作社印製 層 晶 形 球 半 刻； 触圖 法面 刻剖 #,圓 濕晶 以體 明導 發半 本的 據區 根雜 爲摻 圓質 七雜 第板 基 及 層 化 氧 隧 穿 的 面 表 糙 粗 具 成 形 明 發·’ 本圆 據面 根剖 爲圓 圖晶 八體 第導 半 的 本紙張尺度適用中國國家標串（CNS ) Α4規格（210X297公釐） 經濟部中央標準局貝工消費合作杜印裝 408502 A7 ________B7五、發明説明（） 第九圖爲根據本發明形成一 N型多晶矽層並定義懸 浮閘極的半導體晶圓剖面圖^ ^ 第十圖爲根據本發明形一超薄之内介電層.於懸浮閘 極上的半導體晶圓剖面圖。 第十一圖爲根據本發明形成另—N型多晶石夕層並定 義控制閘極的半導體晶圓剖面圖。 5 - 5發明洋細説明： 本發明提供一個簡單的方法以製造具高電容耦合率 的高密度非揮發性記憶體。其中應用到許多在傳統技藝中 已廣爲熟知的技術如微影、蝕刻、以及化學氣相沈積法 (ChemicalVaporDeposition, CVD)等，在此即不再詳述 其内容。此外，本發明製造具有粗糙表面的穿隧氧化層以 提高電子注流效率與電荷崩潰。 參見第一圖中所顯示，基板2爲結晶面向<1〇0>的單 晶石夕。首先在此基板2上形成一氧化ί夕層4，此氧化$ 夕層 4可以採用低壓化學氣相沈積法.（Low Pressure Chemical Vapor Deposition, LPCVD)在攝氏溫度约 400-750 度之 下形成，也可以在攝氏溫度約8 0 0 -110 0度之下以熱氧化 法形成。此氧化矽層4除了可作爲墊氧化層（pad oxide) 之外，並且可以在後續的離子植入法中作爲犧牲氧化層 (sacrificial oxide)以防止通道效應的產生。 本紙浪尺度適用中國國家標準（CNS ) A4規格（公釐） (請先閱讀背面:填寫本頁) -裝· 訂 -線· 408503 A7B7 五、發明説明（ 經濟部中央標準局員工消費合作社印製 接著在塾氧化層4之上形诸 .. ^ , s &上和成—氮化矽層（S作爲氧化罩 幕’此氮化石夕層6同樣可以接机肺 rf . ^ 』以株用低壓化學氣相沈積法在攝 氏溫度约700-800度之下形成。缺诒 风然後，以光阻塗佈、曝光' 顯影等標準的微影製程技術在氛仆功麻 识·町杜鼠化矽層ό之上形成光阻 層以定義出絶緣區的圖形。以此氺 -h . 岡/以此光阻層爲軍幕實施等向性 钱刻法触刻氮化石夕層6以定蟲惫仆苗 乂疋我乳化罩幕，於去光阻後實施 熱氧化法，於絶緣區上形成屋庁的& 。n y成厚度约爲3000至8000埃的場 氧化層8 ’作爲元件隔離區。在場葡仆& * l 杜場氧化隔離區8形成後， 可選擇將原氮化矽層6去除，重斩形ώ — 重祈^成—鼠化矽層 基板2上。 ' .參閲第二圖，以另-微影製程在主動區域上定義 :氧化區與非穿隨氧化區。以非等向性麵刻法㈣氮化發 層10,暴露出非穿随氧化區上之塾氧化層4;此非等 触刻製程可採用cf4/〇2/ CF2/H2, CHF3或是NF3作 蝕刻電漿源。蝕刻後，於溫度約攝氏8〇〇至度之… 實施高溫蒸氣氧化法’在非穿随氧化區上形成一層厚：： 化層12。如第三圖中所顯示，此熱氧化層12的厚 300至2500〶，可以提高記憶胞的電⑼合率。.、、. 接下來參見第四圖，以熱磷酸溶液作 F瑪礙蚀刻液去降 餘下的氮化矽層10。然後實施離子植入 成ί將離子雜 免經由氧化矽層4植入基板2中，以形 維 ν叫雖質摻雜區14， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐 (請先閱讀背面之注 填寫本頁) .裝 .訂 -線 408502 A7 B7 五、發明説明（） 作爲電晶體的源極與没極。此離子植入的能量與劑量分别 約爲 0·5 至 1 5 03KeV 以及 5 X l〇i4 _5 x 10i6 at〇ms/cm2。在 此離子植入製程中，氧化矽層4可作爲缓衝以防止基板2 受到離子轟擊之損壞，並可防止摻質離子發生通道效應； 厚熱氧化層12則使摻質離子難以穿透，無法進入其正下 方之基板區。實施退火製程修補基板損壞，同時可將摻質 活化並驅入以形成最佳分佈，如第五圖中所顯示。此退火 製程以在溫度約攝氏700 ‘至800度之下實施.快速熱製程 (rapid thermal processing, RTP)爲適當。然後以缓衝氧 化石夕敍刻液（buffered oxide-etching solution, BOE solution)或是稀釋的氫氟酸（HF)溶液去除氧化矽層4。 參見第六圖，沈積一層未摻雜的薄半球型矽晶粒層 (hemispherical grained silicon HSG-Si)16 於基板 2 之 上’厚度約爲20至300埃。在一實施例中，此—未摻雜 的半球型矽晶粒層16以每分鐘約 20埃的逵度沈積形 成。The Flower-Nordheim tunneling effect, or cold-electron tunneling effect, is a quantum effect that allows electrons with lower energy to pass through the interface between the stone barrier and the oxidized dream with higher potential barriers. H. Shirai et al. Described in his thesis " A 0.54μιη2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memories " (in IEDM Tech. Dig. Vol '95, p. 56, 1995) And, due to the use of the Flower-Nordheim tunneling effect for stylization and data erasure of the memory cell, it has a lower current consumption rate, so it has become a low-power manufacturing standard. This paper is applicable to the Chinese National Standard (CNS) A4 specification. (210X297 mm) {Please read the note on the back to fill in this page first) Binding 'Order 4085G2 Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs _B7_ V. Description of the invention "Indispensable design system for flash memory. However, to write and erase data with F1 〇wer-N 〇rdheim, it is necessary to provide a strong reversible electric field in the dielectric layer between the substrate and the floating gate. Therefore, a high supply voltage must be applied to the memory cell. Control gate. In order to reduce this control gate bias, the capacitive coupling rate of the memory cell structure must be increased. YS Hisamune et al. Proposed a method for manufacturing flash memory in Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories " (IEDM Tech. Dig. Vol. 93, p. 19, 1993). Contactless memory cell array with high capacitive coupling rate. However, in order to achieve the goal of high capacitance coupling rate, this method performed four times of polycrystalline silicon deposition, and the process was very complicated. In addition, as mentioned in the paper by CJ Hegarty et al. "Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates" (Solid-State Electronics, Vol. 34, p. 1207, 1991), non-volatile It is extremely difficult to fabricate a thin tunneling oxide layer south of the heavily doped substrate in the sex memory with electron flow injection rate and charge-to-breakdown. Therefore, the simple process to achieve high capacitive coupling ratio, high electron flow efficiency and high charge collapse has become an important topic in today's manufacturing of high density, low power non-volatile memory. 5-3 Purpose and summary of the invention: (Please read the note on the back and fill in the purchase first). Binding 'Thread-This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 5. Description of the invention ( The rough surface is penetrated by a non-penetrating layer with a simple charge breakdown, and the semiconductor floating gate polar layer is formed on it with tunneling oxidation. Its 408502 A7 B7 dip I (in the background of the invention, the traditional non-volatile memory does not allow i1 to reach 鬲Capacitance coupling rate, high electron flow efficiency and high tunneling gas :: L According to the above purpose, the present invention provides-has a thick. "A meaning non-volatile memory" This memory structure contains an oxide layer formed in the semiconductor 1 10, on the substrate < on the two sides of the non-pass-through oxide layer with a rough surface, the cone-doped region under the tunneling oxide layer is formed as the source and the drain; Layer and tunneling oxide layer; -internal dielectric = above the closed pole; and-the process of controlling the formation of the w pole in the internal dielectric layer is described below. Please read the note on the back and fill in this education first) -Equipment. Economy Printed by the Central Standards Bureau of the Ministry of Work and Consumer Cooperatives A field oxide isolation layer is formed on the top and an active area is defined. A stacked layer of silicon oxide and silicon nitride is then defined as a tunneling oxide region. A non-tunneling gas is formed by a high temperature oxidation method. The y + s β layer is denitrified. After the silicon layer is implanted, a phosphorus ion impurity is implanted in the substrate to replace the π y,.! ≫ impurity impurity doped regions as the source and the drain. The substrate damage is repaired by a thermal annealing process and the substrate is damaged. Drive in impurity ions. Deoxidize the dream layer and form an undoped thin hemispherical rare-grain layer, then use HN〇3 / CH3COOH / HF / DI solution or temperature about 14 to 170 < > The solution of hot scaly acid (three) between C is used as the engraving agent "x wet-type engraving method to resemble the hemispherical m-layer and the hetero-selective region in the substrate. Due to the lin ion impurity # 杂 n 的The off rate is higher than that of the undoped hemispherical W particles. 4 The impurity-doped region after etching will have a rougher surface shape β, and a tunnel oxide layer with a rough surface will be formed on the impurity-doped region. Paper size is applicable to National Standards (CNS) A4 specifications (210 × 297 mm customized) 408502 A7 B7 V. Description of the invention (high 'degree The dense high 0-pole gate system. Controlled and shaped layers of electricity are memorized in the mediator, and the shape sequence speed of the floating gates is recorded according to the postscript. After the Chinese civilization, the following examples will be used: Detailed and detailed descriptions of the actual state of the description will be more detailed. This figure is based on the layer of silicified gas and layer of silicified oxygen. _ M The detailed description of the detailed explanation of H / will be based on The top plate in the first row of the graph is based on the zoned oxygen tunneling. • The first surface of the figure is carved and the circle is based on the crystal root. The upper plate of the second plate is based on the layered oxygen heat. According to the figure, the root surface of the figure is .-glif, a circular three-crystal body guide, and the middle plate is based on the area pole drawing and polar source forming. According to the figure, the root Aσ is the circular four-body crystal semi-conductive oxygen pad removal. Wenhu Wen Shi Shiming made the heat retreat; according to the root of the picture, * 'is a thin monolithic pentad with a five-body crystal. A picture is a cross-section of the figure, Ming ^ The figure shows the body of the crystal plane, which is based on the guide of the semicircular root crystal. The six-segment semi-basic base is on the M layer (please read the attention on the back first. Women's clothing — ί (Fill in this page) Half-engraved printed crystal spheres are printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives; The surface of the base of the seven miscellaneous plate and the layered oxygen tunnel is rough and shaped with a clear hair. 'This circle is cut to the root of the octahedron, and the paper size is applicable to the Chinese National Standard String (CNS) Α4 Specifications (210X297mm) The Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperation, Du printed 408502 A7 ________ B7 V. Description of the invention () The ninth figure is a cross section of a semiconductor wafer that forms an N-type polycrystalline silicon layer and defines a floating gate in accordance with the present invention. Figure ^^ Figure 10 is a cross-sectional view of a semiconductor wafer with an ultra-thin inner dielectric layer on a floating gate according to the present invention. FIG. 11 is a cross-sectional view of a semiconductor wafer in which another N-type polycrystalline silicon layer is formed and a control gate is defined according to the present invention. Detailed description of inventions 5-5: The present invention provides a simple method for manufacturing high-density non-volatile memory with high capacitive coupling ratio. Among them, many techniques that are well-known in traditional techniques such as lithography, etching, and Chemical Vapor Deposition (CVD) are used, and the details are not described here. In addition, the present invention manufactures a tunneling oxide layer with a rough surface to improve the electron injection efficiency and charge collapse. As shown in the first figure, the substrate 2 is a single crystal with a crystal face of < 100 >. First, an oxide layer 4 is formed on the substrate 2. The oxide layer 4 can be formed by a low pressure chemical vapor deposition (LPCVD) method at a temperature of about 400-750 degrees Celsius. It can also be formed by a thermal oxidation method at a temperature of about 8 0-110 0 degrees Celsius. The silicon oxide layer 4 can be used as a pad oxide, and can be used as a sacrificial oxide in a subsequent ion implantation method to prevent the generation of a channel effect. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (mm) (Please read the back: fill in this page first)-Binding · Binding-Thread · 408503 A7B7 V. Description of the invention (Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Then on top of the plutonium oxide layer 4: ^, s & on and into a silicon nitride layer (S as an oxide mask 'this nitride layer 6 can also be connected to the lung rf. ^ ” The low pressure chemical vapor deposition method is formed at a temperature of about 700-800 degrees Celsius. Then, in the absence of wind, standard photolithographic process techniques such as photoresist coating and exposure and development are used in the laboratory. A photoresist layer is formed on the silicon layer to define the pattern of the insulating area. Using this 氺 -h. Gang / Isotropic money engraving method using the photoresist layer as a military curtain to touch the nitride layer 6 to fix the insect I ’m tired of emulsifying the curtain, and then performing thermal oxidation after removing the photoresist, forming a roof & on the insulation area. A field oxide layer with a thickness of about 3000 to 8000 angstroms is used as the element isolation area. After the formation of the field oxidation isolation region 8, the original silicon nitride layer 6 can be removed and re-chopped. Shape-free — heavy prayer ^ -moulded on silicon substrate 2. 'Refer to the second figure to define the active area with another-lithography process: oxidized area and non-penetrating oxidized area. Non-isotropic The surface-etched hafnium nitride layer 10 exposes the hafnium oxide layer 4 on the non-pass-through oxide region; this non-isotropic etching process can use cf4 / 〇2 / CF2 / H2, CHF3 or NF3 as an etching plasma source After etching, at a temperature of about 800 degrees Celsius to… implement a high-temperature vapor oxidation method to form a thick layer on the non-pass-through oxidation zone :: Chemical layer 12. As shown in the third figure, this thermal oxide layer 12 The thickness is 300 to 2500 〶, which can improve the electrical coupling rate of the memory cells........ Next, referring to the fourth figure, use a hot phosphoric acid solution as the F etch etching solution to lower the remaining silicon nitride layer 10. Then implement Ion implantation: I implant ion ions into the substrate 2 through the silicon oxide layer 4. The shape dimension ν is called the mass-doped region 14. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm (please First read the note on the back and fill in this page). Binding. Binding-Line 408502 A7 B7 V. Description of the invention () As the source and impulse of the transistor. This The energy and dose of ion implantation are about 0.5 to 15.0KeV and 5 X l0i4 _5 x 10i6 at 0ms / cm2. In this ion implantation process, the silicon oxide layer 4 can be used as a buffer to prevent Substrate 2 is damaged by ion bombardment and can prevent the channel effect of dopant ions; Thick thermal oxide layer 12 makes it difficult for dopant ions to penetrate and cannot enter the substrate area directly below it. An annealing process is used to repair the substrate damage and at the same time The dopants are activated and driven in to form an optimal distribution, as shown in the fifth figure. This annealing process is performed at a temperature of about 700 ′ to 800 degrees Celsius. A rapid thermal processing (RTP) is appropriate. The buffered oxide-etching solution (BOE solution) or diluted hydrofluoric acid (HF) solution is then used to remove the silicon oxide layer 4. Referring to FIG. 6, an undoped thin hemispherical grained silicon HSG-Si 16 is deposited on the substrate 2 ′ to a thickness of about 20 to 300 angstroms. In one embodiment, the undoped hemispherical silicon grain layer 16 is formed at a degree of about 20 angstroms per minute.
接著如第七圖中所顯示，實施一濕式蝕刻法，以回蝕 半球型梦晶粒層（HSG-Si)16，以及基板2中的雜質掺雜區 域14。在一較佳實施例之中，此一濕式蝕刻法可以採用 HN〇3/CH3COOH/HF/DI 溶液作爲蝕刻劑。S.H. Woo 等 人在其論文"Selective Etching Technology of in-situ Doped Poly-Si (SEDOP) for High Density DRAM 本紙張尺度適用中國國家標準（CNS > A4规格（2S0X 297公釐） I----^J--裝—— 請先閲讀背面之注意14!^:填寫本頁 訂 經濟部中央標準局員工消费合作社印製 408502 經濟部中央標準局貝工消費合作社印製 A7 __B7_ 五、發明説明（） Capacitors" (Symposium on VLSI Tech., p.25, 1994)中 指出，以此一蝕刻劑對含重掺雜磷離子的矽基板與未摻雜 的半球型矽晶粒層進行蝕刻蝕時，將具有高達6 0至8 0 倍的蝕刻選擇比，所以對於基板2磷離子摻雜區域的 暴露部份，其蝕刻速率及蝕刻深度皆遠較未摻雜的半球型 矽晶粒層爲高，而可獲致較高的蝕刻效果。在另—較佳實 施例中，溫度約140到17〇 °C之間的熱磷酸（phosphoric a c i d, Η Ρ Ο3)溶液也可以在此一姓到製程中採用作爲蚀刻 液。根據Hirohito Watanabe等人在論文"a Novel Stacked Capacitor with Porous-Si Electrodes f〇r High Density DRAMs" (Symposium on VLSI Tech., p 17 19 9 3)中所提及’在半球塑砂晶粒層i 6触刻去除之後，鱗 離子摻雜區域14的表面上將會形成鱗梦結構（p 〇 r 〇 u s _ s f structure)以及微孔隙表面（micro cavity surface)，而將 具有較蝕刻前更粗糙的表面形狀。 接著參見第八圖’將一薄氧化層18形成於雜質摻雜 區域14之上。此薄氧化層18可以採用化學氣相沈積法予 以沈積’或是在乾氧環境中，以溫度約爲攝氏75〇至115〇 度的熱氧化法氧化形成’也可以採用—氮化製程以及—再 氧化製程形成氮氧化矽層】8。此時由於底層的雜質摻雜 區域14具有粗糙的表面形狀，因此所形成的薄氧化層18 將具有粗糙的表面以及—粗糙的矽與二氧化矽界面。根據 吳t切霖博士等人在其論文"characteriz£iti〇ri 〇f Thin (請先閲讀背面之注意填寫本頁) 裝· -訂 線 本紙張尺歧财@目料 經濟部中央標準局員工消費合作社印製 408502 A 7 __B7_ 五、發明説明（）Then, as shown in the seventh figure, a wet etching method is performed to etch back the hemispherical dream grain layer (HSG-Si) 16 and the impurity-doped region 14 in the substrate 2. In a preferred embodiment, the wet etching method may use a HNO3 / CH3COOH / HF / DI solution as an etchant. SH Woo et al. In their thesis " Selective Etching Technology of in-situ Doped Poly-Si (SEDOP) for High Density DRAM This paper is applicable to the Chinese national standard (CNS > A4 specification (2S0X 297 mm) I --- -^ J--Installation—— Please read the note on the back 14! ^: Fill in this page and print it by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed 408502 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Bayer Consumer Cooperatives __B7_ () Capacitors " (Symposium on VLSI Tech., P.25, 1994) pointed out that when using this etchant to etch a silicon substrate containing heavily doped phosphorus ions and an undoped hemispherical silicon grain layer Will have an etching selection ratio of up to 60 to 80 times, so for the exposed portion of the substrate 2 phosphorus ion doped region, the etching rate and etching depth are much higher than the undoped hemispherical silicon grain layer And a higher etching effect can be obtained. In another preferred embodiment, a solution of phosphoric acid (phosphoric acid, ΗΡΟ3) at a temperature of about 140 to 17 ° C can also be used in this process. Adopted as an etching solution. According to Hirohito Watanabe et al. Mentioned in the paper " a Novel Stacked Capacitor with Porous-Si Electrodes f〇r High Density DRAMs " (Symposium on VLSI Tech., P 17 19 9 3) 'in the hemispherical plastic sand grain layer i 6 After the etching is removed, a squamous structure (p 〇r 〇us _sf structure) and a micro cavity surface will be formed on the surface of the scale ion-doped region 14 and will have a rougher surface than before etching. Shape. Then refer to the eighth figure, 'a thin oxide layer 18 is formed on the impurity-doped region 14. This thin oxide layer 18 can be deposited by chemical vapor deposition' or in a dry oxygen environment at a temperature of about It is oxidized and formed by thermal oxidation method with a temperature of 75 to 115 degrees Celsius. A silicon oxynitride layer can also be formed by a nitriding process and a re-oxidation process. 8. At this time, because the underlying impurity-doped region 14 has a rough surface shape Therefore, the thin oxide layer 18 formed will have a rough surface and a-rough silicon-silicon dioxide interface. According to Dr. Wu Tie Lin et al. In their thesis "characteriz £ iti〇ri 〇f Thin (Please first Complete this page to read the back of the note) installed · - set the paper size line this fiscal discrimination @ mesh material Ministry of Economic Affairs Bureau of Standards employees consumer cooperatives printed 408502 A 7 __B7_ V. invention is described in ()
Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon" (IEEE Trans. Electron Devices, Vo I. 43, p. 287, 1996)中發表 的研究，在晶界處由於氧份子的擴散速度較快，因此有較 快的氧化速率，於是產生的氧化矽層18將會形成一粗糙 (textured)的矽與氧化矽界面。此一粗糙界面會造成局部 的高電場，而使從基板2注入氧化層的電子流增大。因此 較之於傳統的穿隧氧化層，結構，以表面粗糙的薄氧化層 18作爲穿隧氧化層可以增加電子流注效能，降低電荷捕 獲率，並使電荷崩潰增大。 如第九圖中所顯示，沈積一導電層20於基板2之上， 此導電層20可以採用摻雜或同步摻雜的多晶矽爲材質， 以低壓化學氣相沈積法形成。接著以標準的微影製程在導 電層20之上定義出懸浮閘極的圖案，而採Cl2、 HBr > SF6或是SiCl4爲蝕刻電漿源，非等向性地蝕刻多晶矽層 以形成懸浮閘極20於主動區域及部份的場氧化隔離區 上。 在第十圖中顯示出一超薄的内多晶矽介電層22沈積 於懸浮閘極20的表面上。此内多晶矽介電層22可採用五 氡化二麵（T a 2 〇 5)、銷想鈇酸鹽（b a r i u m s t r ο n t i u m titanate, BST)、由氮化矽與氧化矽組成的複合薄膜 (ON)、或是由氧化矽、氮化矽與氧化矽組成的三重薄膜 本紙張尺度適用中國國家榡準（CNS M4規格（210X 297公釐） (請先閲讀背面之注意填寫本頁) •裝· 408502 A7 ---------B7 五、發明説明（） (〇二)爲材質。，最後，參見第十一圖中所示，沈積並蝕刻 電層以形成控制閘極，此控制閘極同樣可以採用摻 雜或同步掺雜的多晶發爲材質，以低壓化學氣相沈積法形 成。 .根據以上所提的方珐，本發明完成一具有粗糙表面穿 隧氧化層之㈣發性記體。如第十时所顯示，此記憶 體結構包含—非穿随氧化得12形.成料導體基板2 上’穿隧氧化層18形成於非穿隧氧化層12的兩側，雜質 摻雜區14形成於半導體基板2中穿隧氧化層的下方，作 爲源極與汲極；一懸浮閘極20形成於非穿隧氧化層12 與穿隧氡化層18之上；一内介電層22 $成於懸浮閘極 2〇义上；以及—控制閘極24形成於内介電層22之上。 上述之穿隧氧化層18具有粗糙的上下表面，可產生高區 j電場，增加電子流注效能，降低電荷捕獲率並使電荷崩 说增大。採用此具有粗糙表面的穿隧氧化層18，可以在 比傳統穿随結構面積較小的條件下達到相同的穿隧電 泥，因此可以製造高密度、高運作选度的非揮發性記愫 體。 _ 〜 經濟部中央標準局員工消費合作社印製 定精專 限之請 以示申 用揭之 非所述 並明下 發在 本含 Μ離包 例脱應 施未均 實它， 佳其饰 幸凡 Υ 之.，或 明圍變 發範改 本中效 爲專等 僅請之 述申成 所之完 上明所 以發下 本神 已The study published in Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon " (IEEE Trans. Electron Devices, Vo I. 43, p. 287, 1996), due to the rapid diffusion of oxygen molecules at grain boundaries, Therefore, there is a faster oxidation rate, and the resulting silicon oxide layer 18 will form a textured silicon-silicon oxide interface. Such a rough interface causes a local high electric field, which increases the electron flow injected from the substrate 2 into the oxide layer. Therefore, compared with the traditional tunneling oxide layer, the structure, using a thin oxide layer 18 with a rough surface as the tunneling oxide layer can increase the efficiency of electron injection, reduce the charge capture rate, and increase the charge collapse. As shown in the ninth figure, a conductive layer 20 is deposited on the substrate 2, and the conductive layer 20 may be made of doped or synchronously doped polycrystalline silicon and formed by a low-pressure chemical vapor deposition method. Next, a standard lithography process is used to define the floating gate pattern on the conductive layer 20, and Cl2, HBr > SF6 or SiCl4 is used as the etching plasma source, and the polycrystalline silicon layer is anisotropically etched to form the floating gate. The pole 20 is on the active region and part of the field oxidation isolation region. In the tenth figure, an ultra-thin inner polycrystalline silicon dielectric layer 22 is deposited on the surface of the floating gate 20. Here, the polycrystalline silicon dielectric layer 22 may use a pentamed two-sided (T a 2 05), a barium strontium titanate (BST), and a composite film (ON) composed of silicon nitride and silicon oxide. , Or a triple film consisting of silicon oxide, silicon nitride and silicon oxide. This paper is sized for China National Standards (CNS M4 (210X 297 mm)) (Please read the note on the back to fill out this page first). • 408502 A7 --------- B7 V. Description of the invention () (〇 二) is the material. Finally, referring to the eleventh figure, the electric layer is deposited and etched to form a control gate. This control gate The poles can also be doped or synchronously doped polycrystalline hair as the material and formed by the low-pressure chemical vapor deposition method. According to the square enamel mentioned above, the present invention completes the bursting property of a rough surface tunneling oxide layer. As shown at the tenth time, this memory structure contains-non-penetrating and oxidizing to form 12. The tunneling oxide layers 18 on the conductor substrate 2 are formed on both sides of the non-tunneling oxide layer 12, and impurities are doped. The impurity region 14 is formed under the tunneling oxide layer in the semiconductor substrate 2 as a source A pole and a drain; a floating gate 20 is formed on the non-tunneling oxide layer 12 and a tunnelling layer 18; an internal dielectric layer 22 is formed on the floating gate 20; and—the control gate 24 is formed on the inner dielectric layer 22. The above-mentioned tunneling oxide layer 18 has rough upper and lower surfaces, which can generate a high region j electric field, increase the electron flow efficiency, reduce the charge trapping rate and increase the charge collapse. The tunneling oxide layer 18 having a rough surface can achieve the same tunneling mud under the condition that the area of the conventional tunneling structure is smaller than that of the conventional tunneling structure. Therefore, a non-volatile recording body with high density and high operational selectivity can be manufactured. _ ~ The Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs has set out the precise limit. Please indicate the application of the disclosure, and issue it explicitly in this example. The application should not be applied uniformly. Fan Zhizhi, or Mingwei changed the Fanfan version of the effect to be special, etc. Only the statement of Shen Chengsuo's completion was issued, so the god has sent
内 園 範 fMH 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Inner Garden Fan fMH This paper size applies to China National Standard (CNS) A4 (210X297 mm)