TW404072B - The manufacture method of high-density non-volatile memory with high capacitor coupling ratio having rough tunnel oxide on the surface - Google Patents

Abstract

This invention provides a method to manufacture the non-volatile memory having rough tunnel oxide on the surface. The process is as follows: Use the silicon nitride layer to define the tunnel oxide region on the substrate; the non-tunnel oxide region is formed with thermal oxidation method; after removing the silicon nitride layer, the doping region is formed as the source and the drain; a silicon layer is formed and is being feedback to form the rough surface shape on the doping region after etching; form the tunnel oxide region with rough surface. Finally, form the floating gate, the inner dielectrics and the control gate subsequently.

Description

4ϋ4ϋϊί 5. Description of the invention (5-1) Field of the invention: The present invention relates to a non-volatile memory, particularly a high-density non-volatile memory with a high capacitive coupling ratio. 5-2 Background of the Invention: The non-volatile memory (nonvolatile, memory) printed by the Consumer Cooperatives of the Central Bureau of Standards and Assistance of the Ministry of Economic Affairs includes mask-type read-only memory (Mask ROM) and programmable read-only memory (prom ), Erasable and programmable read-only memory (EPROM), erasable and programmable read-only memory (EEPROM or E2PROM >, and flash memory), etc., can be retained after power is removed Retained data is widely used in the electronics and computer industry. A. Bergemont et al. In his paper "Low Voltage NVGTM: A New High Performance 3 V / 5 V Flash Technology for Portable Computing and Telecommunications Application" ( in IEEE Trans. Eiectron Devices V〇l. 43, p. 1510 .. 1996) ii stated that in recent years, due to the rapid development of the market, the portable computer and telecommunications industry have become the main semiconductor semiconductor circuit design technology. Driving force, so a lot of demand for low power 'high density and rewritable non-volatile memory. These programmable and erasable memory such as EPROM E2PR〇M , And flash memory can store the operating system and application software in the above system, which is one of the indispensable basic components. This paper scales Guanjia County (CNS) Ya 4 threats (2 丨 Gx297 public meals) (Please (Read the notes on the back first and write this page)

Printed by the Central Government Bureau of the Ministry of Economic Affairs of the Central Bureau of Shellfish Consumer Cooperatives 404072 at ___ B7 V. Description of the Invention () The erasable and programmable read-only memory. The basic storage cell contains a storage transistor with a double gate. Among them, the floating closed electrode (floating ga⑷ is enveloped by the dielectric) and the control closed-circuit (contro1 gate) capacitor is stacked on it. It can be removed and the programmable read-only memory Zhao contains more- Take m, or select the crystal element as the control element. In some erasable and programmable memory, the data storage (called stylization) and erasing are based on the suspended closed-pole charge and discharge. Achieve. For example, 'erasable and programmable read-only memory injects the non-polar hot electron current of the selected memory cell into the suspension gate to write data, and accelerates the charge in the suspension gate with ultraviolet light or X-ray. It can be detached to erase the written data. The rewritable and programmable read-only memory and most of the flash memory can be hot electron stream injection, or called F10Wer N〇 Cold electron tunneling effect of rdheim tunneling for data writing , And Flower-Nordheim tunneling mainly electrons from the suspension into the gate driving source to perform data erase operation.

The Flower-Nordheim tunneling effect, or cold electron tunneling effect, is a quantum effect that allows electrons with lower energy to pass through the silicon-silica interface with higher potential barrier β H. Shirai et al. In his paper " A 0.54μιη2 Self-Aligned, HSG Floating Gate Cell (SAHF

Cell) for 256 Mbit Flash Memories " (in IEDM Tech. Dig.

Vol. 95 / p. 56, 1995) mentioned ‘because of the use of j? Lower-

Nordheim's tunneling effect for stylization and data erasing of memory cells has a low current consumption rate, so it has become a low-power-rate method. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm). ^) ^-(Please read the #Notes on the above page% to write this page) Order 404072 ^ -1 --- DuPont Packing A7 B7, Shellfish Consumption Cooperation, Central Bureau of Standards, Ministry of Economic Affairs V. Description of Invention () It is an indispensable system of programmable read-only memory and flash memory. However, in order to carry out data, write and erase with Flower-Nordheim, it is necessary to provide a strong reversible electric field in the dielectric layer between the substrate and the floating gate. Therefore, a high supply voltage must be applied to the control cell of the memory cell. pole. In order to reduce this control gate bias, it is necessary to increase the capacitance coupling rate of the memory cell structure. Y. S. Hisamune and others

Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories, IEDM Tech. Dig. Vol. 93, p. 19, 1993) proposes a method for manufacturing flash memory, which uses contactless memory The cell array also has a high capacitive coupling ratio. However, in order to achieve the goal of high capacitance coupling rate, this method performed four times of polycrystalline silicon deposition, and the process was very complicated. In addition, 'as mentioned by CJ Hegarty et al. In the paper Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates " (Solid-State Electronics, Vol. 34, p. 120 7, 1991), non-volatile at low power It is extremely difficult to manufacture a thin tunneling oxide layer on a heavily doped substrate in the memory to improve the electron injection efficiency and charge-to-breakdown. Therefore, the simple process to achieve high capacitive coupling rate, high electron flow efficiency and high charge collapse has become an important issue in today's manufacturing of high-density, low-power non-volatile memory. This paper scale applies Chinese national standards ( CNS > Α4 specification (210X297mm) ^ ------ 1T ------ ^ (Please read the precautions for back-up first, ΓΑ ·, this page) 404072

V. Description of the invention (5_3 Purpose and summary of the invention: :: Upper: In the background of the invention, the traditional non-volatile achieves high capacitance ..., high electron flow efficiency and high: non-volatile memory through the oxide layer. This The memory structure H tunnel II tunnel oxide layer is formed on the semiconductor substrate; a chemical layer with a rough surface is formed on both sides of the non-tunneling oxide layer, and an impurity-doped region is formed below the oxide layer in the semiconductor semiconductor substrate As the source and the drain;-the suspended closed electrode is formed on the non-pass-through oxide layer and the tunneling oxide layer; the internal dielectric layer is formed on the suspended gate; and a control gate is formed on the internal dielectric The process is described as follows. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, the field oxide isolation layer is first formed on the substrate and the active area is defined. The oxide stone and nitride stone stacks are deposited and then the through oxidation is defined. Area. A non-tunneling oxide layer is formed by a high temperature oxidation method. After removing the silicon nitride layer, a phosphorus ion impurity is implanted in the substrate to form an impurity-doped region as a source and a drain. The substrate is repaired by a thermal annealing process. Damage Drive in impurity ions. Remove the oxidized hard layer and form an undoped silicon layer. Then use Cl2, BC13, HBl <, SFe or SiCU as the etching plasma source, and dry-etch back the silicon layer and the substrate. Impurities doped in the region, and the surface shape of the crude sugar is formed on the impurity-doped regions after etching. Then a penetrating oxide layer with a rough surface is formed on the impurity-doped regions. Finally, a suspension gate, an internal Dielectric layer This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 404072 A7 B7 V. Description of the invention (and control gate. High density, * π & Α Λ ^ and A non-operating speed The volatile memory is described briefly in the 5-4 circle: The preferred embodiment of the present invention will be described in more detail in the following explanatory text: the column shape will be described in more detail : The first section is a cross-sectional view of a semiconductor wafer formed with a silicon oxide layer and a silicon nitride layer on a substrate according to the present invention; the second section is a cross-sectional view of a conductor wafer with a through oxide region defined according to the present invention; the third section is Is in accordance with the invention After the formation of the thermally quenched layer on the substrate semiconductor wafer cross section; the fourth figure is a sectional view of the semiconductor wafer with the source and drain regions formed on the substrate according to the present invention; the fifth is a high temperature thermal annealing and Sectional view of a semiconductor wafer with oxygen pad removed; ^ Please read the t-face first. Note f Figure 7T bound on this page is a cross-sectional view of a hair layer formed on the base wafer in accordance with the present invention. Printed on the substrate and layers of the Central Bureau of Standards and Technology Cooperative Consumers Co. The surface of the tunnel is rough and shaped with clear hair. According to the figure, the surface is cut into the 404072 A7 of the first half of the round octagonal crystal. A cross-sectional view of a semiconductor wafer defining a floating gate for forming an N-type polycrystalline silicon layer according to the present invention. The tenth figure is a cross-sectional view of a semiconductor wafer having an ultra-thin inner dielectric layer on a floating gate according to the present invention. The eleventh figure is a cross section 囫 of a semiconductor wafer in which another N-type polycrystalline silicon layer is formed and a control gate is defined according to the present invention. 5-5 Detailed description of the invention: The present invention provides a simple method for manufacturing high-density non-volatile memory with high capacitive coupling rate. Among them, it is applied to many technologies that are well known in traditional techniques such as lithography, etching, And chemical vapor deposition (Chemical Vapor Deposition, CVD), etc., which will not be described in detail here. In addition, the present invention manufactures a tunneling oxide layer with a rough surface to improve the electron injection efficiency and charge collapse. See that the substrate 1 is a single crystal silicon having a crystal orientation < 100 > First, a silicon oxide layer 4 is formed on the substrate 2. The silicon oxide layer 4 can be formed by a low-energy chemical vapor deposition method (10w Pressure Chemical

Vapor Deposition (LPCVD) is formed at a temperature of about 400-750 degrees Celsius, or it can be formed by a thermal oxidation method at a temperature of about 800-1100 degrees Celsius. The silicon oxide layer 4 can be used as a pad oxide layer, and can be used as a sacrificial oxide in a subsequent ion implantation method to prevent the generation of a channel effect. · This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297mm) ---------- 1 ------, order ^ ----- 0 (Please read first Note on the back, again on this page) A7 B7 _ 404072 printed by Shelley Consumer Cooperative, Central Bureau of the Ministry of Economic Affairs 5. Description of the invention () Then a silicon nitride layer 6 is formed on the oxide layer 4 as an oxidation cover The silicon nitride layer 6 can also be formed using a low pressure chemical vapor deposition method at a temperature of about 700-800 degrees Celsius. Then, a photoresist layer is formed on the silicon nitride layer 6 by standard photolithography process techniques such as photoresist coating, exposure, and shadow-like processes to define the pattern of the insulating region. Using the photoresist layer as a mask, the silicon nitride layer 6 is etched isotropically to define an oxide mask. After the photoresist is removed, a thermal oxidation method is performed to form a thickness of about 3000 to 8000 angstroms on the insulating region. The field oxide layer 8 serves as an element isolation region. After the field oxide isolation region 8 is formed, the original nitride nitride layer 6 can be optionally removed to form a nitride nitride layer on the substrate 2 again. Referring to the second figure ', another lithography process is used to define the steep and non-tunneled oxide regions on the active region. Anisotropic etching is used to etch the nitride nitride layer 10 to expose the pad oxide layer 4 on the non-tunneled oxide region. This anisotropic axis engraving process can use CF4 / 02, CF2 / H2 / CHF3 or NF3. As an etching plasma source. After the etching, a high-temperature vapor oxidation method is performed at a temperature of about 800 to 1100 ° C to form a thick thermal oxidation layer 12 on the non-tunneling oxidation zone. As shown in the third figure, the thickness of the thermally quenched layer 12 is 300 to 2500 Angstroms, which can improve the capacitive coupling ratio of the memory cells. "Next, refer to the fourth figure," remove the remaining silicon nitride layer 10 by using a hot galvanic acid solution as a wet etchant. Then, an ion implantation method is performed to implant ion impurities into the substrate 2 through the silicon oxide layer 4 to form Impurities are included in the high-standard paper standard (CNS) A4 size (210X297 mm) I ^ I ϋ —1ΤΙ I- ^ (Please read the notes on the back first: ·, write this page) Economy Printed by the Central Bureau of Standards, Shellfish Consumer Cooperatives, Ministry of Economics, Central Government Bureau of Standards, Shellfish Consumer Cooperatives, Seal 404072 A7 __ B7 V. Description of the invention () As the source and drain of the crystal crystal ceremony. The energy of this ion implantation and The doses are approximately 0.5 to 150 KeV and 5 x 10-5_1016 atoms / cm2, respectively. In this ion implantation process, the silicon oxide layer 4 can be used as a buffer to prevent the substrate 2 from being damaged by ion bombardment, and can prevent the channel effect of the dopant ions; the thick thermal oxide layer 12 makes it difficult for the dopant ions to penetrate , Can not enter the substrate area directly below it. An annealing process is performed to repair the substrate damage, while the dopants can be activated and driven in to form the optimal distribution, as shown in the fifth circle. In this annealing process, a rapid thermal processing (RTP) is performed at a temperature of about 700 to 800 degrees Celsius. The buffered silicon-etching solution (BOE solution) or diluted hydrofluoric acid (HF) solution is then used to remove the silicon oxide layer 4. Referring to the sixth figure, an undoped silicon layer 16 is deposited on the substrate 2 to a thickness of about 50 to 50 angstroms. This silicon layer 16 can be formed by using amorphous silicon, rugged poly silicon, or polysilicon, and deposited by a low-pressure chemical vapor deposition method. Among them, amorphous silicon, rough polycrystalline silicon, and polycrystalline silicon The formation temperature is about 400-56010, 560,590 * C and 590-800¾, respectively. Then, a dry etching method is performed to etch back the silicon layer 16. This dry etching method can use cl2, BC13, HBr, SF6, or SiCl4 as the etching plasma source. In this silicon etch-back process, the impurity-doped region of the substrate can be over-etched by about 20% to 100%. Because amorphous silicon has an irregular atomic arrangement 'and polycrystalline sand has an irregular grain arrangement', different rates of money engraving will occur across the silicon layer during the etching, and finally after etching, Paper Newcastle®® furniture ratio (CNS) A4 specification (210X297 mm) ----------- see -------- π ---------- ^ ( Please read the precautions on the back first, and then νντ on this page) A7 B7 404072 V. Description of the invention (substrate impurity-doped region M) You have a rough surface structure on the surface, just like the TF shown in the seventh circle. The eighth step is to "form" a thin oxide layer 18 on the impurity doped layer. This thin oxide layer 18 can be formed by chemical vapor deposition.

Nitrogen oxide layer 18 may be formed by deposition or by thermal oxidation in a dry oxygen environment at a temperature of about 750 to 1150 degrees Celsius. A nitriding process and a re-oxidation process may also be used. At this time, since the underlying impurity-doped region 14 has a rough surface shape ', the thin oxide layer µ formed will have a rough surface and a coarse sugar silicon and silicon dioxide interface. According to Dr. Wu Xielin and others in their thesis " characterizaH〇n 〇f Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon /, (IEEE

Tfans' Electron Devices, Vol. 43, p. 287, 1996) published a study 'Since the diffusion rate of oxygen molecules is faster at the grain boundaries, there is a faster oxidation rate', so the resulting silicon oxide layer 18 will A roughened silicon-silicon oxide interface is formed. Such a rough interface causes a local high electric field, which increases the electron flow injected from the substrate 2 into the oxide layer. Therefore, compared with the traditional tunneling oxide layer structure, using a thin oxide layer 18 with a rough surface as the tunneling halide layer can increase the electron injection efficiency, reduce the charge trapping rate 'and increase the charge collapse. As shown in the ninth figure, a conductive layer 20 is deposited on the substrate 2. This conductive layer 20 can be made of doped or synchronously doped polycrystalline silicon. 10 This paper size is applicable to China National Sample Standard (CNS) A4. (210X297 mm) 11-; ----- Without clothes ------, tT ------ ^ ___ Please read the «Notes on the back» / .. ¾ page) Ministry of Economic Affairs Printed by Huanggong Consumer Cooperative of the Central Government Bureau of Standards «. A7 B7 on 404072 5. Description of the invention () Formed by low pressure chemical vapor deposition. Then, a standard lithography process is used to define a suspension gate on the conductive layer 20, and using c 〖2, HBr 'SF6 or SiCU as the etching plasma source, the polycrystalline silicon layer is anisotropically etched to form In the tenth circle, the floating gate 20 shows an ultra-thin inner polycrystalline silicon dielectric layer 22 deposited on the surface of the floating gate 20 in the active region and a part of the field oxidation isolation region. Here, the polycrystalline silicon dielectric layer 22 may be made of pentoxide (Ta205), barium gill titanate (BST), composite film (ON) composed of silicon nitride and silicon oxide, or composed of The triple film (NO) composed of silicon oxide, silicon nitride, and silicon oxide is made of material. Finally, referring to the tenth figure, another conductive layer is deposited and etched to form a control gate. This control gate can also be doped or synchronously doped polycrystalline silicon as a material and formed by a low-pressure chemical vapor deposition method. According to the method mentioned above, the present invention completes a non-volatile memory with a rough surface penetrating the oxide layer. As shown in the tenth circle, the memory structure includes a non-tunneled oxide layer 12 formed on the semiconductor substrate 2, a tunneled oxide layer 18 is formed on both sides of the non-tunneled oxide layer 12, and an impurity-doped region 14 is formed under the tunneling oxide layer in the semiconductor substrate 2 as a source and a drain. A floating gate 20 is formed over the non-tunneling oxide layer 12 and the tunneling oxide layer 18;-the inner dielectric layer 22 is formed on the floating gate electrode 20 < and a control gate electrode 24 is formed on the inner dielectric layer 22. | ~ ^; ^ ------ 1T ^ ----- ^ (Please read the notes on the back ^ for this page) Printed by the Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs

A7 B7 404072 V. Description of the invention (The above-mentioned penetrating oxide layer 18 has the upper and lower surfaces of the crude sugar, which can generate a high-area electric field 'increasing the efficiency of electron flow injection', reducing the charge trapping rate and increasing the charge collapse. Using this rough surface Pass-through oxidation & M can achieve the same tunneling current under the condition that the area of the conventional tunneling structure is smaller than that of conventional tunneling structures, so it is possible to manufacture non-volatile memory with high density and high operating speed. The preferred embodiments of the present invention are not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below "(Please read the precautions on the back first. ¾ This page) 'Installation'-, *! Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives 12 This paper size applies to China National Standard (CNS) A4 (2IOX297 mm)

Claims (1)

Patent application scope 1—A method for forming a non-volatile memory structure on a semi-conductive substrate. The memory structure has a roughened tunneling oxide layer. The method includes at least: forming a silicon oxide layer on the semiconductor substrate. Forming a silicon nitride layer on the silicon oxide layer; etching the silicon nitride layer to define a tunneling oxide region on the semiconductor substrate, and exposing a portion of the oxide layer on the non-tunneling oxide region ^ Implementing the first thermal oxidation method to oxidize a portion of the semiconductor substrate exposed to the nitrided layer to form a non-tunneling oxide layer on the semiconductor substrate; removing the silicon nitride layer; implementing ions An implantation method is used to form an impurity-doped region in the semiconductor substrate, and the ion implantation method uses the non-tunneling oxide layer as a mask; an annealing process is performed to activate the implanted impurities and drive the impurity into the semiconductor substrate. Removing the silicon oxide layer; forming a silicon layer on the semiconductor substrate; performing a dry etching method to etch back the silicon layer and the impurity impurity region; forming a tunnel sugar oxide layer on the surface of the coarse sugar on the impurity Printed on the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Miscellaneous District; forming a first conductive layer on the tunneling oxide layer and the non-tunneling oxide layer as a suspension gate; forming a dielectric layer on the suspension gate Above the standard; this paper size uses China National Standard (CNS) A4 specification (210X297 mm) 404072 ----- Scope of patent application Form a * #-i # wfi. ΤΛ coin a conductive layer on top of the dielectric layer as a method of controlling the gate 2: The patent application method, where the upper is a P-type substrate. Dry guide Zhao substrate 3. For example, the degree of A of the patent application Fan Yuan i is about 40 to 300 angstroms. The method (the thickness range of the oxygen cutting layer ...), in which the first-time thermal oxygen is performed "under the temperature of 800 to 1100 degrees Celsius in an oxygen vapor environment # — (Please read the precautions on the back before / S Page 吣 • If the method of the scope of patent application (i), the thickness of the non-tunneling oxide layer is about 300 to 2500 angstroms. 6. If the method of the scope of patent application (申请), the above mentioned implanted impurities are N-type impurity. Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative. 7. The method of claim 6 in the patent scope, wherein the N-type impurities are selected from the group consisting of phosphorus ions, arsenic ions and antimony ions. 8. The method according to item 6 of the patent application group, wherein the above-mentioned N honey impurities are implanted at a dose of 5 × 10 × 4 × 5 × 1016 atoms / cm2 at an energy of 0.5 to 150 KeV. This paper uses the Chinese National Standard (CNS) A4 specification (210X297) wire 404072 g88 6. Application for patent scope 9 · As for the method of applying for the first item of patent scope, the above annealing process is about 800 to 1150 degrees Celsius 10. If applying for a patent The method of round item 1, wherein the thickness of the above-mentioned hemispherical stone layer is about 20 to 300 angstroms. 11. The method of item 1 of the patent application, wherein the material used for the above silicon layer is selected from A group consisting of amorphous stone (am〇rph〇us silicon), rough round polycrystalline stone (rugged polysilicone), and polycrystalline stone (polysilicone). 12 · As claimed in the scope of patent application The method of item 11, wherein the formation temperatures of the aforementioned amorphous stone, rough polycrystalline silicon, and polycrystalline silicon are about 400_560'C, 560-590¾, and 590-800TC, respectively. 13. The method of item 11 in the scope of patent application Among them, the etching plasma source used in the above-mentioned dry etching method is selected from the group consisting of Cl2, BCI3, HBr, SFe, and Sicl4. ^! (Please «read the precautions on the back first, then this page) Line · Ministry of Economy The description of the rough and rough surface printed by the Central Government Bureau of Work and Consumer Cooperatives was completed. The result is the Shen Xiang phase of the product law, the law, the encyclopedia, the fan, the specialization, and the oxygen application. Rough surface. The description of the table is above. i 1st round of the second round of the Eli layer of specialization M ^ Application Sui Ruchuan. The 5 papers used by the Chinese family Liang Feng (CNS) from the threat (2ωχ297 public envy) A8 B8 C8 D8 404072 VI. Application The scope of the patent covers the first item of the method in which the above-mentioned second thermal oxidation method is carried out at a temperature of about 750 ° C. Below 1050 ° C, printed by the Central Bureau of Standards of the Ministry of Dry Oxygen Environment and Economics®: Industrial and Consumer Cooperatives's 17 = Patent Fan Yuan No. 1 method, in which the above-mentioned surface rough tart "tunnel oxide layer is- -Reoxidation process formation. 18. The method of the first paragraph of the patent application, wherein the first conductive layer is a doped N-type polycrystalline silicon. 19. The method of the first scope of the patent application, wherein the first A conductive layer is synchronously doped N-type polycrystalline silicon. 20. The method according to item 1 of the patent application, wherein the above-mentioned dielectric layer is made of tantalum pentoxide (Ta205). 21. If the patent is applied for The method of the first item of Fan Guo, wherein the above-mentioned dielectric layer is made of barium strontium titanate (BST). 22. For the method of the first item of the patent scope, wherein the above-mentioned dielectric layer is made of gasification The composite film (ON) composed of silicon and silicon oxide is used as the material. 23. The method of the first item of the patent application park, wherein the above-mentioned dielectric layer is a triple film composed of silicon oxide, silicon nitride, and silicon oxide ( ΟΝΟ) 16 papers ΛΑϋ 财 (CNS) (21 () > < 297) Ⅰ-I --------- 1 ------ 11 ------ ^ (Please read the notes on the back first ^ '^ -This page) A8404072 § VI. The scope of the patent application is made of materials. The conductance of the 22nd paragraph of conductance is described above, middle, and top. Models around multi-round N Fan Fanli N Lizai, if you are special, please do not apply, please apply for the same step as if it is a layer M 4 5 2 2 --------- ^ ------ 1T ^ ----- 0 (Please read the notes on the reverse side first, please refer to this page) The paper size of the printed paper printed by the Central Standards Bureau of the Ministry of Economic Affairs, Gongheng Consumer Cooperative, printed in Chinese National Standard (CNS) 210 × 297 mm)