408500 A7 B7 五、發明説明（ 發明領城： 本發明與一種製造薄膜電晶體之方法有關，特別是 一種具有複合層源極/汲極結構之薄膜電晶體-液晶顯示 器（TFT-LCD)其製造方法。 發明背暑： 長久以來，液晶顯示器早已廣泛的應用於電子手 錶、計算機等數位化的電子產品上。並且隨著薄膜電晶體 -液晶顯示器其技術持續的發展與進步，由於其具有體積 小、重量輕、驅動電壓低、以及消耗功率低之優點，而被 大量的應用於筆記型電腦、個人數位化處理系統、以及彩 色電視上，並逐漸的取代傳統顯示器之影像管。然而隨著 薄膜電晶體-液晶顯示器其設計朝著大型化演進之趨勢， 在製造與發展上也遭遇諸多的問題。例如在製造大尺寸之 薄膜電晶體-液晶顯示器時，往往會產生嚴重的訊號延遲 問題。此外，受制於目前所使用之相關設備與材質，亦導 致所生產之電晶體-液晶顯示器其產品良率偏低，且產能 無法有效提高，因此並導致製造成本居高不下。 請 先 閱 讀 背 之 注 意- 事 i 經濟部中央標準局貝工消費合作社印製 —般而言，TFT-LCD包括了由薄膜電晶體（TFT)和像 素電極所形成的TFT透明底板與具有彩色濾光片之CF透明 頂板。其中在TFT透明頂板和CF透明底板間則充塡著液晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 408500 A7 B7 五、發明説明（） 分子。另外，在每個單位像素中，藉著控制作爲開關元件 之薄膜電晶體其聞極，可自資料匯流線（data bus lines) 傳輸一信號電壓至單位像素。當TFT接收到信號電壓後便 會開啓，如此則攜帶影像資訊之資料電壓便可經由TFT而 施加於相對應的像素電極及液晶上。値得注意的是當資料 電壓加到TFT，液晶分子之排列會產生改變，因而改變其 光學特性並顯示出影像。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注填寫本頁) 如同上述，在應用薄膜電晶體顯示器於大規模尺寸 之產品中，往往會導致極嚴重之信號延遲現像。爲了有效 改善此問題，可藉著降低薄膜電晶體其閘極與源極/汲結 構之電阻，以便提高信號傳輸之效率。由此，在材料的選 擇上，採用鋁金屬來作爲電晶體中之導電結構。然而，由 於鋁金屬與摻雜非晶矽間之歐姆接觸（o.hmic con tact)效 果並不好，是以往往需要再形成一緩衝層來作爲鋁層與摻 雜非晶矽層間之介面層，以便在製造薄膜電晶體-顯示器 時，有效的提高接觸之效果。此外在傳統技術中，爲了有 效的提高產能，往往使用可減少一道光罩之背面通道蝕刻 法（BCE, back channel etching)來取代傳統製程之軸刻 停止法（ES,_etching stopper)。並且，爲了縮減傳統TFT 製程步驟，且有效的降低元件發生短路的機會、並提高產 品良率，增加開口比率（open ratio)，往往採用形成銦錫 氧化物（I TO)層於整個TFT結構之上表面，以導通像素電極 與源極/汲極。然而由於IT0層與作爲源極/汲極材料之鋁 本紙張尺度適用中國國家標隼（CNS > A4規格（21〇 X 297公釐） 408500 A 7 _B7__.__ 五、發明説明（） 金屬其接觸效果不佳，是以往往需要形成一額外之接觸層 於I TO與鋁金屬之間，以便提高其接觸面之導通性。 由此，在傳統技術中，往往形成如第一圖所示之TFT 結構。其中，在一玻璃底材2上具有閘極4;且一絕緣層S 位於該玻璃底材2上，用以覆蓋該閘極4;一非晶矽層10位 於絕緣層8與閘極4之上方，且一 n +摻雜非晶矽層12形成於 非晶矽層1 〇之上表面；此外，作爲源極/汲極結構之複合層 14形成於該n +摻雜非晶矽層12之上，以作爲具有較佳歐姆 接觸與較低電阻値的源極/汲極結構《其中該複合層14包 括了作爲接觸層之鈦層14a與作爲緩衝層之鈦層14c，以及 位於鈦層14a與14c間的鋁層14b;另外，一具有導通孔之保 護層16隨後形成於該複合層14與絕緣層8之上表面，於其 上更再形成一透明導電層，並且藉由前述之導通孔連結源 極./汲極結構1 4。 經濟部中央標準局員工消費合作社印聚 (讀先閱讀背面之注會事項寫本頁) 然而因爲鈦層14c與n+摻雜非晶矽層12之蝕刻選擇 性偏低，是以在蝕刻該複合層1 4 (即鈦/鋁/鈦複合層結構） 以定義TFT之源極/汲極結構時，往往亦會對所曝露之n + 摻雜非晶砂層12造成損壞，從而導致產品良率的降低。此 外，亦有人採用具有鉬（Mo)層14a、鋁層14b、與鉬層14c 之複合層14(即鉬/鋁/鉬複合層結構）來作爲TFT元件之源 極/汲極結構。然而如同第一圖所示，在對保護層16進行 蝕刻時，往往採取過度蝕刻法（over-etching)，但對於源 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 408500 A7 B7 五、發明説明（） 極/汲極結構而言，當其上表面之保護層16被完全蝕刻 後，由於鉬層14a與保護層16之蝕刻選擇率很差，是以往 往在過度蝕刻的製程中，造成鉬層14a受到損壞。此外由 於在對複合層14進行蝕刻以定義源極/汲極之圖案時，是 使用溼蝕刻術來進行，因此往往無法精確有效的控制蝕刻 製程之效果。如第二圖所示，其中在對複合層14(鉬層14a/ 鋁層14b/鉬層14c)進行溼蝕刻程序時，由於蝕刻效果受到 材料性質的影晌而導致鋁層14b之.邊牆（Sidewall )蝕刻速 率高於鉬層14a、14c，如此一來，在後續形成保護層16 於絕緣層8與複合層14之上表面時，便會產生空洞30，從 而使後續製程發生缺陷之機會大增，且造成所製造TFT之 良率降低。 發明冃的及槪沭： 本發明之第一目的在提供一種製造薄膜電晶體-液 晶顯示器之方法，可有效提高源極/汲極結構與摻雜矽層 之接面效果。 經濟部中央標準局員工消費合作社印製 (諳先閣讀背面之注意事項寫本頁) 本發明之第二目的在提供一種製造薄膜電晶體-液 晶顯示器之方法，可有效提高源極/汲極結構與導電氧化 層之接面效果。 本發明之第三目的在提供一種可有效提高薄膜電 本紙張尺度逋用中國國家標準（CNS) A4規格（210X297公釐） 408500 經濟部中央標準局負工消費合作社印製 A7 B7五、發明説明（） 晶體-液晶顯示器其良率之製造方法 一種在玻璃底材上形成薄膜電晶體（TFT )之方法包 含了下列之步驟。首先’形成第一金屬層於該玻璃底材 上，且飩刻第一金屬層以定義出蘭極結構。接著，形成絕 緣層於第一金屬層與玻璃底材上。然後依序形成政層於該 絕緣層上，並形成摻雜矽層於該砂層之上表面。隨後，進 行蝕刻程序以移除部份矽層與摻雜矽層。其中殘餘之妙層 用以形成TFT所需之通道。接著形成複合層於摻雜矽層與 絕緣層之上，其中値得注意的是該複合層包含了作爲頂層 之接觸層與作爲底層之緩衝層，且第二金屬層位於該接觸 層與緩衝層之間。其中該接觸層與緩衝層可分別用來增加 第二金屬層與透明導電層'摻雜矽層之接面效果》接著蝕 刻該複合層以定義源極/汲極結構，其中該緩衝層相對於 該摻雜矽層的蝕刻選擇性大於1。在定義出源極/汲極結構 後’接著移除被複合層所曝露之摻雜矽層。然後形成保護 層於複合層、矽層與絕緣層之上，其中上述之保護層相對 於接觸層之蝕刻選擇性大於1。接著，蝕刻保護層與絕緣 層以曝露出源極/汲極結構以便與後續所彤成之透明導電 薄膜進行電性連接。然後，形成透明導電薄膜於保護層之 上表面。 圖式簡Μ說昍： 藉由以下詳細之描述結合所附圖示，將可輕易的了 (請先_ 閲讀背面之注—事^^! 填寫本頁) •r. 訂 -線. 本紙張尺度適用中國國家標準（CMS ) A4規格（210 X 297公釐） 408500 A7 B7 經濟部中央標準局員工消費合作社印聚 五、發明説明（） 解上述內容及此項發明之諸多優點，其中： 第一圖爲絕緣透明底材之截面圖，顯示根據傳統技 術所形成薄膜電晶體-液晶顯示器之結構； 第二圖爲絕緣透明底材之截面圖，顯示根據傳統技 術形成保護層結構時所產生之缺陷； 第三圖爲絕綠透明底材之截面圖，顯示根據本發明 形成閘極結構與像素電極之步驟；. 第四圖爲絕緣透明底材之截面圖，顯示根據本發明 形成絕緣層與非晶矽層之歩驟； 第五圖爲絕緣透明底材之截面圖，顯示根據本發明 形成作爲源極/汲極結構之複合層其步驟； 第六圖爲絕緣透明底材之截面圖，顯示根據本發明 形成保護層之步驟； 第七圖爲絕緣透明底材之截.面圖，顯示根據本發明 形成透明導電層.之步驟。 發„明詳細說昍： 本發明提供一個新方法用以製造具有複合層結構 之薄膜電晶體液晶顯示器（TFT)。其中該複合層具有作爲 上層之接觸層、作爲底層之緩衝層、與位於上層與底層之 間的鋁金屬層。値得注意的是該緩衝層相對於n+摻雜矽層 之触刻選擇性大於1 ;而該保護層相對於接觸層的蝕刻選 (請先閲讀背面之注會事填寫本頁) -裝. -訂 線 本紙張尺度賴中賴家標芈（CNS > M規格（21QX297公兹） 408500 A7 B7 五、發明説明（） 擇性大於I，可避免在對保護層進行過度蝕刻程序時，發 生損壞。如此可大幅提昇所製造TFT產品之良率。有關本 發明之詳細說明如下所述》 請參照第三圖，在一較佳實施例中，提供一玻璃、 石英、或類似的材質來作爲透明絕緣底材102。接著可使 用濺鍍法（Sputtering)形成第一金屬層於該玻璃底材102 上’以便用來定義閘極結構。一般.而言，上述第一金屬層 之材料可選擇鉻、鎢、钽、鈦、鉬或其任意組合，此外如 鉻鋁化物亦可作爲第一金屬層之材料。然後對第一金屬層 進行圖案化（pattern)以定義聞極結構104於該玻璃底材 102 上。 請參照第四圖，形成一絕緣層108於閘極結構104 與玻璃底材102之上，以作爲絕緣之用。其中該絕緣層 108之材料可選擇一般之介電材料來加以形成，可氧化 矽、氮化矽、氮氧化矽或其任意組合。在一較佳實施例中， 可使用電漿化學氣相沈積法（PCVD)來形成。製程中的反應 氣體是 SiH4i N2ONH3, SiH4，NH3, N2，N2〇 or SiH2Cl2, NH3, N2，及 N2〇。 隨後，使用熟知技術形成一非晶矽層1 1 0於該絕緣 層108之上，並形成一摻雜非晶矽層112於該非晶矽層 之上表面。接著進行一蝕刻程序，以移除部份非晶矽層110 本紙張尺度適用中國國家標隼（〇呢）八4規格（2〖0父297公楚) (請先間讀背面之注意事一^填寫本頁) 言 經濟部中央標準局I工消费合作社印製408500 A7 B7 V. Description of the Invention (Invention City: This invention relates to a method for manufacturing thin film transistors, especially a thin film transistor-liquid crystal display (TFT-LCD) with a composite source / drain structure. Method: Inspiration from the invention: For a long time, liquid crystal displays have been widely used in digital electronic products such as electronic watches and computers. With the continuous development and progress of thin film transistor-liquid crystal display technology, due to its small size , Light weight, low driving voltage, and low power consumption, it has been widely used in notebook computers, personal digital processing systems, and color televisions, and gradually replaced the traditional display video tube. However, with the film The design of transistor-liquid crystal displays is trending toward large-scale evolution, and it also encounters many problems in manufacturing and development. For example, when manufacturing large-size thin-film transistor-liquid crystal displays, serious signal delay problems often occur. In addition, , Subject to the relevant equipment and materials currently in use, also leads to the production of electricity LCD-LCDs have low product yields, and the production capacity cannot be effectively increased, which leads to high manufacturing costs. Please read the note first-Matter i Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs-in general The TFT-LCD includes a TFT transparent bottom plate formed by a thin film transistor (TFT) and a pixel electrode, and a CF transparent top plate with a color filter. The liquid crystal paper is filled between the TFT transparent top plate and the CF transparent bottom plate. The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 408500 A7 B7 V. Description of the invention () The molecule. In addition, in each unit pixel, by controlling the thin film transistor as a switching element, its smell can be changed. A signal voltage is transmitted from the data bus lines to the unit pixel. When the TFT receives the signal voltage, it will turn on, so that the data voltage carrying the image information can be applied to the corresponding pixel electrode and liquid crystal via the TFT. It should be noted that when the data voltage is applied to the TFT, the arrangement of the liquid crystal molecules will be changed, thus changing its optical characteristics and displaying the shadow. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note on the back to complete this page) As mentioned above, the application of thin film transistor displays in large-scale products often results in extremely serious signal delays. In order to To effectively improve this problem, the resistance of the gate and source / drain structure of the thin film transistor can be reduced in order to improve the efficiency of signal transmission. Therefore, in the choice of materials, aluminum metal is used as the conduction in the transistor. Structure, however, because the ohmic contact (o.hmic con tact) effect between aluminum metal and doped amorphous silicon is not good, it is often necessary to form a buffer layer between the aluminum layer and the doped amorphous silicon layer. The interface layer is used to effectively improve the contact effect when manufacturing a thin film transistor-display. In addition, in the traditional technology, in order to effectively increase production capacity, a back channel etching (BCE) method that can reduce a mask is often used instead of the traditional process (ES, etch stop stopper). In addition, in order to reduce the traditional TFT process steps, effectively reduce the chance of short-circuiting of the device, improve the product yield, and increase the open ratio, an indium tin oxide (I TO) layer is often used to form the entire TFT structure. The top surface is used to turn on the pixel electrode and the source / drain. However, due to the IT0 layer and the aluminum paper size as the source / drain material, the Chinese national standard (CNS > A4 specification (21〇X 297 mm)) 408500 A 7 _B7 __.__ V. Description of the invention () Metal The contact effect is not good, so it is often necessary to form an additional contact layer between the I TO and the aluminum metal in order to improve the continuity of the contact surface. Therefore, in the conventional technology, it is often formed as shown in the first figure TFT structure, wherein a gate 4 is provided on a glass substrate 2; and an insulating layer S is located on the glass substrate 2 to cover the gate 4; an amorphous silicon layer 10 is located on the insulating layer 8 and the gate Above the electrode 4, and an n + doped amorphous silicon layer 12 is formed on the surface of the amorphous silicon layer 10; in addition, a composite layer 14 as a source / drain structure is formed on the n + doped amorphous On the silicon layer 12 as a source / drain structure with better ohmic contact and lower resistance, wherein the composite layer 14 includes a titanium layer 14a as a contact layer and a titanium layer 14c as a buffer layer, and An aluminum layer 14b between the titanium layers 14a and 14c; in addition, a protective layer 16 having vias is formed subsequently On the upper surface of the composite layer 14 and the insulating layer 8, a transparent conductive layer is further formed thereon, and the source / drain structure is connected by the aforementioned via. 14. The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Yinju (read the note on the back to read this page first) However, because the titanium layer 14c and the n + doped amorphous silicon layer 12 have a low etching selectivity, the composite layer 1 4 (that is, titanium / aluminum) is etched. / Titanium composite layer structure) When defining the source / drain structure of a TFT, it will often cause damage to the exposed n + -doped amorphous sand layer 12, resulting in a reduction in product yield. In addition, some people have adopted A molybdenum (Mo) layer 14a, an aluminum layer 14b, and a composite layer 14 (ie, a molybdenum / aluminum / molybdenum composite layer structure) with the molybdenum layer 14c are used as the source / drain structure of the TFT element. However, as shown in the first figure, When the protective layer 16 is etched, an over-etching method is often adopted, but the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied to the source paper size. 408500 A7 B7 V. Description of the invention () For the pole / drain structure, when the protective layer 16 on the upper surface is completely etched After the etching, the molybdenum layer 14a is often damaged in the over-etching process because the etching selectivity of the molybdenum layer 14a and the protective layer 16 is very poor. In addition, the composite layer 14 is etched to define the source / drain. The polar pattern is performed using wet etching, so the effect of the etching process can often not be accurately and effectively controlled. As shown in the second figure, the composite layer 14 (molybdenum layer 14a / aluminum layer 14b / molybdenum layer 14c) ) During the wet etching process, the aluminum layer 14b is caused by the effect of the material on the etching effect. The sidewall etch rate is higher than that of the molybdenum layers 14a and 14c. In this way, a protective layer 16 is formed in the subsequent insulation. When the upper surfaces of the layer 8 and the composite layer 14 are formed, voids 30 will be generated, thereby increasing the chance of defects in subsequent processes, and reducing the yield of the manufactured TFT. Inventions and Inventions: A first object of the present invention is to provide a method for manufacturing a thin film transistor-liquid crystal display, which can effectively improve the interface effect between a source / drain structure and a doped silicon layer. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (see the note on the back of the book written by Xian Xiange) The second object of the present invention is to provide a method for manufacturing a thin film transistor-liquid crystal display, which can effectively improve the source / drain Interface effect between structure and conductive oxide layer. A third object of the present invention is to provide an effective way to increase the size of thin-film electrical paper, using Chinese National Standard (CNS) A4 (210X297 mm) 408500, printed by A7, B7, and Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Crystal-liquid crystal display with its yield method A method of forming a thin film transistor (TFT) on a glass substrate includes the following steps. First, a first metal layer is formed on the glass substrate, and the first metal layer is engraved to define a blue structure. Next, an insulating layer is formed on the first metal layer and the glass substrate. Then, a political layer is sequentially formed on the insulating layer, and a doped silicon layer is formed on the upper surface of the sand layer. Subsequently, an etching process is performed to remove a part of the silicon layer and the doped silicon layer. The remaining wonderful layer is used to form the channel required by the TFT. Next, a composite layer is formed on the doped silicon layer and the insulating layer. It should be noted that the composite layer includes a contact layer as a top layer and a buffer layer as a bottom layer, and a second metal layer is located on the contact layer and the buffer layer. between. The contact layer and the buffer layer can be used to increase the interface effect between the second metal layer and the transparent conductive layer 'doped silicon layer. Then the composite layer is etched to define the source / drain structure, where the buffer layer is opposite to The etch selectivity of the doped silicon layer is greater than one. After defining the source / drain structure ', the doped silicon layer exposed by the composite layer is then removed. Then, a protective layer is formed on the composite layer, the silicon layer and the insulating layer, wherein the etching selectivity of the protective layer with respect to the contact layer is greater than one. Then, the protective layer and the insulating layer are etched to expose the source / drain structure so as to be electrically connected to the transparent conductive film formed later. Then, a transparent conductive film is formed on the upper surface of the protective layer. Schematic Schematic Illustration: By following the detailed description combined with the attached diagram, it will be easy (please first _ read the note on the back-something ^^! Fill out this page) • r. Order-line. This paper The scale is applicable to the Chinese National Standard (CMS) A4 specification (210 X 297 mm) 408500 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention () Explain the above content and many advantages of this invention. Among them: One image is a cross-sectional view of an insulating transparent substrate, showing the structure of a thin film transistor-liquid crystal display formed according to the conventional technology; the second image is a cross-sectional view of an insulating transparent substrate, showing the production of a protective layer structure according to the traditional technology Defects; the third figure is a cross-sectional view of an absolutely green transparent substrate, showing the steps of forming a gate structure and a pixel electrode according to the present invention; the fourth figure is a cross-sectional view of an insulating transparent substrate, showing the formation of an insulating layer and Steps of an amorphous silicon layer; The fifth figure is a cross-sectional view of an insulating transparent substrate, showing the steps for forming a composite layer as a source / drain structure according to the present invention; the sixth figure is a schematic view of an insulating transparent substrate A cross-sectional view shows a step of forming a protective layer according to the present invention; a seventh view is a cross-sectional view of an insulating transparent substrate, and a cross-sectional view shows the step of forming a transparent conductive layer according to the present invention. The invention is described in detail: The present invention provides a new method for manufacturing a thin film transistor liquid crystal display (TFT) having a composite layer structure. The composite layer has a contact layer as an upper layer, a buffer layer as a lower layer, and an upper layer. The aluminum metal layer between the substrate and the bottom layer. It should be noted that the contact selectivity of the buffer layer relative to the n + doped silicon layer is greater than 1; and the etching selection of the protective layer relative to the contact layer (please read the note on the back first) Fill out this page) -Packing. -The book size of the booklet is based on the Chinese standard (CNS > M size (21QX297)) 408500 A7 B7 5. Description of the invention () Selectivity is greater than I, which can avoid the protection layer When the over-etching process is performed, damage occurs. This can greatly improve the yield of the manufactured TFT products. The detailed description of the present invention is described below. Please refer to the third figure. In a preferred embodiment, a glass and quartz are provided. Or similar material as the transparent insulating substrate 102. Sputtering can then be used to form a first metal layer on the glass substrate 102 'to define the gate structure. Generally. As the material of the first metal layer, chromium, tungsten, tantalum, titanium, molybdenum, or any combination thereof can be selected. In addition, chromium aluminide can also be used as the material of the first metal layer. Then, the first metal layer is patterned (pattern ) To define the electrode structure 104 on the glass substrate 102. Referring to the fourth figure, an insulating layer 108 is formed on the gate structure 104 and the glass substrate 102 for insulation. The insulating layer 108 is used for insulation. The material can be selected from general dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In a preferred embodiment, plasma chemical vapor deposition (PCVD) can be used. Formation. The reaction gases in the process are SiH4i N2ONH3, SiH4, NH3, N2, N2O or SiH2Cl2, NH3, N2, and N2O. Subsequently, an amorphous silicon layer 1 110 is formed on the insulating layer 108 using well-known techniques. A doped amorphous silicon layer 112 is formed on the upper surface of the amorphous silicon layer. Then, an etching process is performed to remove part of the amorphous silicon layer 110. This paper size is applicable to the Chinese national standard (0?) 4 specifications (2 〖0 father 297 male Chu) (please first On the back of a ^ precautions Complete this page) Ministry of Economic Affairs Bureau of Standards Introduction I work printed consumer cooperatives
I 4065CC Λ7 Α7 Β7 五、發明説明（） 與摻雜非晶矽層1 12並曝露出該絕緣層1〇8之上表面.其中 殘餘之非晶矽層11 〇用來覆蓋於該閘極結構1 〇 4與絕緣層 1 0 8之上以作爲後續所形成薄膜電晶體之通道 (channel)。在一較佳實施例中，可藉著形成一正光阻於 摻雜非晶矽層112之上，再以閘極結構1〇4作爲背面曝光時 之罩冪，進行如第四圖中所示箭頭方向之背面曝光。隨後 將該正光阻曝光的部份移除，如此一來該正光阻僅有位於 閘極結構1 04上方的部份窜被保留。再使用所保留之正光 阻作爲蝕刻罩冪，對非晶矽層1 1 〇與摻雜非晶矽層1 i 2進行 鈾刻。 接著，請參照第五圖，形成複合層114於該n +摻雜 矽層112與該絕緣層108之上表面，其中該複合層114包含 作爲頂層之接觸層114a與作爲底層之緩衝層114c，且一第 二金屬層114b位於該接觸層114a與緩衝層114c之間。値得 注意的是該緩衝層11 4c相對於n +摻雜矽層112之蝕刻選擇 性大於1，且該緩衝層114c可有效提昇第二金屬層114b與 η +摻雜矽層112之導通性。在一較佳實施例中，該接觸層 1 1 4a可選擇鉻、鈦或其任意之組合；另外該第二金屬層 1 1 4b則可選擇鋁、或鋁合金來加以形成；至於作爲下層之 緩衝層114c其材料則可選擇鉻、鉬或其任意之組合。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事一^填寫本頁) 接著藉由對複合層1 1 4進行蝕刻程序，以便定義出 TFT之源極/汲極結構圖案。如同上述，由於在對複合層Π 4 本紙張尺度適用中國國家標準（CNS ) A4规格（210 X 297公釐） 408500 A7 B7 經濟部中央標準局員工消费合作社印製 五、發明説明（） 進行鈾刻時，其緩衝層114c相對於n +摻雜政層112之餓刻 選擇性大於1，是以在藉由14刻術來定義源極/汲極圖案 時，將不致於對其下之n +摻雜矽層112造成損壞。在定義 出源極/汲極結構圖案後，進行一蝕刻程序以移除被複合 層1 1 4所曝露之部份n +摻雜非晶矽層1 1 2。一般而言，可使 用複合層1 1 4來作爲蝕刻n +摻雜非晶矽層1 1 2之罩冪。此 外，也可選擇形成一光阻層作爲蝕刻罩冪，以便進行蝕刻 n +摻雜非晶矽層之程序。， 隨後，如第六圖所示，形成保護層116於該複合層 114、非晶砂層11〇、n +接雜砂層112與絕緣層108之上。 其中値得注意的是上述該保護層116相對於接觸層114a 之蝕刻選擇性大於1。其中該保護層116之材料可選擇一 般之介電材料，如氮化層、氧化層或其任意之組合，同時 該保護層可以爲一層以上之結構。在一較佳實施例中，可 使用化學氣相沈積法（CVD)。 然後，蝕刻保護層116與絕緣層108以曝露出作爲源 極/汲極結構之複合層114之上表面。其中値得注意的是， 在對保護層11 6進行過度蝕刻程序時，對複合層11 4而言， 當其上表面之保護層11 6被移除後，將直接曝露於蝕刻環 境中。然而如同上述，由於位於複合層11 4上層之接觸層 1 1 4a相對於保護層1 1 6之餽刻選擇性小於1，是以在進行過 度蝕刻程序中，將不致於造成該接觸層11 4a的損壞。 (請先閱讀背面之注意事〇：填寫本頁) .裝. 訂_ 線_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 4085G0 A7 _B7_ 五、發明説明（） 接著，請參照第七圖，形成透明導電層120於保護 層116之上表面，並藉由蝕刻保護層時形成之導通孔與作 爲該源極/汲極結構之複合層114連結。在一較佳實施例 中，於溫度大約250°C的環境中，形成厚度約200至800埃 之銦錫氧化物（ITO)薄膜來作爲透明導電層120。 本發明具有許多優。例如.，藉著運用鉬、鉻材料 來作爲鋁金屬層與其下n+摻雜矽層之間的緩衝層，可以有 效的提高其接面之導通效果，並且由於所形成之緩衝層相 對於n +摻雜矽層之蝕刻選擇性大於1，是以在進行蝕刻程 序以定義源極/汲極圖案時，可避免對位於緩衝層下方之 n +摻雜矽層造成損壞；此外，藉著運用鉻、鈦材料來作λ 鋁金屬層與ITO層之間的接觸層，除了可有效的提高鋁金 層層與IT0層之接面效率外，並由於所形成保護層相對於 接觸層之蝕刻選擇性大於1，是以在對保護層進行過度鈾 刻程序時，將不致於對接觸層造成損壞，從而降低了所製 造TFT產品之良率。 本發明雖以一較佳實例闡明如上，然其並非用以限 定本發明精神與發明實體僅止於此一實施例爾。對熟悉此 領域技藝者，在不脫離本發明，之精神與範圍內所作之修 改，均應包含在下述之申請專利範圍內。 本紙張尺度適用中國國家標辛·（ CNS ) A4规格（210 X 297公釐） I---^ I I I 裝 [訂— 腺 1 (請先閱讀背面之注意事{3填寫本頁)~yI 4065CC Λ7 Α7 B7 V. Description of the invention () and doped amorphous silicon layer 1 12 and exposing the upper surface of the insulating layer 108. The remaining amorphous silicon layer 11 〇 is used to cover the gate structure 104 and the insulating layer 108 are used as channels for a thin film transistor to be formed subsequently. In a preferred embodiment, as shown in the fourth figure, a positive photoresist can be formed on the doped amorphous silicon layer 112, and the gate structure 104 is used as the mask power for the back exposure. The back of the arrow direction is exposed. The exposed portion of the positive photoresist is subsequently removed, so that only a portion of the positive photoresist located above the gate structure 104 is retained. Then, the remaining positive photoresist is used as an etching mask, and uranium etching is performed on the amorphous silicon layer 1 10 and the doped amorphous silicon layer 1 i 2. Next, referring to the fifth figure, a composite layer 114 is formed on the upper surfaces of the n + doped silicon layer 112 and the insulating layer 108. The composite layer 114 includes a contact layer 114a as a top layer and a buffer layer 114c as a bottom layer. A second metal layer 114b is located between the contact layer 114a and the buffer layer 114c. It should be noted that the etching selectivity of the buffer layer 11 4c relative to the n + doped silicon layer 112 is greater than 1, and the buffer layer 114 c can effectively improve the conductivity of the second metal layer 114 b and the η + doped silicon layer 112. . In a preferred embodiment, the contact layer 1 1 4a may be selected from chromium, titanium, or any combination thereof; in addition, the second metal layer 1 1 4b may be formed from aluminum or aluminum alloy; as a lower layer, The material of the buffer layer 114c may be chromium, molybdenum, or any combination thereof. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note on the back ^ fill out this page) and then perform the etching process on the composite layer 1 1 4 to define the source / drain structure pattern of the TFT. As mentioned above, since the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to the paper layer of the composite layer, the paper size is 408500 A7 B7. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. At the time of etching, the selectivity of the buffer layer 114c relative to the n + doped political layer 112 is greater than 1, so that when the source / drain pattern is defined by 14 engraving, the n below it will not be affected. The doped silicon layer 112 causes damage. After the source / drain structure pattern is defined, an etching process is performed to remove a part of the n + doped amorphous silicon layer 1 12 exposed by the composite layer 1 1 4. In general, the composite layer 1 1 4 can be used as a mask for etching the n + doped amorphous silicon layer 1 1 2. In addition, it is also possible to form a photoresist layer as an etching mask to perform the process of etching the n + doped amorphous silicon layer. Then, as shown in the sixth figure, a protective layer 116 is formed on the composite layer 114, the amorphous sand layer 110, the n + doped sand layer 112, and the insulating layer 108. It should be noted that the etching selectivity of the protective layer 116 with respect to the contact layer 114a is greater than one. The material of the protective layer 116 may be selected from general dielectric materials, such as a nitride layer, an oxide layer, or any combination thereof. At the same time, the protective layer may have more than one structure. In a preferred embodiment, chemical vapor deposition (CVD) can be used. Then, the protective layer 116 and the insulating layer 108 are etched to expose the upper surface of the composite layer 114 as a source / drain structure. It should be noted that, when the over-etching process is performed on the protective layer 116, for the composite layer 114, when the protective layer 116 on the upper surface is removed, it will be directly exposed to the etching environment. However, as mentioned above, since the contact selectivity of the contact layer 1 1 4a located on the upper layer of the composite layer 11 4 with respect to the protective layer 1 16 is less than 1, the contact layer 11 4a will not be caused during the excessive etching process. Damage. (Please read the note on the back 〇: fill in this page first). Binding. Order _ Thread _ This paper size is applicable to China National Standard (CNS) A4 (210X297 mm). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4085G0 A7 _B7_ 5. Description of the invention () Next, referring to the seventh figure, a transparent conductive layer 120 is formed on the upper surface of the protective layer 116, and the via hole formed when the protective layer is etched is used as a composite of the source / drain structure. Layer 114 is connected. In a preferred embodiment, an indium tin oxide (ITO) film having a thickness of about 200 to 800 angstroms is formed as the transparent conductive layer 120 in an environment at a temperature of about 250 ° C. The invention has many advantages. For example, by using molybdenum and chromium materials as the buffer layer between the aluminum metal layer and the n + doped silicon layer below it, the conduction effect of the interface can be effectively improved, and the buffer layer formed relative to n + The etching selectivity of the doped silicon layer is greater than 1, so that when the etching process is performed to define the source / drain pattern, damage to the n + doped silicon layer under the buffer layer can be avoided; in addition, by using chromium Titanium material is used as the contact layer between the λ aluminum metal layer and the ITO layer, in addition to effectively improving the interface efficiency between the aluminum gold layer and the IT0 layer, and due to the etch selectivity of the protective layer formed relative to the contact layer If it is greater than 1, the contact layer will not be damaged when the protective layer is subjected to an excessive uranium engraving process, thereby reducing the yield of the manufactured TFT product. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the invention of the present invention to only this embodiment. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. This paper size applies to Chinese National Standard Xin (CNS) A4 size (210 X 297 mm) I --- ^ I I I Binding [Booklet — Gland 1 (Please read the note on the back first {3Fill this page) ~ y