TW406445B - The growing method of the nitride semiconductor, nitride semiconductor substrate and the nitride semiconductor device - Google Patents

Abstract

This invention relates to a kind of growing method of the nitride semiconductor crystal, having very few crystal defects and could be used as the substrate. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Description

Printed by the Central Government Bureau of the Ministry of Economic Affairs, Masonry and Consumer Cooperatives 406445 V. Description of the invention () [Application fields in the industry] The present invention relates to a method for growing a nitride semiconductor, a nitride semiconductor substrate, and a nitride semiconductor element, especially A method for growing a nitride semiconductor with a good crystal quality by using a substrate formed of a material different from the nitride semiconductor, a nitride semiconductor substrate and a nitride semiconductor device. [Knowledgeable technology and problems to be solved by the invention] When growing a semiconductor on a substrate, if the crystal lattice of the semiconductor substrate used can be matched with the semiconductor to be grown, a semiconductor with few crystal defects and good crystallinity can be grown. Things are well known. However, in the present world, there is no one that can match the nitride semiconductor on the crystal lattice, and nitride semiconductor crystals can be stably grown thereon, and there is a substrate with excellent crystallinity. A nitride semiconductor is grown on a substrate that does not match its lattice, such as sapphire, spinel, or silicon carbide. On the one hand, various research institutions are trying to make gallium nitride (hereinafter referred to as GaN) bulk crystals that can match the lattice of nitride semiconductors, but the reports obtained so far are only a few millimeters in overall size. (Mm). That is, until now, there has not been obtained a practical GaN bulk crystal which can be cut out from a large number of wafers and actually used as a substrate for growing a nitride semiconductor layer. Therefore, in GaN substrate fabrication technology 10, for example, Japanese Unexamined Patent Publication No. 7_202265 or Japanese Unexamined Patent Publication No. 7_165498 describes the formation of an oxide buffer layer (hereinafter referred to as Zn0) on a sapphire substrate, and the Zn0 buffer layer After the nitride semiconductor is grown, the technics of the buffer layer is removed and dissolved. However, the knot of the buffer layer grown on the sapphire substrate 4 This paper size is applicable to China National Standard (CNS) A4 (210X297) ) I -------- ^ ------ ΐτ ------.:^ (Please read the notes on the back before filling this page) Printed 406445 A7 '---------- 87__ V. Description of the invention () --- Poor' so that nitride semiconductors are grown on it, and it is difficult to obtain nitride semiconductors with good σθ quality . In addition, it is difficult to continuously grow random compound semiconductors on the ZnO buffer layer of the thin film to obtain a thickness sufficient for use as a substrate '. When manufacturing nitride semiconductor electronics for various electronic devices such as light-emitting diodes (LED) devices, laser diodes as y-devices (LD) devices, and light-sensitive devices, When a substrate made of a nitride semiconductor with a low crystal defect is formed thereon, a new nitride semiconductor constituting the element structure can be grown thereon with few lattice defects, and therefore, the performance of the obtained device will be long. With this, it is possible to realize high-performance components that have not previously been possible. Therefore, an object of the present invention is to provide a method for growing a nitride semiconductor crystal having excellent crystallinity. Specifically, it provides a method for growing a nitride semiconductor crystal that can be used as a nitride semiconductor substrate, a nitride semiconductor substrate therefor, and a nitride semiconductor element (device) provided on such a nitride semiconductor substrate. [Means for Solving the Invention] A first aspect of the method for growing a nitride semiconductor according to the present invention includes (a) a heterogeneous substrate having a main surface formed of a material different from the nitride semiconductor, and a main substrate on the heterogeneous substrate. A process for forming a first selective growth mask having a plurality of first windows on the support formed by a bottom layer formed of a nitride semiconductor on the surface so that the bottom surface of the support is selectively exposed from the window, And (b) using a gaseous Group 3 element source and a gaseous nitrogen source to cause the nitride semiconductor to grow from the above-mentioned bottom surface exposed by the window until the nitride semiconductor grown from the adjacent window is selected for growth masking (please read first (Notes on the back then fill out this page)

In In · Install · 4β Line 5 This paper is compliant with national standards (CNS) A4 (规格 χ 297 mm) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 406445 A7 --- B7 ) The process until the upper surface of the mold is integrated. At this time, the total surface area of the bottom layer covered by the i-th selective growth mask is larger than the total surface area of the bottom layer exposed from the i-th window, which is preferable. A second aspect of the method for growing a nitride semiconductor according to the present invention includes (a) forming a substrate with a plurality of window windows and a first selection on a support including a heterogeneous substrate formed of a material different from the nitride semiconductor and having a main surface. Growing the mask so that the surface of the support can be partially exposed from the window, and the total surface area of the portion of the support covered by the first selection growth mask is greater than the surface area of the support exposed from the first window Engineering, and (b) using a gaseous Group 3 element source and a gaseous nitrogen source to make the first nitride semiconductor grow from the surface of the support exposed from the window until the nitride semiconductor grown from the adjacent window is selected The upper surface of the growth mask is integrated into one process. In the first aspect and the second aspect of the present invention, the first selective growth mask is preferably composed of a plurality of individual lines which are isolated from each other, constitute a first window between them, and extend in parallel. In the first and second viewpoints, the ratio of the width of each individual line to the width of each first window is preferably more than 1 'and less than 20. In the first viewpoint and the second viewpoint, the 'heterogeneous substrate is a sapphire substrate whose main structure is the (0001) plane, and the individual lines extend toward the direction of the sapphire's (11110) plane's vertical direction; or a heterogeneous substrate It is a sapphire substrate whose main structure is the (lllo) surface, and each individual line is extended to the vertical direction of the (1,02) surface of the sapphire; or 'a dissimilar substrate whose main surface is configured as the (111) surface It is particularly desirable that the spinel substrate has individual lines extending in a direction perpendicular to the (110) surface of the spinel. Also, in the first or second viewpoint, it is possible to use organic gold for project (b) 6 --------- ^ --- ^ ----? Τ ------ Λ (Please Please read the notes on the back before filling in this page) *-， 一 * Public 7 29 A7 B7 406445 V. Description of the invention (It is the first growth of nitride semiconductor crystals by vapor-phase epitaxial growth method. On the nitride semiconductor crystal, the second nitride semiconductor crystal is grown by a dentate vapor growth method. Alternatively, the first nitride semiconductor crystal may be included in the first or second viewpoint on the nitride semiconductor crystal grown in the process (b). (C) forming a second selective growth mask having a plurality of second windows that can selectively expose the first nitride semiconductor surface (c), and using a gaseous Group 3 element source and a gaseous nitrogen source to make the second nitride semiconductor Process (d) from the first argon semiconductor surface exposed from the second window to the growth until the second nitride semiconductor grown from the adjacent window is integrated on the upper surface of the second selective growth mask. In this case, the second selection growth mask is the same as the first selection growth mask. The third aspect of the method for growing a nitride semiconductor of the present invention includes (a) forming a nitride semiconductor layer on a support including a dissimilar substrate having a surface formed of a material different from the nitride semiconductor. A process of forming a plurality of recesses having a bottom surface substantially parallel to the support surface on the nitride semiconductor layer; (c) selectively forming a first growth control mask on the top surface of the nitride semiconductor layer; A process of selectively exposing the nitride semiconductor film from the side surface of the recess; and an engineer who grows a first nitride semiconductor from the exposed surface of the nitride semiconductor using a gaseous 3 element source and a gaseous nitrogen source. In this case, it is preferable that the growth control mask of the first aspect adopts the same structure as the growth mask of the first selection in the second and second aspects. In the third aspect of the process (c), if it includes It is particularly desirable to form a second growth control mask on the bottom surface of the recess so that the nitride semiconductor layer is selectively exposed from the side surface of the recess. In this case, the first growth The masks are isolated from each other, and are formed as the first window between each other and extend in parallel ^ ------ 1T ---------- 0 (Please read the precautions on the back before filling (This page) Printed by the Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 406445 V. Description of the invention () Most of the individual lines are better. In this case, the different substrates are mainly composed of (000 1) planes. Sapphire substrate with individual lines extending in the direction of the sapphire (ιΰο) plane; or a heterogeneous substrate with a sapphire substrate mainly composed of (π3〇) planes, and each individual line is directed toward sapphire (1 20) planes extending vertically; or a heterogeneous substrate is a spinel substrate whose main surface is a (1U) plane, and the individual lines are extending vertically to the (110) plane of the spinel , Especially ideal. According to the present invention, when a nitride semiconductor crystal is grown, the molar ratio of the gaseous nitrogen source to the gaseous Group 3 element source supplied is preferably 2,000 or less. In addition, according to the present invention, it is possible to provide a nitride semiconductor substrate which is composed of a nitride semiconductor crystal and has a first main surface and a second main surface. The crystal defects near the first main region are relatively few. There are relatively many crystal defects in the area close to the second main surface. Moreover, the nitride semiconductor substrate provided is composed of a nitride semiconductor crystal, and has a first main surface and a second main surface. The crystal defects in the main surface area are below lx 105 / cra2. According to the present invention, it is possible to provide a nitride semiconductor element including a structure of a nitride semiconductor element supported by the nitride semiconductor substrate of the present invention. Printed by the Ministry of Economic Affairs of the Central Bureau of Quasi-Bureau Consumer Product Cooperation (please read the notes on the back before filling out this page) and ’The further development of this invention is as follows and described in the scope of patent application. The nitride semiconductor in the present invention can be represented by the formula: inaAlb_Gai. BN (where 〇 $ a, osb, a + bSl) (In: indium, A1: aluminum, Ga: doped, N: nitrogen). [Example] 8 This paper is used in China National Standards (CNS) A4 size (210X297 mm), printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Cooper Consumer Cooperative 406445 A7 _ B7 5. Description of the invention () In the preferred embodiment of the present invention, the same or similar parts are represented by the same symbols in all the figures. FIGS. 1A to 1C are cross-sectional views illustrating the principle of the method for growing a nitride semiconductor according to the i-th aspect of the present invention, in accordance with the engineering order. As shown in FIG. 1A, a substrate (hereinafter referred to as a heterogeneous substrate) n formed of a material different from a nitride semiconductor and a bottom layer formed of a nitride semiconductor provided on the substrate n are prepared first.轴承 体 10。 The support body 10. The bottom layer mentioned in the scope of this specification and the patent claims is a layer made of a nitride semiconductor on a heterogeneous substrate 11 instead of the growth method according to the present invention, but a nitride semiconductor produced by a normal nitride semiconductor growth method. The base layer 12 may have a single-layer structure or a multilayer structure. The bottom layer 12 in FIG. This buffer layer can alleviate the lattice mismatch between the heterogeneous substrate 11 and the nitride semiconductor crystal to be grown on the bottom layer, so that a nitride semiconductor with better crystallinity can be grown on it. Generally, it is a low temperature of less than 900 °, and usually it is grown at a low temperature of 50 to 80 (rc), and the thickness β is about tens of angstroms (A) to hundreds of angstroms. This low-temperature buffer layer is It is best to form a pure gallium nitride (GaN) without doping impurities. In the present invention, by forming the bottom layer into a multilayer structure, a nitride semiconductor crystal with fewer crystal defects can be formed thereon. The bottom layer of the multilayer structure in the invention can be formed by forming a nitride semiconductor layer on the low-temperature buffer layer provided on the heterogeneous substrate 11 as described above. The nitride semiconductor layer to be formed again is AlxGaUxN ( 〇SxS〇.5) is best formed. In addition, the re-formed vaporized semiconductor layer is thicker than the low-temperature buffer layer, and it is best to form a thickness of 10 or less. The bottom layer 12 is a gaseous Group 3 Element source and gaseous gas 9 This paper size is applicable to China National Standard (CNS) 8-4 specifications (2 丨 0 > < 297 male thin) Pull-out iT ------ 0 (Please read the precautions on the back before filling this page;} Α7 Β7 ^ 06445 V. Description of the invention () Source, organic metal vapor phase epitaxial growth method (hereinafter referred to as MOVPE) suitable for the growth of nitride semiconductors, molecular directed epitaxial growth method (hereinafter referred to as MBE) or halogenation The vapor phase directional epitaxial growth method (hereinafter referred to as HvpE), etc., can be grown by any known method. Referring to FIG. 1A again, the bottom layer 12 formed on the heterogeneous substrate U is formed to form a bottom layer. 12 Selective growth mask 13 with a part of (selective) exposure window having multiple receiving windows 14a to 14d. In Fig. 1a, the selective growth mask 13 is in the current form, and each has a substantially rectangular cross-section. The lines composed of lines 13a to 13e are shown as examples. The gap between the lines in Figure i is equivalent to windows 14a to 14d. The following windows 14a to 14d will be collectively referred to as windows 14 only. Then 'such as As shown in Figure 1B, according to the present invention, a gaseous Group 3 element source and wind So that the semiconductor semiconductor 15 is grown from the surface portion of the bottom layer 12 exposed from the windows 14a to 14d of the selective growth mask 13. In this way, the nitride semiconductor is selectively covered by the surface of the selective growth mask 13 (or selected) When the substrate 12 is grown on the substrate 12, the nitride semiconductor will not grow on the entire surface of the selective growth mask 13 in the initial stage, but only on the substrate 12 exposed by the window 14. The growth of nitride semiconductors. When the nitride semiconductor continues to grow beyond the upper end face of the mask 13, each nitride semiconductor crystal 15 will pass through each window 4 and grow laterally on the upper face of each selective growth mask 13. The nitride semiconductor 15 grown in the lateral direction is different from the nitride semiconductor grown in the vertical direction in the bottom layer 12. The crystal defects of the bottom layer 12 are covered by the selective growth mask, so the crystal defects of the bottom layer 12 are difficult to transfer. In addition, although the crystal defects of the bottom layer 12 will extend laterally as the nitride semiconductor 15 grows above the selective growth mask, there is also a tendency to stop on the way β. __ 10 This paper conforms to Chinese national standards (CNS) Α4 specification (210X297 mm) t ------, 玎 ------ ii (Please read the notes on the back before filling out this page} System A7 B7 406445 V. Description of the invention (Although crystal defects transferred from the window 14 may also appear on the surface of the grown semiconductor layer, it also tends to stop on the way. This makes the nitride semiconductor crystal 15 When the nitride semiconductor continues to grow, it will grow laterally on the upper surface of the selective growth mask 13, and adjacent nitride semiconductor crystals that also grow in the vertical direction at the same time are connected to each other, as shown in Figure C. At the end, all the crystals 15 will be combined to form the overall nitride semiconductor crystal 16. Existing at the approximate center position of each line mask 13a ~ 13e, its cross section is triangular and extends over the line mask. The vertical narrow cavities 17a to 17e of the molds 13a to 13e are evidence that the adjacent nitride semiconductor crystals 15 grow laterally on the upper surface of the selective growth mask 13 and then grow in the longitudinal direction to form a single body. i 圊 A ~ the bottom layer 15 in FIG. 1C, the nitride semiconductor crystal 丨 5, and the integrated nitride semiconductor crystal 16 in the wavy lines and zigzag lines indicate crystal defects (through transition ^ FIG. 5A, Figure 6A to 6〜c)). In more detail, 'the substrate grown on the heterogeneous substrate U is grown because of a lattice mismatch between the heterogeneous substrate U and the nitride semiconductor. There will be more crystal defects in the 15 portion of the nitride semiconductor junction, and the crystal defects will pass to the growth top surface in the growth table of the nitride semiconductor 15. On the one hand, the nitrogen formed on the selective growth mask π The part 10 of the semiconductor crystal of the compound semiconductor "is not grown from a heterogeneous substrate n or the bottom layer 12", but is a nitride semiconductor crystal 16 that grows laterally and finally is formed by the integration of adjacent nitride semiconductor junctions 15 into one. Therefore, The number of nitride semiconductor crystals 16 formed on the selective growth mask 13 and the number of crystal defects and the crystals directly grown from the heterogeneous substrate 11 or the nitride semiconductor crystals initially grown from the bottom layer 12 in the windows 14a to 14f Partial phase 11 Private paper size applies Chinese National Standard (CNS) M specification (210x297 mm) Rape-(Please read the precautions on the back before filling this page}

• Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, and printed by the Central Standards Bureau of the Ministry of Economic Affairs, and printed by the Bayer Consumer Cooperatives of the Ministry of Economics, printed 406445 a? Very few. This integrated nitride semiconductor is used for various kinds of nitride semiconductor layers to be constructed as equipment structures. When it is used in a board, its crystallinity is better than before, and its performance can be obtained for nitride semiconductor devices. , ', Then' also refer to No.! Wai A ~ No.!囷 c explains the principle of the nitride semiconductor growth method according to the second aspect of the present invention. In the nitride + conductor growth method of the second aspect, it is prescribed that the total surface area of the portion covered by the selected growth mask u supporting Sha 10 is larger than that of the portion exposed by the window 10 of the support 10. Under the condition that the total surface area is large, the selective growth mask 13 is formed. In this way, the total surface area covered by the selective growth mask 13 of the support body 10 is larger than the total surface area of the support body 10 exposed by the window 14, and a nitride semiconductor junction 2 16 having fewer crystal defects can be obtained. In the second aspect, in addition to the relationship between the total surface area covered and the total surface area of dew =, the remaining semi-conductive crystals can be grown and integrated in the same way as in the first aspect (see the above-mentioned reference to the first丨 Explanation of the first point from Fig. A to Fig. 1C). In the second viewpoint, the reason described above related to the second viewpoint is that the existence of the bottom layer 12 is desirable. However, the underlying I] may be omitted. That is, the support referred to in the present specification and the scope of the patent application may be constituted only by a heterogeneous substrate 11 or a heterogeneous substrate 11 and a bottom layer 12 formed thereon. Of course, “in the first viewpoint” may be used. As in the second aspect, the total surface area covered by the selective growth mask 13 of the support 10 is larger than the total surface area of the support 10 exposed by the windows 14a to 14f to form the selective growth mask 13, It is ideal. Next, 'explain the theory of the growth method of the gaseous semiconductor of the present invention. 12 This paper size is applicable to the Chinese national standard ((: >) 5) 8 4 grid (210 乂 297 mm) ^ ------ ΪΤ- ----- ^ (Please read the notes on the back before filling this page) ^ 06445 ,, A7

Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. < Different substrate> As described above, the 'different substrate' is not specifically limited as long as it is formed of a material different from a nitride semiconductor. For example, sapphire-like, spinel (MgAl2) having a C-plane ((001) plane), an R-plane ((ΓΓ02) plane), or an A-plane ((11)) plane as a main plane can be used. 4) and other insulating substrates; or like silicon carbide (SiC) substrates (including hexahydrogen (6H), tetrahydrogen (4H), three carbon (3C)) substrates' zinc sulfide (zns) substrate gallium arsenide (GaAs) substrate) And silicon substrates and other substrates formed of materials different from nitride semiconductors. In addition, an oxide substrate (for example, a Zn0 (oxidation) substrate, a LaxSri xAlyTai "substrate that can match the lattice of a nitride semiconductor (such as a Zn0 (oxidation) substrate, a LaxSri xAlyTai" substrate (La: Net 'Sr: Record' A1: Ming, Ta: Group, 0: Oxygen) substrate ), Although there is a tendency to decompose in the growth of gaseous semiconductors, it can still be used. Dissimilar substrates are those with a main surface size of 1 inch or 1 inch square shape, and a diameter of 1 Dimensions of 3 to 3 inches, or 1 to 3 inches, are preferred. The surface size of the nitride semiconductor crystals grown by the present invention can also be approximately the same as the surface size of the heterogeneous substrate. _ The heterogeneous substrate 11 also uses a substrate having a main surface formed as an inclined surface from a horizontal plane. More preferably, the main surface is formed as a stepped inclined surface. For example, refer to FIG. 2 for a sapphire having a stepped inclined surface. When the enlarged view of the cross-section of the substrate 11 is specifically explained, the substrate 丨 has a substantially horizontal platform portion A, and the surface unevenness of each platform portion a of the step portion is adjusted to an average of about 0.5 Angstroms (again), It is about 2 angstroms, and it is very regular. The height difference B of each step should be less than 30 angstroms, and preferably 25 angstroms or less, and most preferably 20 angstroms or less. The lower limit is preferably more than 2 angstroms. This step with bevel $ 13 This paper method is applicable to China National Standards (CNS) A4 specifications (2lOX297 male |) I line (please read the precautions on the back before filling This page) A7 406445 V. Description of the invention (The stepped knife is ideally formed continuously on the entire surface of the substrate of a different type, but it can also be formed on a part of it. The oblique angle 0 means as the second As shown in the figure, the angle between the straight line connected to the bottom of the majority of the step heights forming the step-like slope and the horizontal plane of the uppermost step and the stage. Especially the sapphire substrate with the c-plane as the main surface as the heterogeneous substrate At 11:00, the inclination angle Θ from the C plane should be within 1 degree, ideally below 0 °, and most reasonable below 0 °. Using such a dissimilar substrate with a main surface forming an inclined plane, The nitride semiconductor grown according to the present invention and the heterogeneous substrate can be made The distance between the atoms is close, and a nitride semiconductor substrate with less crystal defects can be obtained. ≪ Selection growth mask > The selection growth mask 13 is a material that cannot substantially grow nitride on its surface. This selective growth mask The mold 13 is formed of a material that does not allow nitride semiconductors to grow on its surface, or that is difficult to grow. Such materials can be used, for example, as oxides (Si0j, nitrides (sixNy), oxides (Ti. x), ZrOx and other oxides or nitrides, or multilayer films containing these, or metals with melting points above 1200 ° C (such as tungsten (w), iridium (Ir), platinum (pt)) Yes. The material of these selective growth masks has a high temperature that can withstand a growth temperature of about 600 to about 1 00c when the gaseous semiconductor is grown according to the present invention, and the surface of For the growth of nitride semiconductors, or those that are difficult to grow, "When the material of the growth mask is selected to be formed on the surface of the support 10, for example, vapors such as vapor deposition, sputtering, and chemical vapor deposition (CVD) can be used. Phase film formation technology. And 'when these materials are used to form a growth mask 13 with a window 14', a photo-etching technique can be used to form a photomask with a predetermined shape '. Using this first mask, the above materials can be formed into a nitrogen phase. A selective growth mask 13 having a predetermined shape is formed. Select the shape of the growth mask π. This paper size applies Chinese National Standard (CNS) A4 size (210X 297 male I). Gutter (please read the precautions on the back before filling this page). System · One—-40 ^ 44 ^ V. Description of the invention (): There is no special limitation. For example, dots can be used to form the “blank” shape of a large number of individual lines, as described later. ideal. The knife is formed on the selective growth mask 13 as described above. It is ideal that the growth mask 13 is composed of individual lines Ua to 13e as shown in FIG. These 2's have a multi-mode width (WS) to have. . … More two = _ ′ and it is ideal to have 5 to 20, and each line = when: the ratio of the width (Ww) of each window 14 to its width-mask and ^ 10 is more desirable. In particular, as mentioned above, the width of the line release is the width of the window, which is large. Therefore, in this case, the ratio of Ws / Ww should be more than ^, and below 20 is the ideal, and more than i , And the most ideal in the following. If the interval (Ww) of the line mask is less than or equal to 8 mm, it is preferably equal to or less than 5 mm, more preferably equal to or less than 3 mm, so that nitride semiconductor crystals with less crystal defects can be grown. The interval (Ww) of the line mask is preferably equal to or greater than 0 ". The respective line masks are formed on the entire surface of the support body 10 with substantially the same width and substantially the same thickness' and at substantially the same interval, and are parallel to each other. The above is preferable. The thickness of the selective growth mask 13 is preferably in the range of 0.01 to 5 arrays, and more preferably 0.1 to 3 陴 and 0 "to 2_. The consumer sample cooperation of the Central Samples Bureau of the Ministry of Economic Affairs of Du Printed Selective Growth Mask 13 is to prevent nitride semiconductors from growing from the areas they cover, and to allow nitride semiconductors to selectively grow from the exposed areas of their windows. In this specification and the scope of the patent application, it is referred to as a "selective growth" mask. ≪ The ideal relationship between a heterogeneous substrate and a selective growth mask > Figure 3 is a cell diagram showing the crystal structure of a nitride semiconductor. Nitrogen semi-conducting ships are correctly rhombohedral structures, but you can use these six 15 paper sizes to apply Chinese National Standard (CNS) A4 specifications (210X297 mm)

V. Description of the invention (The approximate diagram below is shown. In the method of the present invention, it is best to use a sapphire substrate with a main surface as the heterogeneous substrate 21, and its choice = the mask 13 'is directed from each side to the sapphire A surface. The vertical directions are mutually flat (in other words, 'parallel to the m_〇〇) plane of the -gaseous semiconductor) direction (the < iToo > direction of the gaseous semiconductor) mutually support each other, and are formed by different lines. That is, the blue extension on the main surface side) most of the 1 planes of the siege monitor. Figure 4 of the plan view of the sapphire substrate: 'The sapphire substrate η is based on the sapphire c-plane, and the orientation plane is called (〇RF) For a noodles. The selective growth mask π is ideally constituted by a plurality of individual lines, each of which is perpendicular to the A-plane of the sapphire and extends parallel to each other as shown in FIG. 4. In Fig. 4, only five individual lines are listed to make it easier to understand, but actually, there are more individual lines formed. ~ When the nitride semiconductor is selectively grown on the C-plane of sapphire, the nitride semiconductor will grow more easily in this plane in a direction parallel to the α-plane, and it will be more difficult to grow in the vertical direction of the A-plane. trend. Therefore, when a line mask extending in the vertical direction of the A plane is provided, the I-oxide semiconductors between adjacent line masks are easily connected and grown on the line masks, and can be easily grown as described in lg0c. Crystal 16. At this time, the front face of the nitride semiconductor crystal 15 grown in the lateral direction on the mask 13, i.e., the crystal plane F (see Fig. I), is constituted as the A face of the nitride semiconductor. Similarly, when a sapphire substrate having an A plane as the main plane is used, for example, when the ORF plane is configured as the R plane, a plurality of individual line masks extending parallel to each other are formed in the vertical direction of the R plane. The line mask tends to grow in the width direction, so nitride semiconductor crystals with fewer crystal defects can be grown. Β Good paper size General China National Standard (CNS) M specification (21〇'297 mm) I ¢ ---- --IT ------ ^ (Please read the notes on the back before filling out this page) Printed on the A7 Β7 printed by the Consumers' Cooperatives of the Central Bureau of Standards and Commerce of the Ministry of Economic Affairs 5. Description of the invention () Also in spinel ( On MgAl204), the growth of nitride semiconductors is also anisotropic. For example, when the (111) plane is used as the growth surface of the vaporized semiconductor (the main surface of the spinel), and the 0RF plane is used as the (111) plane. The nitride semiconductor tends to grow easily in a direction parallel to the (1) plane. Therefore, when forming a plurality of parallel individual line masks extending in the vertical direction of the (⑴) plane, adjacent vaporized semiconductor crystals are integrated with each other on the top of the selective growth mask 13 to form nitride semiconductors with few crystal growth defects. Crystals. < Growth of gaseous semiconductor crystals > The nitride semiconductor crystals grown by the present invention can use a gaseous Group 3 element source and a gaseous gas source in order to communicate with any known MOVPE, MDE, HVPE, etc. of the nitride semiconductor growth method. All methods can make it grow. It is more desirable that the nitride semiconductor crystal be grown at MovpE 'in the early stage and then grown at MOVEE4 HVPE. Especially, as described in detail later, nitride semiconductor crystals are initially grown by MOVPE, and then grown by HVPE to be thicker. When growing a nitride semiconductor with MOVPE, it is desirable to adjust the molar ratio of the nitrogen source gas to the Group 3 source gas (nitrogen source / 3 group source molar ratio, hereinafter referred to as the v / m ratio) to 2000 or less. The ideal gas source / 3 family source molar ratio is below 1 800, and the more ideal nitrogen source / 3 family source molar ratio is below 1500. The lower limit of the molar ratio of the nitrogen source / 3 family source is not particularly limited as long as it is above the stoichiometric ratio, but it is preferably 10 or more, more preferably 30 or more, and most preferably 50 or more. When the value of the molar ratio exceeds 2000, a triangle-shaped nitride semiconductor is grown from the window 14, and as a result, the defects will grow along with it. Therefore, fewer crystal defects will stop on the way, and the number of long-term crystal sinks will increase. When the molar ratio of the nitrogen source and the / 3 group source is adjusted below 2000, each crystal 15 grows in each window 丨 4, and the side is roughly dimensional ------------ ^-(Please read the back (Note 4 '' on this page), ιτη printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 17

40G445 A7 B7 Printed by the Consumers ’Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 5. Description of the Invention () Hold the surface perpendicular to the upper surface of the growth mask selection, and grow laterally from the upper surface of the growth mask 13 to the left and right. The same vertical surfaces of the grown adjacent crystals will be in contact on the selective growth mask Π, and these crystals will be integrated into one body. Therefore, on the upper surface of the selective growth mask, crystal defects easily stop halfway. In addition, crystal defects elongated from the window 14 are also easily stopped. Therefore, nitride semiconductor crystals with less crystal sinking can be grown. MOVPE is particularly desirable when performed under reduced pressure of 50 to 400 torr. In MOVPE, the nitrogen source gas is, for example, a hydrogen gas such as ammonia, hydrazine, or the like. The Group 3 source gas is organic aluminum gas or organic indium gas such as trimethylgallium (hereinafter referred to as TMI). HVPE is also used to grow nitride semiconductor crystals. For example, when gallium nitride crystals are used, gaseous hydrogen (HC1) gas is circulated on the gallium metal raw material. On the one hand, < the other gas supply pipe circulates ammonia gas on the support. Combining these .10 gases on 10

GaCl + NH and GaN + HC1 + H2 reactions. In HVPE, the growth of nitride semiconductor crystals is several times faster than that of MOVPE. Therefore, a nitride semiconductor, such as 300 μm, can be grown in a few hours. In the present invention, although the nitride semiconductor crystal is related to the selection of the width of the growth mask ', it is grown at a thickness of 1 μm or more, and it is currently desired to be 5 mm or more, and most preferably a thickness of 10 μm or more. This is to make the nitride semiconductor crystal cover the lower limit of the thickness of the nitride semiconductor crystal thickness on the selective growth mask. If the thickness is less than 1 μm, the grown nitride semiconductor crystal will be difficult to be deposited on the selective growth mask. The trend of lateral growth, therefore, there will be crystallized 18 paper sizes common Chinese National Standard (CNS) A4 specifications (210 × 97mm) ---------- ^ ------ II (please first (Please read the notes on the back and fill in this page again.) Printed by the Ministry of Economic Affairs, Central Bureau of Standards, Bureau of Work and Consumer Cooperatives. 406445 5. Description of invention () tends to have more defects. Under the condition that the nitride semiconductor dry conductor is difficult to grow in the lateral direction ', it is difficult to make the crystal defects 、, 丨, and trap v. Although the upper limit of the crystal thickness of the nitride semiconductor to be grown is JI, ..., and the type is limited, when the crystal is grown by MOVPE, it is preferable to be 70 or less. If it grows thicker than 70, the growth time will be too long, and the surface of the nitride semiconductor crystals will have coarse chains, and the growth mask will tend to be easily decomposed, which is not a good thing. In the present invention, when it is to be grown to a substrate that can support a gaseous semiconductor device, its gaseous semiconductor crystals (for example, Crystal 16, or Crystal Π, Crystal Π 6, Crystal 76) are pure gas. The best way is to marry or push η impurity gallium nitride. In order to grow thicker nitride semiconductor junctions with fewer defects, the initial idea is to grow gaseous semiconductor crystals with MOVPE, and then change to η. On movpe crystals, it is ideal to grow nitride semiconductor crystals. Figures 5A and 511B are sectional views for explaining a method for growing such a thick nitride semiconductor crystal. According to the i-th view or the second view described with reference to FIGS. 1A to 1C, the nitride semiconductor crystal i7 of the same kind is grown on the nitride semiconductor crystal 16 grown by MOVPE i 7. It is grown to a thickness greater than that of the nitride semiconductor crystal 16. When the nitride semiconductor crystal 17 is regrown by the HVPE on the MOVPE junction e16 in this way, there are almost no crystal defects extending in the longitudinal direction, and a nitride semiconductor having very few crystal defects can be grown as a whole 7. The crystal defects of HVPE nitride semiconductor crystals 7 and 7 will be less than the MOVPE nitride semiconductor crystals 16 below it. For example, finally, a vaporized semiconductor crystal substrate 17 with crystal defects of IX lOVcm2 or less in the surface area can be obtained. The crystal defects in the surface area are ideal at 5 xi 〇4 / cm. It is more ideal that it is less than lXlOVcm2, and the ixl03 / cm is described as the first ratio (please read the precautions on the back first) (Fill in this page)

.1T line. 19 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) * ΐ〇ΐ445 A7 B7 V. Description of the invention Most ideal. The "surface area" refers to the surface on the opposite side of the heterogeneous substrate 11 of the nitride semiconducting crystal (the area up to a height of 5 degrees from the growth terminal surface). (TEM) is measured. In the present invention, the crystal defect of the nitride nitride semiconductor crystals grown is the average of the defect density measured by visual inspection of the TEM (ie, good observation of the naked eye on the simplified photo). (The same applies to the following examples.) The thickness of the HVPE vaporized semiconductor semiconductor crystal 17 is thicker than that of the MvvE gas semiconductor crystal 16, and it is preferably more than 10 mm, and more preferably 50 or more. 100 陴 or more is the most ideal. When less than 10 _, the number of crystal defects tends to be difficult to reduce. The upper limit of the thickness is not particularly limited, but it is preferably less than 1 1. Growth to more than i 叩At the above thicknesses, due to the difference in thermal expansion coefficient between the nitride semiconductor and the heterogeneous substrate, the entire wafer is warped, and there is a tendency that it is difficult to uniformly grow HvpE nitride semiconductors. When the semiconductor crystal 16 and / or 17 are grown, it is desirable to dope n-type impurities in the nitride semiconductor, and it is more desirable that the concentration of the n-type impurity is between 16 or 17 in each crystal. Among them, those with doped η-type impurities with a slope are more ideal. The concentration gradient can be continuous or step-shaped. Especially in each of crystals 16 and 17, the concentration gradient of η-type impurities is It is desirable that the n-type impurity concentration becomes smaller as it leaves the heterogeneous substrate 换. In other words, the closer the n-type impurity in the crystal 16 is to the heterogeneous substrate 11, the higher its doping concentration. Similarly, in the crystal 1 7 The closer the n-type impurity in the substrate to the heterogeneous substrate 1, the higher the doping concentration is. In this way, the closer the crystals are to the growth surface (the main surface), the smaller the n-type impurity concentration will be in the future. After making the component, set the η side power to 20. This paper size is applicable to the Chinese National Standard (CNS) M specification (210X297 mm) ------ (Please read the precautions on the back before filling in this f). .

5T line 406445

、 Explanation of the invention (For example, removing the heterogeneous substrate 11, the bottom layer 12, and the growth mask 13 when printing, such as removing the heterogeneous substrate 11, the bottom layer 12, and the growth mask 13 in order to expose the nitride semiconductor 16 ′ or the nitride semiconductor crystal substrate 16 When the 'is removed to expose the nitride semiconductor substrate 17, the surface regions of the nitride semiconductor crystals 16 and 17 doped with high-concentration η impurities can be exposed on the back side. Therefore, by using the exposed surface as the η-side electrode formation surface, Reduce the forward voltage (Vf) of the device and increase the output. In addition, from the device structure side grown on the nitride semiconductor crystal substrate, the high-concentration n-type can be doped when the f electrode is provided on the etching surface Nitride semiconductor crystals of impurities or 17 are used as the n-electrode formation layer. In the present invention, n-type impurities doped in the nitride semiconductor crystals are made of silicon (Si), iron (Ge), tin (Sn), and sulfur ( S) and other Group 4 elements, with Shi Xi and / or tin as the imagination. These n-type impurities can be used as hydrides or gaseous organometallic compounds in the growth of argon semiconductors. N-type impurities are based on 5Xl 〇iVCm3 ~ 5x102i / cm3 is ideally doped. When less than 5x1016 / Cm3, the carrier concentration of nitride semiconductor crystal 16 or 17 is insufficient, and its resistivity will increase. In addition, when the concentration of n-type impurities exceeds 5 X 1 0 / cm, the impurity concentration is too high, crystallinity will deteriorate, and crystal defects tend to increase. Η-type impurities are in the range of 1 x 10 "/ cm3 to 1 x 10 2 W. Doping within the range is the most ideal. In addition, in the present invention, the conversion from M0 VPE to HvPE can also be carried to the vaporizer semi-conductor at MOVPEit. Before (for example, in the state of FIG. B), the nitride semiconductor crystal 15 has been grown laterally on the upper surface of the mask 13 with MovpE, but before the adjacent nitride semiconductor crystals 15 are integrated with each other, The HVPE nitride semiconductor crystal n can be grown. As shown in the fifth circle A, the nitride semiconductor crystals 16 and 17 are grown IIIIII Order I n (Please read the precautions on the back first and recommend this page) 21 406445 at _B7F Description of the invention 51 After that, as will be described later, the structure shown in FIG. 5A can be used as an element substrate, and a desired nitride semiconductor element structure can be formed thereon. Alternatively, the structure of the fifth country A can be obtained from a heterogeneous substrate 11 On the back surface, at least the heterogeneous substrate 11, the bottom layer 12 and the selective growth masks 13 a to 13 e are polished and removed in a direction perpendicular to the main surface of the heterogeneous substrate 11 to obtain a nitride semiconductor crystal 16 and an argon semiconductor crystal 17. Double-layered nitride semiconductor substrate. If the semiconductor semi-conductor crystal 16 is also removed, as shown in the fifth country B, it can be composed of H VPE nitride semiconductor crystal} 7 Bulk nitride semiconductor semiconductor substrate. As can be seen from the above description, the HVPE nitride semi-conductor substrate has the characteristic that the crystal defects in the surface area are below 1 X 105 / cm2. The HVPE nitride semiconductor substrate has a doped η-type impurity, the η-type impurity has a concentration gradient in the nitride semiconductor substrate, and the closer to the main surface (that is, the more it leaves the heterogeneous substrate U, the closer it is to Growth terminal surface), the smaller the n-type impurity concentration of any one of three or more features. From another point of view, the substrate thus obtained is characterized by having first and second major surfaces' doped with n-type impurities, and those impurities have a gradient in concentration on the substrate. In addition, in the present invention, before a substantial portion of a nitride semiconductor crystal (for example, a nitride semiconductor crystal 16 or the like is grown on a mask to crystallize it), it may be first grown by a nitride. Buffer layer composed of semiconductor ^ The buffer layer may be composed of a nitride semiconductor such as aluminum nitride (A1N), gallium nitride (GaN), aluminum-gallium nitride (AlGaN), indium-gallium nitride (InGaN), and the bottom layer 12 Similarly, at a low temperature of less than 900 ° C, a thickness of tens of angstroms to hundreds of angstroms is grown. After the low-temperature buffer layer is grown, the substantially semi-conductive blade semiconductor crystal is grown. It also belongs to the scope of the present invention. This buffer layer is to relax the heterogeneous substrate and nitride semiconductors grown in the future. (Please read the precautions on the back before filling out this page). Binding and binding. —II 1- I -II 111 ___ 22i paper Guan Xu (21〇X29T ^ y 406445 V. Description of the invention () A7 B7 Printed by the Consumers 'Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China :: The appearance of the mismatch is caused by the appearance of' So, because of the shape of the nitride semiconducting Zhao. The method, or the type of the substrate, may be omitted. The second method of making crystal defects / nitride semiconductor crystals will be described with reference to the sixth circle A to 6 帛 c. First, as in the sixth As shown in Figure A, the surface of a nitride semiconductor crystal grown in accordance with the above-mentioned detailed description of the second or second aspect of the present invention is polished as necessary to form a flat surface, and then on the surface of the vaporized semiconductor crystal 16 'The formation of the second selective growth mask 113 that partially exposes the surface of the vaporized semiconductor crystal 16 and has a large number of windows α. The description of the first selective growth mask 13 (material, shape, width, thickness, window shape) 'Visibility and dissimilar substrates Relationship), unless otherwise specified, all of them can be applied to the second selection growth mask 113. The second selection growth mask 113 is usually formed at a position staggered from the formation position of the first selection growth mask 13. That is, The second selective growth mask 113 is formed at a crystal defect that can be generated at the interface between the support body 10 and the nitride semiconductor crystal 16 through the windows 14a to Hf of the first selective growth mask 13 so as to be stretched to the surface. A portion of the nitride semiconductor crystal 16 on the surface is covered, and the surface of the nitride semiconductor crystal 16 is selectively exposed. On the substrate, as in FIG. 6A, the growth mask 113 and the i-th are selected. The selective growth mask is also composed of individual lines 3a to 113f, and each line is located at a position covered by the surface area of the nitride semiconductor crystal 16 corresponding to the windows 14a to 14f of the optional growth mask 13, The windows ii4a to 114e are positioned in a region corresponding to the approximate central area of the first line masks 13a to 13e. In this way, the second selection growth mask 113 is formed in the window corresponding to the first selection growth mask 13. 14 of Position, you can apply the Chinese national standard (CNS) A4 size (210X297 mm) on this paper size 2 23 (Please read the precautions on the back before filling this page). Γ

L 5 406 445 A7 B7, invention description (Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed selection growth mask U3 resists the penetration of crystal defects on crystal 16. It is ideal to make the second selection growth mask 13 (by The hinge surface area of the nitride semiconductor crystal 16 covered by the second selection growth mask 113 is larger than the windows σ 14a to 14f (the hafnium semiconductor crystals 16 exposed by the windows ⑷ to Mf) of the i selection growth mask 13. The total surface area of the part is large. Specifically, when the shape of the growth mask 113 is selected to be formed by a dot line, etc., the surface area of the unit dot and the width of the unit line are made larger than the window. Nitride semiconductor with fewer growth defects on the crystal 16 ^ Next, the same method as that used to grow the nitride semiconductor crystal 16 'is grown so that a nitride semiconductor junction of the same type as the nitride semiconductor 16 (either pure or doped n-type In the case of impurity gallium nitride (GaN), as shown in FIG. 6B: the same as that described with reference to FIG. 1B for the crystal 15 'will grow nitride conductor crystal 11 5' to the end 'in the second selection growth mask ii 3 on, The ortho-nitride semiconductor crystal 丨 15 is connected between them, and a synthesis can be obtained: the ship ’s nitride semiconductor crystal 116. At the time of weeping, the second nitride semiconductor crystal grown on the i-th vapor semiconductor crystal 16 115, because it is a nitride semiconductor of the same type, and it is grown on a semiconducting semiconductor crystal with a small number of crystal defects. Therefore, it is not easy to generate crystal defects caused by lattice mismatch, and it will transfer crystal defects. It is also reduced, so that a second nitride semiconductor crystal 116 having excellent crystallinity can be obtained. By using the nitride semiconductor semiconducting hafnium crystal 1 丨 6 as a growth substrate for element structure, nitrogen having very good crystallinity can be obtained. Of course, the yellow semiconductor 116 may be doped with a ^ -type impurity in the same manner as the nitride semiconductor 16 or 17 (refer to C ', FIG. 5A). Also, FIGS. 6A to 6 The formation of the second long mask and the growth of the next nitride semiconductor crystal illustrated in Figure C are half as long as the second one. (Please read the precautions on the back before filling out this page.) , Π line 24 This paper scale applies to China's National Standards (CNS) A4 specification (210X297). Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 406445 Α7 _ Β7 V. Description of the invention () Repeatedly performed. When a defective nitride semiconductor is crystallized, a new mask can be formed on the part and a new nitride semiconductor can be grown on the mask. The principle of the nitride semiconductor growth method according to the third aspect of the present invention will be described below. A method for growing a nitride semiconductor according to a third aspect of the present invention is characterized in that after a nitride semiconductor is grown on a support of the present invention, the nitride semiconductor is used as a so-called seed crystal, and a new nitride semiconductor is grown in the longitudinal direction. Suppressed, essentially growing only in the lateral direction 'and then causing it to grow longitudinally and laterally. In the present invention, the inhibition of the growth of nitride semiconductors in the longitudinal direction is at least to prevent the growth of nitride semiconductors from proceeding in the longitudinal direction, and to cause the nitride semiconductors to grow in the lateral direction or to expose the initially grown nitride semiconductors to the vertical surfaces. This can be achieved by growing the new nitride semiconductor light from the exposed surface. In this way, the nitride semiconducting impurity whose growth direction is suppressed starts to grow from the longitudinal direction to the lateral direction. When the growth is continued, in addition to the lateral growth, the longitudinal direction starts to grow again. In this way, crystals of nitride semiconductors having fewer crystal defects can be obtained. This method of growing a nitride semiconductor body that controls the growth direction of a nitride semiconductor in accordance with the third aspect of the present invention will be specifically described with reference to Figs. 7A to 7D. As shown in FIG. 7A, a nitride semiconductor layer 71 is formed on a support body 10 made of a heterogeneous substrate 11 with or without a bottom layer 12 formed thereon. It is ideal on substantially the entire surface, and the support body 10 includes a heterogeneous substrate II and a bottom layer 12 as described above. Nitride semiconductor 71 is made of (pure) gallium nitride (GaN) without impurities. 25 This paper size is applicable to China's national standard FcNS) A4 specification (210x " T97 mm) Binding I line (Please read the back Note: Please fill in this page again.) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperatives ^ vi ο 4 4 5 V. Description of the invention (... The above-mentioned formation of GaN doped with n-type impurities is particularly ideal. The imaginary layer 71 is formed at a high temperature, specifically 900 ° C to 1100 ° C, at a temperature of 950C to 1050C to grow on the support. The nitride semiconductor layer 71 _ The thickness of the exposed portion of the recessed portion (this item is also described in detail below) after the formation of the growth control mask is not particularly limited. However, the thickness of the nitride semiconductor layer 71 formed from the side surface of the recessed portion is required to have a certain thickness. Above 100 angstroms, it is preferably about i to about 10 μm, and more preferably about 1 to about 5 μm. Next, as shown in FIG. 7B, the nitride semiconductor layer 71 formed on the support 10 , Many recesses are formed (6 recesses can be seen in FIG. 7B) The first nitride semiconductor layer 71 is selectively exposed on the side surface of each of the recessed portions 72. Then, on the upper surface of the nitride semiconductor layer 7, only a plurality of recessed portions are collectively referred to as the recessed portions 72). The first growth control masks indicated by symbols 73a to 73g and the second growth control masks indicated by symbols 74a to 74f are formed on the bottom surfaces of the recesses 72a to 72f. The i-th growth control masks 73a to 73g also have This is collectively referred to as the i-th growth control mask or mask 7j '. The second growth-control masks 74a to 74f may be collectively referred to as the second growth-control mask or mask 74. The first and second growth control The masks 73 and 74 can be formed using the same materials and similar methods as the selective growth masks described above in relation to the first and second viewpoints. Most of the recesses 72a to 72f, if they are to be on the side, Any shape of the nitride semiconductor layer 71 can be selectively exposed. For example, the nitride semiconductor layer 71 can be formed in an individual cylindrical shape, a square cylindrical shape, or a groove shape. The bottom surface of each of the recessed portions 72 is formed on the upper surface of the support 10. The surface is ideally a substantially parallel surface. Each of the recesses 72 of the compound semiconductor layer 71 can be formed on the way to the nitride semiconductor layer 71 or to the surface of the support body 10, and this paper standard uses the Chinese National Standard (CNS) A4 specification (2 丨 〇 &gt); & 297

V. Description of the invention () The consumer cooperative of the Central Economic and Technical Bureau of the Ministry of Economic Affairs can be printed to the depth of the support body depending on the situation. Although the depth of the recess 72 will reach the thickness of the nitride semiconductor layer 71 or the growth control mask. The thickness of the mold 74 depends on the thickness, etc. In short, as long as the second growth control mask 74 to be formed on the bottom surface of the recess is not exposed to the heterogeneous substrate u, and the second growth control mask 74 can be formed sufficiently The thickness of the nitride semiconductor layer 72 does not hinder the growth of a new nitride semiconductor that grows laterally from the side of the nitride semiconductor layer 72 facing the side of the recess 72. The depth of formation of each recess 72 is preferably not to expose the heterogeneous substrate 11, and the depth of formation is preferably halfway through the thickness direction of the nitride semiconductor layer. For example, when the recessed portion 72 is formed to the depth where the heterogeneous substrate U is exposed, when the second growth control mask 74 is formed, it is difficult to form the second growth control mask 74 near the corners of the bottom surface of the recessed portion 72. When the control mask fails to completely cover the surface of the heterogeneous substrate η, a new nitride semiconductor is grown from the heterogeneous substrate 11 and there is a possibility that a crystal defect is generated therefrom. The recesses 72 may have different depths, but generally the depths of the recesses 72 are all the same. When the recessed portion 72 is to be provided, any method may be used as long as the nitride semiconductor layer 71 can be partially removed, and for example, etching processing, cutting, and the like can be used. The recessed portion 72 'formed by parallel grooves having a rectangular cross-section or the recessed portion 72 formed by a grid structure can be easily formed during cutting. When forming the recessed portion 72 in the nitride semiconductor layer 71 by the engraving method, a mask pattern of various shapes in a photolithography technique is used, and a resist pattern is used as a photomask in a line shape or a grid shape. It is formed on the nitride semiconductor layer 71 and can be formed after etching. The nitride semiconductor layer 71 is etched by methods such as wet etching and dry etching. In order to form a smooth surface, dry etching is preferably used. Dry etching includes, for example, reactive ion etching (hereinafter referred to as RIE) and reactivity. Ion Beam Etching (hereinafter referred to as RIBE), i --- II IIII ^ n wire (Please read the precautions on the back before filling this page} 27

406445 V. Description of the invention () Electron cyclotron etching (hereinafter referred to as ECR), and electron beam etching (hereinafter referred to as ibe), etc., any method can be selected by the appropriate etching gas, nitride semiconductor etched to form欲 之 沉 部 72。 Desire 72. For example, a nitride semiconductor etching method described in Japanese Patent Application Laid-Open No. 8-1 78G3 previously published by the applicant can be used. In addition, when the recessed portion 72 is formed by an etching method, the side surface of the formed recessed portion 72 may be substantially perpendicular to the heterogeneous substrate, or may be in an upslope shape or inversely abutment shape as shown in FIG. 7B. The method of forming the 73 and the second mask 74 differs by how much the recess 72 is formed by the etching method or the cutting method. When the recess 72 is to be formed by etching, the first! After a mask material layer is formed on the nitride semiconductor layer 71, a resist film is formed thereon, a predetermined pattern is copied, exposed, developed, and a first mask 73 is formed. Concavity 72. Next, a growth control mask material layer is formed on the nitride semiconductor 71 having the i-th mask 73 and the recessed portion 72 formed, that is, the bottom surface, side pairs, etc. of the mask 73 and the recessed portion 72, for example, fluorinated The dry etching of carbon (CF.4) and oxygen (ο) gas selectively etches the mask material on the side of the recess 72 to form a second mask 74. When formed in this manner, for example, in FIG. 7B, The first mask 73 is shown in the figure as a single layer. In fact, it is a two-layer structure in which a mask material layer is further formed on the first mask 73. Of course, the second mask 74 may be formed before the second mask 74 is formed. After the second mask 73 is removed, the first mask 73 and the second mask 74 are each formed on the portion formed by the first mask 73 and the bottom surface of the recess 72 by the same method. The recess 7 is formed by cutting. At this time, the nitride semiconductor layer 71 is removed from above with a dicing saw, and after forming the recessed portion 72, a growth control mask is formed on the entire surface of the nitride semiconductor layer 71 including the recessed portion 72 as described above .-------- -^: ------ π ------ ^ (Please read the notes on the back before filling this page) Printed by the Industrial Standards and Consumer Cooperatives of the Ministry of Economic Affairs

406445 A7 B7 V. Description of the invention () ~ '-, the material layer, with the drying of carbon fluoride (CF4) and oxygen (〇2) gas vessels, only the growth control mask material layer on the side of the recess 72 Etching is performed to form the first and second growth control masks 73 and 74 at the same time. Regarding the thickness, both the i-th growth control mask 73 and the second growth-control mask 74 may have different thicknesses, as described later, which do not hinder the growth of nitride crystals. For example, the second growth control mask 74, especially when the underlayer 12 is not formed on the heterogeneous substrate 11, has a thickness sufficient to prevent the heterogeneous substrate u on the bottom surface of the recess 72 from being exposed, and Z is formed so as to be subjected to heat. Ying Le will not produce a sufficient thickness of pinholes in the cymbals. Of course, it should not be thick enough to hinder the growth of the semiconducting Zhao crystal of the nitride semiconductor 71 part exposed from the side of the recess. When pinholes are generated in the second mask 74, the nitride semiconductor may grow from the pinholes in the longitudinal direction, which may be a cause of crystal defects later. For example, if the first growth control mask 73 is formed relatively thin, the barrier height (the height of the first growth control mask 73) to be crossed by the nitride semiconductor is low, and it is easy to pass it. Horizontal growth. The formation of such a growth control mask should be clear to the operator. To form it in this way, the formation of the mask can be divided into two steps. It is desirable that the first growth control mask 73 has the same relationship with the heterogeneous substrate 11 as the first growth control mask 73 for the heterogeneous substrate 11 described above. Therefore, all of the items described under "Relationship between heterogeneous substrates and selective growth masks" are applicable to the i-th growth control mask, that is, the first growth control mask 73 has a substantially short cross-section. Most of the individual lines are ideal. At this time, the respective lines are formed on the sapphire A plane and parallel to each other in the vertical direction of the sapphire R plane, or on the spinel (111) plane, the vertical directions to the spinel (110) plane are Parallel extension 29 This paper scale is applicable to Chinese National Standard (CNS) A4 specification (2i0x297) A7 B7 406445 V. Description of the invention (formed ideally. Therefore, each recess 72 is controlled by the linear growth The top φ ′ of each wall defined by the plurality of individual grooves formed by the mask 73 extending in the same direction between adjacent grooves has a plane shape that is the same as the plane shape of each linear growth control mask 73 The width of each of the linear growth control masks 73 (equivalent to the width Ws of the first selected growth mask) is preferably i to 20_, and more preferably 10 to 20 ，, and the interval is It is more preferable to use i to 20, and 2 to 5 mm. In this way, the recess 72, the i-th and the second growth control cover 73 and 74 are formed, as shown in 7 @ C, so that the The vapor phase growth method described in the first and second aspects makes the nitride semiconductor 75 The exposed side surface of the semiconductor layer 71 grows. As explained above with reference to FIG. 7B, the nitride semiconductor layer 71 is on its upper surface (ie, the top surface of the wall between the recessed portions) in addition to the side surface of the recessed portion 72 formed therein, and The bottom surface of the recess 72 is covered by the growth control mask 73 and 74. The nitride semiconductor layer 7 丨 is exposed only on the side of the recess 72. Therefore, a nitride semiconductor grown in a vapor phase will only pass from the nitride semiconductor layer. The selective exposed surface of 71 grows. That is, the nitride semiconductor 75 initially starts to grow laterally from the exposed side of the nitride semiconductor layer 71. Then, as the nitride semiconductor 75 continues to grow, in addition to the lateral growth, the nitride semiconductor 75 also grows vertically. It starts to grow, and after reaching the top of the recess 72, it will grow on the ι growth control mask 73 on both sides of the recess to the left and right, and the adjacent nitride semiconducting Zhao crystal 75 will be in between as described above. According to the viewpoint and the second viewpoint, they are integrated with each other to form an integrated nitride semiconductor crystal 76 as shown in FIG. 7D. Thus, in the initial stage of growth, the nitrogen whose growth direction is controlled Compound semiconductor crystal 76, if it grows very thick, its crystal ---------- ^ ------ 1T ------ Φ (Please read the precautions on the back before filling (This page) Du Yinzhong, Shellfish Consumer Cooperation, Central Bureau of Standards, Ministry of Economic Affairs

Printed side of the Work and Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs 445 a?--B7 V. Description of the invention () Defects are still very few, and have very good crystalline characteristics. The gaseous semiconductor 75 to be grown is an ideal semiconductor semiconducting semiconductor or a dry conductive semiconductor of the same kind as the nitride semiconductor layer 71. Dry conductive® is preferred, especially for pure or doped n-type impurity gallium nitride (GaN). . When the n-type impurity is to be doped during the growth of the gaseous semiconductor crystal 76, as described above, a gradient may be provided in its concentration. Also, in the third point, a second growth control mask is formed. The mold 74 is preferable, but when the growth control mask 74 is not formed, a gaseous semiconductor crystal having excellent growth m can be formed. In this case, regarding the formation of the first growth control mask 73 and the recessed portion 72, the formation method of the 丨 selected growth mask 13 and the 丨 window 14 described in the first and second viewpoints can be used to Instead of the formation method of the} th growth control mask 73 and the recessed portion 72, the descriptions of the 丨 selected growth mask 13 and the first window 14 described in the inner gates 丨 and 2 are all applied to the 丨 growth control On the mask 73 and the recess 72. In this case, the recessed portion 72 should have a depth that does not expose the surface of the support body 10. From the above description, it can be seen that the nitride semiconductor crystals 16, 17, 116, and 76 grown by the method of the present invention (hereinafter, these crystal substrates are collectively referred to as the substrate 1000) have very few defects and are suitable for being used thereon. A substrate for supporting a predetermined nitride semiconductor device structure. The characteristics of the nitride semiconductor substrate of the present invention, especially the nitride semiconductor substrate grown by the methods related to the first to third aspects, can be described as having a first main surface and a second main surface, which are close to There are relatively few crystal defects in the area of the first main surface (that is, the surface to support the element structure, or the growth termination surface), and the number of crystal defects near the second main area is relatively large. The second is mainly the main surface closer to the heterogeneous substrate U than the first. The gas _ 31 This paper size applies to Chinese National Standard (CNS) A4 ^ grid (210X297 male thin) '' ---- ^ ------ ^ ------ ^ (Please read the note on the back first Matters need to be refilled ^ This page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 406445 V. Description of Invention Since the surface area of the second main near house can be configured as an n + area, the n-side electrode of a nitride semiconductor device can be provided in this area to reduce the voltage facing the device. ^ The nitride semiconductor substrate of the present invention can be described as having a region (second region) with relatively few crystal defects and a region (second region) with relatively large crystal defects when viewed from the first principal surface. The state of defect unevenness is formed. The first region is a region corresponding to the masks 13 and 73, and the first region is a region corresponding to the window 14 and the recessed portion 72. The nitride semiconductor device of the present invention is a nitrogen device of the present invention. The compound substrate supports its component constructor. At this time, The nitride semiconductor substrate of the invention can remove the support body 10 and the mask (13, U3, 73, 74, etc.), support the element structure in an independent state, and retain the original state of the support body and the mask. "Support element structure" Also, the nitride half body of the present invention can be made into an independent state in advance, and then an element structure is formed thereon, and the support body 10 and the original state of the mask can be retained to form an element structure thereon. After that, the support body 10 and the mask are removed to become independent. The independent nitride semiconductor substrate of the present invention needs to have a thickness of 70 or more, and a thickness of 100 μΐη or more is desirable, and a thickness of 300 or more is more desirable. When the thickness is more than 70 mid, the nitride semiconductor substrate is not easily broken and is easy to handle. The upper limit of the thickness is not particularly limited, but it is preferably 1 μη or less. In addition, when a heterogeneous substrate is provided It is desirable that the thickness of the gaseous half-substrate of the present invention is 1 to 50 μm, and the thickness lies in this range. The whole wafer is caused by the difference in thermal expansion coefficient between the substrate 11 and the heterogeneous substrate 11

2 The guide is also in the state < The reason is to use conductors to tune ---------- sai ----- 1T ------ line · (Please read the precautions on the back before filling (This page) 32 This paper size applies to China National Standards (CNS) A4 specifications (210 × 297 mm) 406445 A7 B7 V. Description of the invention () ~~ Will be reduced. a * The element structure supported by the vaporized semiconductor substrate of the present invention may include a light-emitting diode (hereinafter referred to as "ca") element structure as long as it can exhibit a predetermined element function ', and a laser diode ( Hereinafter referred to as ld) ... cattle structures, etc. 'but are not limited by these structures. The element structure of the present invention is one that can include at least an n-type or p-type bis-type semiconductor. For example, the n-type nitride semiconductor layer having an n-type nitride semiconductor layer having a superlattice structure, and the n-type nitride semiconductor system having the element structure formed on the n-type layer of the superlattice structure, etc. . For example, the rhenium element and the LD element of the present invention basically have an active layer and two cladding layers on both sides. In addition, for other structures that form a nitride semiconductor element, for example, an electrode and a suitable shape can be used for the shape of the electrode and the element. In the present invention, the p-side and the n-side are, for example, opposite sides of the active layer, the P-side is one side of a nitride semiconductor layer containing a dopable p-type impurity, and the n-side is a side containing a dopable n-type One side of the nitride semiconductor layer of impurities. FIG. 8A is a schematic cross-sectional view of the structure of the LED element on the nitride semiconductor substrate 1000 of the present invention. The 8th circle B is a plan view. As can be seen from FIG. 8B, the LED element as a whole is roughly Become a cuboid. As shown in FIG. 8A, a nitride semiconductor doped with an n-type impurity such as (Si), such as n-type gallium oxide (GaN), is formed on the nitride semiconductor substrate 1000. Buffer layer 8 ^ The buffer layer 8 丨 is a nitride semiconductor crystal that is usually grown at a high temperature of 900 C or higher. The high-temperature buffer layer 81 is for reducing the lattice between the substrate and the nitride semiconductors to be formed thereon. Does not match the low-temperature buffer layer that is grown at low temperature (for example, the 33rd paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --------- installation ------ ir ------ ^ (please read the notes on the back to fill in the original text) Printed by the Consumers Cooperative of the Central Bureau of the Ministry of Economic Affairs A7 B7 406445 V. Description of the invention () 1 Picture A ~ 1 Picture C The buffer in Tu 1.2) is different, but acts as a cladding. When the LED element is manufactured, it is preferable that the n-type buffer layer 81 is formed to a thickness of 20 angstroms or more. The buffer layer 81 is preferably a deformed superlattice structure composed of alternating layers of first and second nitride semiconductor layers having different components from each other. The buffer layer with a superlattice structure can be used as a carrier blocking layer to provide an η-side cladding layer with excellent crystallinity. The buffer layer of such a superlattice structure can be composed of, for example, an aluminum-containing semiconductor semiconductor doped with n-type impurities, especially a thin layer of gallium gas compound (Al GaN), and gallium nitride not doped with impurities. (GaN) layers are formed by alternately stacking. The buffer layer with a superlattice structure preferably has a thickness of 50 angstroms or more. An active layer 82 is formed on the buffer layer 81. The active layer 82 is preferably a quantum well structure including a well layer composed of indium-gallium nitride (InGaN). The quantum well structure is composed of both a single quantum well (SQW) structure and a multi-weighted sub-well (MQW) structure. The active layer of a multiple quantum well structure can be, for example, alternately stacked first and second indium-gallium nitride (InGaN) thin layers with different compositions, or an indium-indium nitride (InGaN) thin layer and gallium nitride. (GaN) thin layers are alternately stacked to form them. When the active layer 82 is to adopt a quantum well structure, n or p-type impurities may be added to either or both of the well layer and the barrier layer, and impurities may not be added. When the active layer 82 does not have a quantum well structure, n-type and / or p-type impurities are doped into the active layer. On the active layer 82, a p-side cladding layer 83 is formed as a p-type nitride doped with a p-type impurity, for example, magnesium (Mg). The p-side cladding layer 83 is preferably a nitride semiconductor containing aluminum, and particularly preferably an aluminum-gallium nitride (A1GaN). On the P-side cladding layer 83, a doped p-type impurity is formed, for example, magnesium (Mg) 34

Sheet paper Newcastle Financial Services (CNS) A4 ^ (21〇X297 ^ F ---------- ^ ---- ^ --- ΐτ ------ & (Please first Please read the notes on the back of the page and fill in this page again.) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A7, B7, 406445. V. Description of the invention (The p-type nitride semiconductor p-type contact layer 84 serves as the p-side contact layer. The layer 84 is particularly preferably formed of p-type gallium vaporized (GaN). A transparent p-electrode 85 is provided on substantially the entire surface of the P-side contact layer 84, and a disk-shaped soldering base is provided at a substantially central portion thereof. 86. As shown in FIG. 8A, the p-side contact layer 84, the p-side cladding layer 83, the active layer 84, and the buffer layer 81 are all etched to expose their sides, and the etch processing is made into the surface of the substrate 1000 ' "Cut line" is set. In this way, when the cutting line is set by etching, the impact on the pn junction surface can be reduced when cutting each wafer in the future, and each LED element with higher reliability can be obtained and the yield can be improved. The "cutting line" is preferably formed in a portion of the window 14 corresponding to the first selective growth mask 13. Because the "cutting line" is provided, the After removing the sapphire substrate and selecting a growth mask, it is possible to clearly discriminate the wafer cutting position in the area with a large number of crystal defects and the area with few crystal defects. As described above, the argon semiconductor substrate i 000 If n-type impurities are doped in the middle, the n-side electrode 87 can be provided on the entire surface of the back surface of the substrate 1000. Fig. 9 is a view showing that the nitride semiconductor substrate of the present invention is still supported by the bottom layer 10; 8A and 8B are schematic cross-sectional views of LED elements having similar structures to the LED elements in Fig. 8. In the LED element in Fig. 9, the P-side contact layer 84, the p-side cladding layer 83, and the active layer 85 are all etched. The side surface is exposed, and the etching process is deep to the η-side cladding layer 81, while a part of the η-side cladding layer 81 is retained. On the surface of the reserved η-side cladding layer 81, an η-side electrode 88 is provided. FIG. 10 It is a schematic cross-section of a laser diode (LD) structure provided on a nitride semiconductor substrate 1000 of the present invention. On the nitride semiconductor substrate 1000, an argon semiconductor 35 is formed. This paper is applicable to China National Standard (CNS) Α4 Specification (210X297 mm) (Please Read the notes on the back before filling this page) • 岽--* Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs A7 B7 as 406445 V. Description of the invention (The buffer layer 211 is created. The buffer layer 211 is based on A nitride semiconducting monocrystalline layer grown at a high temperature above 900t, which is a low-temperature buffer layer grown at a low temperature in order to alleviate the lattice mismatch between the substrate and the nitride semiconductor grown thereon. (For example, the buffer layer 12 in Figures A to 1 圏 c) is different. When manufacturing an LD device, the thickness of the buffer layer 211 must be 100 angstroms or less. More preferably, it is 70 angstroms or less. It is preferably 50 angstroms or less, and the first and second nitride semiconductor layers which are different or different from each other are alternately stacked, and the structure is preferably a deformed superlattice structure. When it is made into a deformed superlattice structure, its crystallinity is improved, and a high-speed out-of-zero element can be obtained. The buffer layer 211 may be omitted. A crack prevention layer 212 made of a nitride semiconductor is formed on the buffer layer 211. If the seam prevention layer 212 is formed of indium-type nitride semiconductor containing indium, it is preferably formed of indium gallium nitride (InGaN). In the nitride semiconductor containing aluminum to be formed later, it is more effective to prevent the invasion of cracks. The crack prevention layer 212 is preferably formed by inxGa | χN (0 < χ < 〇5). The formation thickness of the crack prevention layer 212 should be 100 angstroms or less, and ideally 0.5 or less. When it is thinner than 100 angstroms, it is difficult to prevent cracks. When it is thicker than 0.05 angstroms, the crystal itself tends to become black. The crack prevention layer 2 丨 2 may be omitted. On the crack prevention layer 212, an n-side cladding layer 213 made of an n-type nitride semiconductor is formed. The n-side cladding layer 213 has a dual function of a carrier blocking layer and a light blocking layer. The n-side cladding layer 213 is preferably a superlattice structure in which first and second nitride semiconductor layers having mutually different band gap energies are sequentially stacked. This superlattice structure is preferably a nitride semiconductor containing aluminum, and more preferably a semiconductor containing 18-gallium nitride (A1GaN). At this time, more impurities are added to any of the first layer and the second layer for so-called modulation doping. For 36 paper sizes, the Chinese National Standard (CNS) .. A4 specification (210X297 mm) is applied- -II II installed I Ί II i III line (please read the notes on the back before filling out this page) Central Standards of the Ministry of Economy 扃 Printed by the Consumer Cooperatives of the Ministry of Economic Affairs Central Printed by the Central Bureau of Standards of the Ministry of Economy 406445 Α? _; Β7 Five 'invention description () can reduce the critical value of LD yuan. For example, the n-type cladding layer 213 of such a superlattice structure may be made of n-type impurities, such as a thin layer of aluminum-gallium nitride (AlGaN) and a thin layer of pure gallium nitride (GaN) doped with silicon (si). Alternately stacked to form it. The superlattice structure provides a carrier seal layer with good crack-free crystallinity. The thickness of the η-side cladding layer 213 is preferably 100 Angstroms or more and 2 Angstroms or less, and is preferably 500 Angstroms or more, and more preferably 1 Angstrom or less. On the n-side cladding layer 213, an n-side light guide layer 2 1 4 made of a nitride semiconductor is formed. The n-side light guide layer 2 14 functions as a guide layer for light from the active layer 21 5 described below. In the case of gallium nitride (GaN) or indium-gallium nitride (InGaN), it is desirable that the thickness of the 11-side light guide layer 214 should be 100 angstroms to 5 μm, and 2,000 angstroms to 1 μm. As ideal. ^ The side light-guiding layer 214 is generally an n-type impurity doped with silicon (Si), germanium (ge), or the like as the n-type conductive type, but such impurities may not be doped. The n-side light guide layer 214 may be a superlattice constructor. The n-side light guide layer 2 14 of such a superlattice structure may include, for example, a first layer made of a hafnium nitride semiconductor such as gallium nitride (GaN), and a second nitride different from the first nitride semiconductor. Semiconductors such as indium-gallium nitride (InGaN) are formed by alternately stacking second layers. In this case, "n-type impurities may be doped in at least one of the first layer and the second layer", or do not need to be doped. The magnitude of the bandgap energy in the present invention is based on the layer with a larger bandgap energy in the superlattice structure, and the active layer in the quantum well structure is based on the well layer. On the n-side light guide layer 214, an active layer 215 made of a nitride semiconductor is formed. The active layer 2 and 5 are made of a nitride semiconductor containing indium (preferably indium-gallium nitride, InGaN or indium-aluminum nitride, 1ηA1N), and a quantum well structure with a well layer is particularly preferable. This quantum well structure 37 paper size is applicable to China National Standard (CNS) Α4 size (210x297 male thin) --------- ¾-- (Please read the precautions on the back before filling this page) Order Line • i Ο 6 4 4 5 Α7 Β7 Printed by the Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 5. Description of the invention () The structure is constructed by a single quantum well (SQW), or a multiple quantum with a well layer and a barrier layer Wells (MQW) can be constructed. Constructors with multiple quantum wells are ideal. For example, 'multiple quantum well structures can be constructed by alternately stacking indium-gallium vapor (InGaN) semiconductors with different compositions, or they can be constructed by alternately stacking gallium nitride (GaN) and indium-gallium nitride. The active layer may be doped with impurities in the well layer and / or the barrier layer, or may not be doped with impurities. The active layer with pure mass sub-well structure is ideal. At this time, the well layer can be replaced with indium nitride nitride (InAIN) instead of indium-gallium nitride (InGaN). On the active layer 2 1 5, a band-side energy having a larger band gap energy than the P-side light guide layer 2 1 7 to be described later is formed. The specific active layer 2 1 5 (well layer in a quantum well structure) is larger than p.侧 盖层 216。 Side cover layer 216. The formation thickness of the p-side cap layer 216 is preferably 0.1 angstrom or less, more preferably 500 angstrom or less, and most preferably 300 angstrom or less. When the thickness of the p-side capping layer 216 is greater than 0.1 μη, cracking tends to invade into the p-side capping layer 216, and it is difficult to grow the p-side capping layer 2 1 6 of a nitride semiconductor layer with good crystallinity. The p-side cap layer 2 16 is preferably made of a nitride semiconductor containing a semiconductor, particularly aluminum-gallium gas (AeGaN). At this time, if the aluminum-gallium nitride (AeGaN) having a larger composition ratio of aluminum is formed with a thinner p-side cap layer 216, the LD element is more likely to be laser oscillated. For example, when the p-side cover layer 216 is formed of AlyGai.yN with a y value of 0.2 or more in the formula, it is particularly desirable to adjust the thickness of the p-side cover layer 216 to 500 angstroms or less. The lower limit of the thickness of the ρ-side cover layer 21 6 is not particularly limited, but the formation thickness of the ρ-side cover layer 2 16 is preferably 10 Angstroms or more. The p-side capping layer 216 may be doped with a p-type impurity as the p-type, but because the thickness is too thin, it may be doped with an n-type impurity as the type of the compensated carrier, or it may not be doped with impurities. It is most desirable that the p-type capping layer 216 be doped with a p-type impurity. On the P-side cover layer 216, a band gap energy ratio of the p-side cover layer 216 is formed. 38 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ---------- installation-( Please read the precautions on the back before you fill out this page)-* Printed by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Bayer Consumer Cooperative ¾ 406445 a? __ B7 V. Description of the invention () is small, and the p-side is made of nitride semiconductor Light guide layer 2 丨 7. In the p-side light guide layer 217, light from the active layer 215 serves as a guiding layer, and it is ideal to be formed of gallium halide (GaN) or indium gallium nitride (InGaN) like the n-side light guide layer 214. The p-side light guide layer 217 may be used as a buffer layer when a P-side cladding layer 2 1 8 to be described later is grown. The thickness of the p-side light guide layer 2 i 7 is 100 angstroms to 5 angstroms, and more preferably 200 angstroms! Alas, it has the role of an ideal light guide layer. The p-side light guide layer 217 is usually a p-type impurity doped with magnesium (Mg) and the like, and may be doped with no impurity. The p-side light guide layer 217 may be formed as a superlattice structure. This superlattice structure can be formed by sequentially stacking first and second nitride semiconductor layers having mutually different band gap energies. The p-type side light guide layer 217 of such a superlattice structure may be formed by alternately stacking an i-th layer made of gallium nitride (GaN) and a second layer made of indium-gallium nitride (InGaN). In this case, at least one of the first layer and the second layer may be doped with a p-type impurity or not. On the p-side light guide layer 217, a p-side cladding layer 2 1 8 made of a nitride semiconductor is formed. This cladding layer 21 8_ functions as a carrier blocking layer and a light blocking layer similarly to the η-side cladding layer 2 1 3. The ρ is a cladding layer 2-8 which is a nitride semiconductor containing aluminum, and more preferably an aluminum-gallium nitride (AlGaN) -containing one. When formed into a superlattice structure, it has the effect of reducing the resistivity of the p-side layer. This superlattice structure can be formed by sequentially stacking the first and second compound semiconductor layers with different band gap energies. In this case, by doping a plurality of impurities into one of the first layer and the second layer to do so-called modulation doping, the threshold value of the LD element can be reduced. For example, the p-side cladding layer 21 8 can be doped with a P-type impurity, such as a first thin layer composed of magnesium (Mg) aluminum-gallium argon hydride (A1GaN) and an impurity-doped gallium nitride (GaN). The 39th paper size constituted by) applies Chinese National Standard (CNS) A4 specification (2 丨 〇 > < 297mm) --------- ^ — (Please read the precautions on the back before (Written on this page)-Order 406445 Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs. 5. Description of the invention (2) It is formed by alternately laminating thin films. ? The side cladding layer 218 is formed to a thickness of 100 angstroms or more and 2 acres or less, and more preferably 500 angstroms or more. In addition, those who form the P-side cladding layer 218 into a super-changer structure have a tendency to reduce the resistance of the ρ-side layer as described above, compared to those who form the η-side cladding 2 1 3 into a superlattice structure. It is desirable to reduce the forward voltage of the LD element. For example, a double-heterostructure gaseous semiconductor device having an active layer 215 with a quantum structure, especially in an LD device, where the band gap energy is larger than that of the active layer 2L5 near the active layer 215, and the thickness 0 > 1 A capping layer 216 containing a nitride semiconductor containing aluminum, which is located farther from the active layer 215 than the capping layer 216, and has a p-side light guide containing a nitride semiconductor whose band gap energy is smaller than that of the capping layer 216. Layer 217; and is located farther away from the active layer 2 1 5 than the p-side light guide layer 2 1 7, and its band gap energy is set to be greater than that of the P-side light guide layer 217 'a super crystal containing a nitride semiconductor containing aluminum The lattice structure p-side cladding 218 'is very ideal. At this time, the p-side cap layer 216 has a larger band-gap energy ', so that electrons injected from the p-side layer are blocked in the cap layer 216. As a result, electrons do not overflow the active layer 215, so that the leakage reduction current of the 'LD device is reduced. The structure of the LD element is basically composed of an n-side cladding layer 213, an n-side light guiding layer 214, an active layer 215, a p-side light guiding layer 217, and a p-side cladding layer 218. In order to install a p-electrode, a p-side contact layer 219 made of a p-type nitride semiconductor is formed on the p-side cladding layer 218. The p-side contact layer 219 is inxAlyGaix yN (0 helmet X, 0 $ y, x + y $ l) 'doped with p-type impurities, especially doped with p-type impurities, especially magnesium (Mg) gallium nitride. (GaN) formers are ideal. The formation thickness of the ρ-side contact layer 219 is 500 angstroms and 40 paper sizes, using the Chinese National Standard (CNS) A4 specification (2 丨 0x 297) --------- install-(please First read the notes on the back δ Write this page) Binding line A7 B7 406445 V. Description of the invention (below, it is more ideal to be 400 angstroms or less and 20 angstroms or more. As shown in Figure 10, the uppermost P-side contact The layer 219 and the portion of the P-side cladding layer 2 1 8 are etched into a line shape to form a ridge portion. On the entire surface of the top surface of the Shaw portion, a p-side electrode 22o is formed, such as nickel. (Ni) 'Platinum (Pt), Palladium (Pd), Cobalt (Co)' Nickel (Ni) / Gold (Au) (laminated or alloy), Platinum (pt) / Gold (Au) (laminated or alloy) When palladium (pd) / gold (An) (laminate or alloy) is formed, a more ideal resistive contact with the p-side contact layer 2 1 9 can be achieved. In addition to the top surface of the p-side electrode 220, On the exposed surfaces of the p-side cladding layer 218 and the p-side contact layer 219, an insulating film 221 made of silicon oxide (SiO2) or zirconium oxide (ZrO) is preferably formed. On the insulating film 221, an insulating film 221 is formed. Electrically connected to the p-side base electrode 222 of the p-electrode 220 »In the nitride semiconductor substrate 1000, as described above, the n-type impurity is doped, so that the n-side electrode 223 can be formed on substantially the entire surface of the back surface of the nitride semiconductor substrate 1000. The η-side electrode 223 is made of a metal such as aluminum (Al), titanium (Ti), tungsten (W), copper (Cu), zinc (Zη), tin (Sn), or indium (In), or a laminate of these metals. When an alloy of these metals is formed, a more ideal resistive contact with the η-type layer (the back surface of the substrate 1000 in this example) can be achieved. On the II-side electrode 223, a heat sink (to be mounted) The metal thin film (not shown) with Au / Sn two-layer structure is preferably used for metallization between layers. Figure 11 shows the nitride semiconductor substrate 1000 except the support 10 of the present invention. A schematic perspective view of the LD element having a structure similar to that in FIG. 10 except for the LD element in a supported state. In the LD element in FIG. 11, the p-side cladding layer 21 8, the p-side light guide layer 217, The cap layer 21 6, the active layer 215, the n-side light guide layer 214, the n-side cladding layer 213, and the crack prevention layer 212 are all etched. Carved to make the side exposed, and become a rectangular parallelepiped paper size applicable to China National Standards (CNS) A4 (210 X 297 mm) ^ ------ tr ------ ^ {Please first Read the notes on the back and then #write this page) Consumption Cooperation for Employees of the Central Procurement Bureau of the Ministry of Economic Affairs 406445 A7 B7 V. Description of Invention This etching also penetrates into the surface of the buffer layer 211 so that the surface of the buffer layer 211 is exposed on both sides of the rectangular parallelepiped structure, and n-side electrodes 223a and 223b are formed on both surfaces of the buffer layer 211 (this The buffer layer 211 also functions as an η-side contact layer. Of course, the insulating film 221 also covers the exposed ρ-side cladding layer 2 1 8, the ρ-side light guide layer 2 1 7, the cover layer 216, the active layer 215, and the η-side light guide. Each side of the layer 214, the n-side cladding layer 213, and the crack prevention layer 212. In addition, when the substrate is doped with n-type impurities, the buffer layer 211 can be completely etched by the above-mentioned etching process to make the substrate The surface of 100,000 is exposed. In this case, the η-side electrodes 223a and 223b may be formed on the surface of the exposed substrate 1000. The η-side electrodes may not be only on one side of the rectangular parallelepiped structure. Fig. 12 is a structural diagram of another LD element according to the present invention. In the LD element shown in Fig. 12, the insulating film 221 is formed on the exposed surface of the p-side cladding layer 218 'so that the p-side contact layer 2 1 9 is formed. The thickness of the top surface is exposed, the p-side electrode 220 contacts the p-side contact layer 2 1 9 and is wide It is formed on the insulating film 22 1 'as a result' except that the base electrode 222 is not provided, and it has a structure similar to that of the LD device having the structure shown in FIG. II. Furthermore, in the LD device shown in FIG. 223 is formed only one. To grow the nitride semiconductors constituting the nitride semiconductor device structure of the present invention, 'any suitable method such as MOVPE, HVPE, MBE, etc. which is known to be suitable for nitride semiconductor growth can be used. The ideal growth method is the MOVPE method. This method can make the crystal grow beautifully. However, when the MOVPE method requires a longer time to form a thicker nitride semiconductor layer, a time-dependent growth method is more ideal. In addition, according to the purpose of use, a variety of nitride semiconductor growth methods are appropriately selected to grow the nitride semiconductor, which is more in line with the ideal. In addition, the national semi-conductor layer 42 paper size is applicable to Chinese National Standards (CNS) A4 size (210 mm 297 mm) (Please read the precautions on the back before filling this page).

• Printed by the Consumer Cooperatives of the Central Bureau of Standards and Procurement of the Ministry of Economic Affairs 406445 Α7 _B7 5. In the description of the invention (), when n-type impurities or p-type impurities are to be doped, it is as familiar in this field. In general, 疋 incorporates a Group 4 element as an n-type impurity in the form of an organic compound or argon 'or a Group 2 element as a p-type impurity in the form of an organic compound. Hereinafter, the present invention is illustrated by examples. In the following embodiments, Movpe is performed under a reduced pressure in a 50-400 torr range.氺 Embodiment 1 This embodiment can refer to FIG. 1A to FIG. 1C. First, "form a line-shaped mask on a sapphire substrate π with a diameter of 2 inches, which has a main surface composed of the C plane and an orientation plane (hereinafter referred to as the ORF plane) constituting the" a "plane. Hereinafter, the CVD) device forms each selective growth mask I with a line width of 10 μm, a line interval (window width) of 6 angstroms, and a thickness of 0.1 formed by most silicon oxide (SiO2). Each line mask is formed so as to extend parallel to each other in a direction perpendicular to the ORF surface. Put the sapphire substrate 11 on which the selective growth mask 13 is formed in a MOVPE reaction vessel, set the temperature to 5 ° C, and use hydrogen as a carrier gas. The raw material gas is ammonia and trimethylgallium (hereinafter referred to as TMG). On the substrate 11 on which the selective growth mask 13 is formed, a low-temperature buffer layer (not shown) made of gallium nitride (GaN) is grown to a thickness of about 200 angstroms. The low-temperature buffer layer is formed only in the window 14. After the buffer layer grows, stop the flow of TMG (that is, continue to circulate the hydrogen carrier gas and ammonia) and increase the temperature to 1050 ° C. In 105 (rc), TMG and oxygen are used as source gases, and the dopant gas is a silane gas, which is a nitride semiconductor crystal substrate composed of GaN doped with silicon (hereinafter referred to as si) at 1 × 1018 / cm3. 16 Grows 100 thickness of the cape. 43 This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) ---------- ^ ------ ΐτ ----- -Line (Please read the precautions on the back before filling in this page) A7 B7 406445 V. Description of the invention () Then 'remove the cymbals from which the GaN crystal substrate has been grown out of the reaction container' and grind the surface of the GaN crystal substrate 16 into a mirror surface Comparative Example 1 For comparison, on the sapphire substrate of Example 1, a selective growth mask was not formed, and the GaN buffer layer was directly grown to the same thickness of 22 Angstroms, and IX 1018 / cm3 was doped thereon. The growth of Si and GaN is 100 μη. The number of lattice defects per unit area (crystal defects) of the GaN crystal obtained in Example 1 and the GaN crystal obtained in Comparative Example i was measured with a plane-view electron microscope (hereinafter referred to as TEM). As a result of observation, the number of lattice defects of the GaN crystal of Example 1 was observed. Comparative example 1 is less than 1/10. * Example 2 This example can refer to Figures 6A to 6C. On the surface of the GaN crystal 16 obtained in Example 1, the same as in Example 1 are formed. Line width 10 μη ′ Most of the thickness of the line interval 6 μm is made of silicon nitride (SisN4) lines. The thickness of the second selective growth mask 113 is explained. The position of the second selective growth mask 113 is the same as that of the first selective growth. The positions of the masks 1 and 3 are staggered. In more detail, each line of the second selection growth mask Π3 is located at a position corresponding to the window 14 of the first selection growth mask, and 'and the first selection growth mask The mold 13 extends in parallel to make the mask counterposition. The wafer after forming the second selective growth mask 113 is placed in the MOVPE reaction vessel again, using TMG and ammonia as the source gas, and silane as the dopant gas. The GaN crystal 116 doped with Si of 1 × 1018 / cm3 was grown to a thickness of 150 μηι. The wafer after growing the GaN crystal was taken out of the reaction container, and 44 paper standards were applied to Chinese National Standard (CNS) A4 specifications. (210X297 mm) ---------- ^ ------, tr ------. ^ (Please The notes on the back of the reading are reproduced on this page.) The BBC Industrial and Consumer Cooperation Cooperation Department of the Central Bureau of Standards of the Ministry of Economic Affairs is printed by the Central Government Bureau of the Ministry of Economic Affairs and printed by the Central Bureau of Industrial and Consumer Affairs Cooperatives. 445445 A7 _ B7 V. Description of Invention () Example 1 is the same. The surface was polished to a mirror surface, and the number of lattice defects (crystal defects) per unit area was measured by plane TEM observation. As a result, the number of defects of the GaN crystal 116 of this example was 1 / the number of GaN crystal defects of Comparative Example 1. 100 or less.氺 Embodiment 3 In this embodiment, reference can be made to the first circle A to Fig. 1C and the sixth circle A to Fig. 6C. On the sapphire substrate 1 of Example 1, a low-temperature buffer layer made of GaN was grown to a thickness of 200 angstroms, and a pure GaN layer was grown thereon to a thickness of 5 meshes to form a bottom layer 12 having a two-layer structure. On the plane of the bottom layer 12 of the obtained support 10, the same method as in Example 1 was used to form each line with a width of 10 μxη 'and a line interval of 8 μm. 1Select growth mask 13. The first selective growth mask 13 is an extender which is perpendicular to the sapphire a plane and is parallel to each other. The wafer after forming the first selective growth mask 13 was placed in a MOVPE reaction vessel, and 1050 eC was used to grow pure GaN crystal 16 to a thickness of 100 μm using TMG and ammonia as raw material gases. Remove the wafer of the grown GaN crystal 16 from the reaction container, and grind the surface of the GaN crystal 16 into a sharp surface β. On the surface of the GaN crystal, the width of each line is 12 μm, and the interval between the lines is 6 μm. Most of the second choice growth mask 113 made of Si3N4 with a thickness of ο.ίμηι. The line masks of the second selective growth mask 113 are formed at positions corresponding to the windows 14 of the first selective growth mask 13, respectively. The wafer after forming the second selective growth mask 113 was placed in the MOVPE reaction vessel again, and TMG and ammonia were used as source gases to grow the pure GaN crystal 116 to a thickness of 150 μm. The obtained pure GaN crystal 116 45 paper size is applicable to the Chinese national standard (CNS > A4 size (210X297 mm) -----: ----- ^ ------ 1T-- ---- ^ (Please read the precautions on the back before writing this page) The Central Industry Bureau of the Ministry of Economic Affairs, Zheng Gong, Consumer Cooperation Du printed 406445 a? __ B7 V. The number of crystal defects in the description of the invention (') and implementation The GaN crystals of Example 2 are the same. 氺 Example 4 In this example, 'except that the heterogeneous substrate 11 is a sapphire substrate having a main surface composed of the A surface' and an RF surface constituting the R surface, so that 2 The line mask is formed except that it extends perpendicular to the r-plane, and the same method as in Example 1 is used to grow the Si-doped GaN crystal 16 to a thickness of 100 μm. The number of crystal defects of this GaN crystal 16 is approximately the same as that of Example 1. The GaN crystals are the same. * Example 5 In this example, reference can be made to Figure 1A to Figure 1C. First, 'preparing a main surface with a (211) plane and an ORF plane with a (110) plane' A spinel substrate n having a diameter of 1 inch. On the surface of the spinel substrate II, as in Example 1, a spinel substrate n is formed by a plurality of lines. The width of each line of the i-th selective growth mask Πβ extending in the vertical direction of the ORF surface is 12 μm. The interval between the lines is 6 μm. Inside the quartz reaction container on the HVPE device, a boat capable of containing gallium (Ga) metal is set. . At the position away from the quartz boat |, the inclined setting has formed the spinel substrate 11 after the first selective growth mask 13. The position close to the Ga metal in the reaction vessel is provided with a tooth gas supply pipe, and A nitrogen source supply pipe is provided at a position separated from the halogen gas supply pipe and close to the substrate 11. A nitrogen carrier gas and a hydrogenated hydrogen gas (hereinafter referred to as HC1) gas are simultaneously introduced from the halogen gas supply pipe. At this time, the The boat of Ga metal is heated to 900 ° C, and the spinel substrate is heated to 1050t. Then, HC1 gas and Ga metal are reacted to generate gallium gas (hereinafter referred to as GaCl3), and the nitrogen from the spinel substrate 11 is close to The source supply pipe supplies both ammonia gas and nitrogen carrier gas, and from the 46 paper size of halogen to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) ---------- install-(please (Read the notes on the back first to write this page) Printed by the Department of Economics of the Ministry of Economic Affairs, Central Bureau of Quasi-specialty Bureau, Male Workers Consumer Cooperative «. A7 406445__j___ V. Description of the invention () The supply pipe pays attention to HC1 gas and silane gas at the same time, and grows at a growth rate of 50 μm / hour for 3 hours. So that the GaN crystal 16 doped with Si of 1 X 10u / cm3 is grown to a thickness of 150 μω. The wafer of the grown HVPE gallium nitride crystal 16 is taken out of the reaction container, and the surface of the GaN crystal 16 is polished to remove the surface. Concave and convex, measure the number of lattice defects. As a result, the number of defects of the GaN selective crystal 16 obtained in this example is the same as that of the GaN crystal of the first example. * Embodiment 6 This embodiment can refer to FIGS. 8A to 8B. First, the wafer with Si-doped GaN crystal obtained in Example 1 was placed in a reaction vessel of a MOVPE device, and the doped 1 X was doped on the Si-doped GaN crystal at 50 ° C. The two-temperature buffer layer 81 composed of SaN of 〇18 / cm3 of Si was grown to a thickness of 1 pm. Next, on the high-temperature buffer layer 81, an active layer 82 composed of In0.4Ga0.6N (In: Marriage, Ga: Gallium'N: Nitrogen) with a single quantum well structure with a thickness of 20 Angstroms was sequentially grown in MOVPE. The thickness is 0.3μω, which is made of Mg-doped AlO ^ Ga. A p-side cladding layer 83 made of 8N and a 41 p-side contact layer 84 made of Mg-doped GaN having a thickness of 0.5 nm. Then, the wafer was taken out of the reaction vessel, and the temperature was changed to 600 in a nitrogen atmosphere. (: Annealing 'reduces the resistance of the p-side cladding layer 83 and the p-side contact layer 84. Then, the p-side contact layer 84 is sequentially etched to expose a portion of the Si-doped GaN crystal. This etched portion is used as a subsequent scribe. After etching, a light-transmissive p-side electrode 85 with a thickness of 200 Angstroms in a Ni / Au double-layer structure is formed on the entire surface of the P-side contact layer 84, and 0.5 is formed on the p-side electrode 85. The thickness of the base electrode 86 for welding is formed. After forming the base electrode 86, the wafer is made of sapphire substrates 11, 47. The paper size is in accordance with the Chinese standard (CNS > A4 (210X297 mm)) (Please read first Remarks on the back page will be rewritten on this page) • Binding-Binding-Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 406445 A7 _________B7 V. Description of the invention () Low-temperature buffer layer 12 and the first choice growth mask ι3 (see section 丨Figure c) The 'reverse surface of the doped SiGaN crystal 16 is exposed by grinding and removed, and an η-side electrode 87 having a thickness of 0.5 μm is formed on a substantially entire surface of the back surface. Then, a scribe is cut along the cutting line from the η-electrode side. , On the M side of the Si-doped GaN crystal 16 ((11 〇) surface) and the surface perpendicular to the μ surface, cleave it to make a 300 μη square LED chip. This LDE emits 520 μηι green light at 20mA, which is the same as the conventional one on a sapphire substrate. Compared with the grown LED element, it has more than twice the output, and the electrostatic withstand voltage is more than doubled. It has very excellent characteristics. * Example 7 This example can refer to Figure 10. The obtained from Example 2 will be grown and doped. The wafer after 3 ′ GaN crystal 116 was placed in the reaction vessel of the MOVPE device, and the Si-doped GaN crystal 116 was replaced with Si 10 doped with 5 X 1 〇18 / cm2. The thickness of the high-temperature buffer layer 211 made of GaN is grown. Then, on the two-temperature buffer layer 211, an η-type In doped with Si doped with 5 × 101 * / cm3 of Si. The growth crack prevention layer 212 made of jGaogN is 500 angstroms. Thickness-On the crack prevention layer 212, a layer of 20 angstrom thickness consisting of η-type Al ^ Ga ^ N doped with 5 x 10u / cm3 of si and a thickness of 20 angstroms made of pure GaN The second layer having a thickness of 100 μm is alternately laminated to form a η-side cladding layer 213 of a superlattice structure with a total thickness of 0.4 μm. On the layer 213, a η-side light guide layer 214 composed of η-type GaN doped with Si of 5 × 108 / Cin3 is grown to a thickness of 0.1 μm. The connector 'will be made of pure I η. 2 G a 〇8 Ν The formed _ 2 5 Angstrom thickness well layer and the 50 Angstrom thickness barrier layer composed of pure In .. (nGao. ^ N 48 sheets of paper are used in China National Standard (CNS) A4 (210X297 mm) — (Please read the precautions on the back before filling out this page)-Binding · Ordering A7 B7 406445 V. Description of the invention (Activate the stack to form a multiple quantum well (MQW) structure with a total thickness of 175 Angstroms.) Layer 21 5. Next, the band-gap energy is made larger than that of the P-side light guide layer 2 1 7 and also larger than that of the active layer 215. The p-type Al 0 3Ga is doped with Mg doped at 1 × 102 Q / cm3. The p-side cap layer 216 made of 9N grows to a thickness of 300 angstroms. On the P-side cap layer 21 6, its band gap energy is smaller than that of the p-side cap layer 21 6. A p-side light guide layer 217 composed of p-type GaN doped with Mg of 1 × 10 (2) / cm3. Grow 0.1 μm thickness. Next, on the P-side light guide layer 217, p-type Al doped with Mg doped with 1 × 10 2 Vcm 3. 2Ga. The first layer with a thickness of 20 angstroms composed of 8N and the second layer with a thickness of 20 angstroms composed of p-type GaN doped with 1 × 1020 / cm3 of Mg were alternately stacked to form an ultra-thin layer with a total thickness of 0.4 μm. The p-side cladding of the lattice layer 2 1 8. Finally, a P-side contact layer 219 composed of p-type GaN doped with Mg of 2 × 102 ° / cm3 was grown to a thickness of 150 angstroms. After being printed by the Consumer Cooperative of the Central Associated Bureau of the Ministry of Economic Affairs to grow all the nitride semiconductors, the wafer was placed in a nitrogen atmosphere and annealed at 700 ° C to make the P-type layer more resistant. . After annealing, the wafer was taken out of the reaction vessel, and the uppermost p-side contact layer 219 and p-side cladding layer 218 were etched with a reactive ion etching (hereinafter referred to as RIE) device to form a wide band-shaped ridge portion. A p-side electrode 220 of a Ni / Au two-layer structure is formed on the entire top surface of the ridge. Next, an insulating film 221 made of SiO 2 is formed on the exposed side surfaces of the p-side cladding layer 2 1 8 and the contact layer 2 1 9 except for the P-side electrode 220, and an electrical connection with the P-side electrode is formed on the insulating film 221. Connected to the p-side base electrode 222. After the P-side pedestal electrode 222 is formed, the wafer sapphire substrate 11, the buffer layer 12, the first selective growth mask 13, the IGaN crystal 16 and the second 49 are scaled to the national standard of China (CNS) A4 specification (210X297mm) 406445 A7 B7 V. Description of the invention (Central Bureau of the Ministry of Economic Affairs, Kibei Consumer Cooperative Printing Co., Ltd. Selects a part of the growth mask 113 and the second GaN crystal 116 by grinding to remove the back of the second GaN crystal. An n-side electrode 223 having a thickness of 0.5 μm was formed on the entire back surface, and an Au / Sn film for metallization between the heat sink and the heat sink was formed thereon. Then, a scribe was made from the n-side electrode 223. 'The second GaN crystal 116 is cleaved into a stripe on the M-plane (1100 plane; the side corresponding to the side of the third hexagonal column) of the second GaN crystal U6.' And Ti〇2 dielectric multilayer mold, and finally cut the elongated body parallel to the extending direction of the p-side electrode 22 to make a laser wafer. With each wafer facing up (the substrate and the heat sink face each other) ) Set on the bulk photo and connect the p-side base electrode 222 to the lead The number of LD elements thus obtained was placed at room temperature 'when the laser was exhausted', and it was confirmed that it was at room temperature. The critical current density was 2.0KA / cm2 and the critical voltage was 4.0V. Those who continuously oscillate at an oscillating wavelength of 405 nm and have an exhaust life of more than 10,000 hours. 氺 Embodiment 8. This embodiment can be referred to Fig. 9. In a similar manner to that of Embodiment 6, 'obtained in Embodiment 2 On top of the pure GaN crystal 116, a high-temperature buffer layer 81 composed of GaN doped with 1 × 108 / cm3 of Si and a single quantum composed of In .. 4G a .. 5N with a thickness of 20 Angstroms are sequentially grown. The active layer 82 of the well structure, the thickness of 0.3 μm is composed of Mg-doped 8 1.20 & .8> 1? Side cladding 83, and the thickness of 0.5 mesh is made of Mg-doped GaN A p-side contact layer 84 is formed. Next, as in Example 6, a translucent p-side electrode 85 'is formed on substantially the entire surface of the p-side contact layer 84, and a base electrode 86 is formed thereon. After predetermined etching After processing, η-side electrodes 8 7 are formed on the high-temperature buffer layer 81. 50 This paper size is in accordance with China National Standard (CNS) A4 210X297 mm) (Please read the precautions on the back before writing this page) -Z · b- -9 Γ Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3: 06445 * A7 ___B7_ V. Description of the Invention () * The LED element of this embodiment is different from the LED element of Embodiment 6 in that the LED element structure of this embodiment is formed on a second GaN crystal 116 having better crystallinity than the GaN crystal 16 of Example 1, The p-side electrode 85 and the n-side electrode 87 are provided on the same surface side of the substrate. In this way, in a nitride semiconductor device having a structure in which a nitride semiconductor doped layer (high-temperature buffer layer 81) doped with n-type impurities is stacked on a pure GaN crystal substrate, when an n-type electrode is provided on the n-type layer side, When the n electrode is provided on the n-type impurity-doped gaseous semiconductor layer, the forward voltage V9 is lower, and it is easier to obtain an LED element with higher luminous efficiency. "In fact, the LED element of the eighth embodiment and the implementation Compared with the LED element of Example 6, its output has been increased by about 1.5 times, and the electrostatic withstand voltage has also been increased by about 1.5 times.氺 Embodiment 9 In this embodiment, reference may be made to FIGS. 1A to 1C and 9). As in Example 3, a low-temperature buffer layer made of GaN was grown to a thickness of 200 angstroms on a sapphire substrate having a main surface composed of c-plane and an ORF surface constituting A-side, and a pure GaN layer Grow 4 μ® thickness to form the bottom layer 12 of a 2-layer structure. A CVD device was used to form a line width of 20 mn on a pure GaN layer. The line interval was 5 pm, and the thickness of the first selection growth mask consisting of most Si02 lines was Ιμη. Β The first selection growth mask system Each vertical direction to the ORF plane is parallel to each other. "The wafer is transferred to a MOVPE device, and the G aN crystals doped with Si x 9 / cm3 are grown to a thickness of 15 μm.

From here on, a single quantum well with a thickness of 20 angstroms, consisting of a GaN doped with IX 10 " / cm3 Si, was sequentially grown on the Si-doped GaN crystal in the same manner as in Example 8. Structure of In. 4Gaa.6N active layer, 0.3 μηη in thickness of Mg-doped Al. 2Ga. P 51 constituted by 8N This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ------------------------------- Please read the precautions on the back before writing this page) Printed by Shellfish Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs, 406445 at __ B7 V. Invention! ^ () Side cladding layer and p-side contact layer composed of Mg-doped eaN with a thickness of 0.5 swells. Then, the surface of the doped GaN crystal doped with Si with a higher impurity concentration is exposed from the p-side cladding and an n-side electrode is formed thereon. On the one hand, a transparent layer is formed on the entire surface of the p-side contact layer. The optical p-side electrode has a solder base electrode formed on the p-side electrode. As described above, in this LED element, the 'n-side electrode and the 卩 -side electrode are placed on the same side of the substrate. Finally, the sapphire substrate was polished to a thickness of about 50 μm, and then diced from the polished surface side to make a 350 μm square LED element. This LED element has the same characteristics as the LED element of Example 6, but the yield rate of the element itself is 100 times or more.氺 Embodiment 10 This embodiment can refer to FIGS. 1A to 1C and 9. Prepare to have a bevel angle 0 = 013 by the C plane. A step with a step height difference of about 15 angstroms, a platform width W of about 56 angstroms, and a sapphire substrate 11β with a diameter of 2 inches that constitutes the ORF surface of the A side. The low-temperature buffer layer composed of GaN is grown to a thickness of 200 angstroms, and a pure GaN layer is grown thereon to a thickness of 4 to form a bottom layer 12 of a two-layer structure. The width of the line 25 ′ μτη, and the line interval 5 _ are mostly the first growth mask 13 having a thickness of 0.1 μm made of SiO 2 lines. The first selective growth masks extend in parallel to each other in a direction perpendicular to the a-plane. The wafer was transferred to a MOVPE device to grow a GaN crystal of Si doped with lxioiVcm3 to a thickness of lOpjjj. Then 'on the Si-doped GaN crystal, sequentially grow a high-temperature buffer layer composed of 1 × 1018 / cm3 of Si-doped GaN, with a thickness of 52. This paper size applies the Chinese National Standard (CNS) A4 specification ( 2 丨 0 > < 297 mm) -------- I -Shang-- (Please read the precautions on the back first and then the fan nest page) Thread A7 B7 406445 V. Description of the invention () 20 Angstroms Of a single quantum well structure. jGa ^ N active layer, p-side cladding layer consisting of Mg-doped AlQ.2Ga0.8N with a thickness of 0.3 mm and p-side consisting of Mg-doped GaN with a thickness of 0.5 mesh Contact layer. Henceforth, the same processing as in Example 9 is performed, and a 350,000-square LED element is produced. Compared with the LED element of Example 9, the LED element can improve the output by about 5%. The yield of the element itself is the same as that of Example. 9 The same high yield.氺 Example Π After the GaN crystal doped with lxl0ivcm3 of Si was grown to a thickness of 10 μm according to the procedure of Example 9, the wafer was taken out of the reaction vessel of the MO VPE device. A second selective growth mask consisting of silicon dioxide lines with a width of 15 μm was formed at each position. The wafer on which the second selective growth mask has been formed is transferred to the MOVPE device again, and the second GaN crystal 116 doped with lxl0i9 / cm and Si is grown to a thickness of 15 µm. Next, in the same manner as in Example 9, a single quantum having a thickness of 20 Angstroms—a high-temperature buffer layer made of ixlOlg / cm3 doped thereon—was sequentially grown on the second Si-doped GaN crystal 116. The well structure of In0.4Ga <). 6N active layer, thickness 0.3. 'a. A p-side cladding layer composed of J and a P-side contact layer composed of Mg-doped GaN with a thickness of 0.5 ceramics. Then, the same process as in Example 9 was performed to form a 350A square LED element. This LED element has approximately the same characteristics as those of the LED of Example 8. The yield of the element itself is 100 times or more than that of Example 8. "Wood Example 12 This embodiment can be referred to Fig. 8A and 8 Figure B .. —-^ 1 — II I I equipment—— I I order—— I I I Brigade (Please read the note on the back first—fill out this page)

406445 V. Description of the invention () Put the sapphire substrate 11 having the main surface composed of the C surface and the ORF surface constituting the A surface into the reaction vessel of the MOVPE device, and place the sapphire substrate 1 on the sapphire substrate 1 at 500 ° C. After the low-temperature buffer layer made of GaN was grown to a thickness of 200 Angstroms, the temperature was set to 105 ° C., and the GaN layer made of GaN was grown to 5 μω to form a bottom layer with a two-layer structure. 12 »Take the wafer out of the reaction container, On the top surface of the bottom layer 12, a line-shaped photomask is formed using a CVD device to form each line with a width of 20 μm, and most of the line interval (window width) 5 μm each have a thickness of SiO. Mask 13 »The masks of the lines extend parallel to each other in the vertical direction of the orf plane. The wafer on which the selection mask 13 has been formed is again inserted into the MOVPE reaction container, and the surface of the Si-doped GaN crystal 16 Polished into a mirror surface. In this Si-doped GaN crystal 16, the number of crystal defects corresponding to the surface area of the first selective growth mask 13 is not more than 10 / cm 2. Next, Si-doped GaN is grown. Crystal 16's wafer, once again moved to MOVPE reaction vessel, on the Si-doped GaN crystal 16, a buffer layer (n-side cladding layer) composed of 1 × 1018 / cm3 of Si-doped GaN is grown to a thickness of 1 μm. The center of the Ministry of Economy Knead the printing of the Bureau ’s Consumer Cooperatives I --------- ^ —— (please read the note f on the back and then $ this page). Then, make it on the cladding 81 on the side in order. A pure quantum well structure with a thickness of 20 angstroms is grown in In.4Ga. ΔN active layer 82, a thickness of 0.3 μm, and a p-side package composed of AV2Ga0.8N doped with Mg 1 X 102 ° / cm3 Layer 83, and a 0.5 μm thick P-side contact layer 84 made of GaN doped with 1 × 102 Å »Then, the wafer was taken out of the MOVPE reaction vessel, and annealed at 600 ° C in a gas atmosphere, so that The P-side cladding layer 83 and the p-side contact layer 84 have reduced resistance. Then, the p-side contact layer 84 is etched to make the η-side cladding layer 8 1 54. This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm). ) 406445 A7 B7 Printed by the Central Bureau of quasi-government of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. 5. Description of the invention () or the surface of GaN crystal 16 is exposed to set a cutting line. On the substantially entire surface of the contact layer 84, a light-transmissive P-side electrode 85 of a Ni / Au two-layer structure with a thickness of 200 angstroms is formed, and a P-side base electrode 86 for welding with a thickness of 0.5 mesh is formed on the P-side electrode 85. After the P-side pedestal electrode 86 is formed, the wafer sapphire substrate 11, the bottom layer 12, and the first selective growth mask 13 are polished and removed to expose the back surface of the GaN crystal 16, and a substantially entire surface of the back surface is formed. 0.5 is called the n-side electrode 87 of the W / A1 two-layer structure with a thickness. Then, the wafer is cut from the cutting line into a long shape, and the long body is cut in a direction perpendicular to the long side of the long body to produce an LED chip. In the nitride semiconductor layer under the active layer of the LED wafer, the crystal defect is that there are fewer parts above the first selective growth mask and more parts above the window. As described above, in a region where there are few crystal defects, more area of the active layer is provided 'to obtain a highly reliable device. At 20 mA, the LED obtained in this example emits 520 nm green light, and its output is more than two times that of the conventional vapor semiconductor semiconductor device structure grown on a sapphire substrate, and the electrostatic withstand voltage is also 2 Above 侉, it has very excellent characteristics. In addition, the shape of the first selective growth mask in this embodiment is a line shape, but it can also be pre-matched to the shape of the wafer to be cut (for example, a square shape) so that the selective growth mask is formed regularly. Dots are formed, and wafers are cut out at positions corresponding to the window of the selective growth mask. * Example 13 This example can refer to the eleventh circle. Using the method of Example 12, the GaN crystal 16 doped with Si of 1 × 0i * / cm3 was grown to a thickness of 6 μm. Put the GaN crystal 16 that has been grown into MOVPE reaction 55 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --- ^ -------- install-(please first (Read the notes on the back and fill out this page)

1T line * ι06445 Printed A7 B7 of the Central Laboratories and Consumer Cooperatives of the Ministry of Economic Affairs of the People's Republic of China 5. Description of the invention () In the container, at 1050 ° C, the Si-doped GaN crystal 16 is doped by 1 X A high-temperature buffer layer 211 made of 10 l8 / cm3 of Si and GaN is grown. Next, on the high-temperature buffer layer 211, a crack termination prevention layer 212 composed of Infl lGaQ9N doped with 5X1018 / cm3 of Si was grown to a thickness of 500 angstroms. Next, the first layer of 20 angstrom thickness made of η-type AluGauN doped with Si doped with 5xl018 / cm3 of Si and the second layer of 20 angstrom thickness made of pure GaN were alternately stacked on the crack-prevention layer 212. 100 layers to form a η-side cladding layer 213 with a superlattice structure of a total thickness of 0.4 μm. Next, an n-side light guide layer 214 composed of n-type GaN doped with Si of 5 × 1018 / cm3 was grown to a thickness of 0.1 μm. On the n-side light guide layer 214, pure In is used. A 25 Angstrom well layer composed of 2Ga0N and pure In. The barrier layers having a thickness of 50 angstroms are alternately stacked to form an active layer 215 of a multiple quantum well (MQW) structure with a total thickness of 175 angstroms. Above the active layer 215 ', its band gap energy is larger than that of the p-side light guide layer 217 and larger than that of the active layer 215, and p-type AlOjGa doped with Mg doped at 1 × 1020 / cm3. The p-side cap layer 216 made of jN grows to a thickness of 300 angstroms. On the p-side cap layer 216, the band gap energy is smaller than that of the p-side cap layer 2 i 6. The p-side light guide layer 217 composed of p-type GaN doped with Mg 1 X 102 ° / cm 3 is grown by 0.1. μm thickness. On top of the P-side light guide layer 217 'will be a P-type Al ^ Ga doped with Mg doped at 1x120 / cm3. The first layer with a thickness of 20 angstroms composed of 8N and the second layer with a thickness of 20 angstroms composed of p-type GaN doped with Mg of 1 X 102 ° / cm3 are alternately stacked to form a total thickness of 0.4 μm. Lattice structure p-side cladding 2 丨 8 β 56 This paper size adopts Chinese National Standard (CMS) A4 specification (210X297 mm) Please read the note on the back of the binding line printed by the Central Government Bureau of the Ministry of Economic Affairs Crack u06445 a? B7 V. Description of the invention () Finally, a p-side contact layer 219 composed of p-type GaN doped with 2 × 102 ° / cm3 of Mg is grown to a thickness of 150 angstroms. After all the nitride semiconductors were grown, the wafer was annealed in a nitrogen atmosphere at 700 ° C to make the p-type layer more resistant. After annealing, the wafer was taken out of the reaction container, and the uppermost P-side contact layer 2 1 9 and the p-side cladding layer 21 8 were etched by using a RIE device to form a ridge portion having a line width of '4. The ridge portion was formed. It is formed in a direction parallel to the lines of the first selection growth mask, and is formed above the first selection growth mask. After the ridge is formed, the p-side cladding layer 2 1 7 exposed on both sides of the ridge is centered on the ridge line, so that the surface of the η-side cladding layer 2 11 is exposed for the formation of the η-side electrode. 223a, 223b. Then, a p-side electrode 220 of a Ni / Au two-layer structure is formed on the entire top surface of the ridge. In addition to the p-side electrode 220, an insulating film 221 made of Si02 is formed on the surfaces of the p-side cladding layer 218 and the p-side contact layer 219, and the insulating film 221 is formed to be electrically connected to the p-side The P-side base electrode 222 of the electrode 22o. On the one hand, on the surface of the η 恻 cladding layer 211 that is exposed before and after, η-side electrodes 223a and 223b of a two-layer structure of W / A1 are formed. After the η-side electrode was formed, as in Example 9, the wafer sapphire substrate was polished to a thickness of 50 μω, and then perpendicular to the lines of the linear ρ-side electrode 220 and the lines of the η-side electrodes 223 a and 223 b. The substrate η cleaves it so that the cleaved surface of the cleaved active layer 215 is used as the resonance surface. In the GaN crystal 16, a region with a large number of crystal defects and a region with a small number of crystals are mixed. In the LD element, n-side electrodes 223 a and 223 b are formed on the region with a large number of crystals, so that the active layer 215 does not exist in this region. In this way, the active layer 215 where the heat is concentrated will not be damaged due to crystal defects, so it can be 57 ---------- ^ ------ tr -----.- I0 (Please first Read the notes on the back and write this page again i / r) Wide-Paper method ffl ifeV 1¾ atk / Mm. Vm Via ia ix. / Λ · f \. ^ Pieces} * Male 9 7- ^ 06445 A7 --- B7 __ 5. Description of the invention (7 ~ " '~~ Obtain an LD device with high reliability and long life. When the LD device obtained in this example is placed at room temperature to make its laser vibrate, the system is reduced. It can continuously oscillate at a critical wavelength current density of 2.0KA / cm2 and a critical voltage of 4.0V at an oscillation wavelength of 405nm, and has a lifetime of more than 100,000 hours.》 Example 14 This example can Reference is made to Figs. 1A to 1C. First, "on a 2-inch diameter sapphire substrate 11 having a main surface composed of c-plane and ORF formed of A-plane, in the same manner as in Example 1, shape A line-shaped photomask is formed by a CVD device to form a first selection growth mask 13 with a width of 10 A and a line interval (window 14) of 5 μm, most of which are formed by SiO 2 with a thickness of 0_1. Each line π It is an extender perpendicular to the ORF surface of the sapphire substrate 11. The sapphire substrate 11 on which the first selective growth mask 13 has been formed is set in a MOVPE reaction vessel, and the temperature is set to 5. The hydrogen gas is used as the carrier gas and the raw material gas. Ammonia and TMG are used to grow a low-temperature buffer layer (not shown) made of GaN on the substrate 11 on which the selective growth masks 13 have been formed. The thickness is about 200 angstroms. After printing to grow the buffer layer, 'only stop the flow of TMG and raise the temperature to 1 050 ° C. At 1050 ° C, TMG and ammonia are used as the raw material gas, and the dopant gas is a silane gas to dope IX 100 s / cm3 of Si GaN crystal 16 is grown to a thickness of 100. Then, the wafer having grown GaN crystal 16 is taken out of the reaction vessel, and the surface of GaN crystal (substrate) 16 is polished to a mirror surface. GaN crystal, as in Comparative Example 1 above The number of crystal defects of the obtained GaN crystals was measured by plane TEM observation. The result was that 58 paper sizes were in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 06.445 V. Description of the invention () Example 14 The number of crystal defects of the GaN crystal is an average of i 3 χ 1 06 / cm2 'and the number of crystal defects of the GaN crystal of Comparative Example 1 is an average of 2 4 X 107 / cm2. That is, the number of crystal defects of the GaN crystal of Example 14 is It is 1/10 or less of Comparative Example 1.氺 Embodiment 1 5 In this embodiment, reference can be made to FIGS. 1A to 1C. On the sapphire substrate 11 used in Example 14, a low-temperature buffer layer made of GaN was grown to a thickness of 200 angstroms, and a pure GaN layer was grown thereon to a thickness of 5 μm to form a bottom layer 12 having a two-layer structure. On the top surface of the bottom layer 12 of the wafer, the same method as in Example 14 is used to form a first selection growth mask 13 with a width of 10 μω and a line interval of 3 μm. Most of the lines are formed by Si02 lines with a thickness of 1 μm. . Each line 13 extends in a direction perpendicular to the RF surface of the sapphire substrate u. The wafer on which the first selective growth mask 13 has been formed is moved into the HVPE reaction vessel 'at 1050t' using GaCl3 and ammonia as raw material gases, and the dopant gas is a silane gas to crystallize Si-doped GaN 16 grow 300 μm thickness. The wafer with the grown GaN crystal 16 was taken out of the reaction container, the sapphire substrate 11, the bottom layer 12, and the selective growth mask 13 were removed by grinding, and the back surface of the GaN crystal 16 was polished to a mirror surface to prepare a Si-doped GaN crystal. Substrate. As in Example 14, the number of crystal defects on the side opposite to the polishing side was measured, and the result was i X 10Vcm2, which was less than the number of crystal defects of the GaN crystal of Example 14, and very good crystals were obtained. Substrates for the production of flexible components β 氺 Example 1 6 59 This paper> ^ 1 Applies to Chinese National Standards (CNS> Α4 Specification (21Qx297)) (Please read the precautions on the back before filling this page) Order from the Ministry of Economic Affairs S. A7 B7 06445 printed by the Consumer Bureau of the Standard Bureau V. Description of the invention (In this embodiment, in addition to the sapphire substrate Η having the main surface composed of the A surface and the 0RF surface configured as the R surface, as the heterogeneous substrate 丨丨 Outside 'The same method as in Example 14 was used to make Si-doped (JaN crystals 16 grow to 100 mesh thickness), and each line 13 is extended in the vertical direction of the R plane. As a result, the general and practical examples can be obtained. 1Equivalent slow pits with very few GaN crystals 16. * Example 17 First, a spinel substrate having a main surface composed of a (111) surface and an ORF surface constituting a (110) surface is prepared. η. On the surface of the spinel substrate u In the same manner as in Example i, a first selective growth mask with a thickness of 1 μm, which is composed of a plurality of SiO 2 lines, is formed, and is extended in the vertical direction of the RF surface β. The width of each line is β 0, and the interval between the lines is β. The spinel substrate π having the first selective growth mask 13 formed thereon was subjected to the same HVPE method as in Example 1 to grow a GaN crystal doped with Si of lxlOi * / cm3 to a thickness of 150 nm. The crystal wafer of the impurity 31 was taken out of the reaction container, and the spinel substrate and the selective growth mask 13 were removed by grinding. The number of crystal defects was measured in the same manner as in Example 14. As a result, the GaN obtained in this example was obtained. Crystals are crystals with approximately the same number of erosion spots as in Example 14. * Example 1 8 For this lean example, refer to Figure 8A and Figure 8B.

From the circular plate obtained in Example 14, the sapphire substrate η, the low-temperature buffer layer, and the selective growth mask 13 were polished and removed, so that the back surface of the doped GaN crystal was scooped out to obtain a monomer doping 3 丨GaN crystal substrate 1000. Put the Si-doped GaN crystalline substrate 1000 into MOVPE and load 60 sheets of paper. Chinese national standard (CNS) A4 specification (210X297 mm) ------------- --- Order ------ line (please read the note ^ on the back of the M first and then fill in this tile) Printed by the Male Workers 'Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economy Printed by the Shell Workers' Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs «. 406445 A7 B7 ''-~ " — * 1 '' " ~ V. In the reaction vessel of the invention (), at 1050 ° C, the surface is made of Si doped with 1 X 1018 / cm3. A high-temperature buffer layer 81 made of GaN is grown. On the high-temperature buffer layer 81, a single quantum well-structured InwGauN active layer 82 having a thickness of 20 angstroms and a thickness of 0.3 μm by a dopant parent 102 were sequentially grown. \ 1§Eight 1 of 1113. .2〇 &. .8] What constitutes ^? A side cladding layer 83, and a p-side contact layer 84 made of GaN doped with 1 × 102 ° Mg GaN having a thickness of 0.5 cm. The wafer on which each nitride semiconductor layer has been grown is taken out of the reaction vessel, and annealed at 600 ° C. in a nitrogen atmosphere to reduce the resistance of the p-side cladding layer 83 and the p-side contact layer 84. Then, an etching process is performed from the p-side contact layer 34 to expose the surface of the Si-doped GaN crystal substrate 1000. The cutting line at the time of the wafer cutting is set by this last process. After the above-mentioned etching process, a light-transmissive p-side electrode 85 having a Ni / Au two-layer structure having a thickness of 200 angstroms was formed on the substantially entire surface of the p-side contact layer 84, and a soldering substrate having a thickness of 0.5 μm was formed on the surface. After the base electrode 86 is formed, the η-side electrode 87 having a thickness of 0.5 μm is formed on the entire surface of the back surface of the GaN crystal substrate 1000. Then, from the η electrode side, scribe along the above-mentioned cutting line, and cleave the GaN crystal substrate 1000 on the M plane (1100 plane) and the plane perpendicular to the μ plane to make a 300u square LED chip. . This LED chip emits 520nm green light at 20mA. Compared with conventional nitride semiconductor element constructors grown on sapphire substrates, the LED chip has more than twice the rotation speed and more than twice the electrostatic withstand voltage. Characteristics. * Embodiment 19 This embodiment can be viewed in accordance with Figure 10. The GaN crystal substrates doped with Si in Example 18, 100, 61 (please read the precautions on the back before filling out this page). Binding and binding paper I use China National Standards (CNS) Eight 4 threats (210X297 mm). Central Standards Bureau of the Ministry of Economic Affairs " C Industrial Consumer Cooperatives Co., Ltd. 406445 5. Description of the invention () Put in the reaction container of the MOVPE device, no buffer layer is provided on the surface of the substrate 1000 211 and the crack prevention layer 211, and the n-side cladding layer 213 is directly formed. More specifically, η-type Al02Ga made of Si doped with 1 X 1019 / cm3 is used. The first layer with a thickness of 20 angstroms composed of 8N and the second layer with a thickness of 20 angstroms composed of pure GaN were alternately grown to form a η-side cladding 21 of a superlattice structure with a total thickness of 0.4 nm. 3. Next, on the n-side cladding layer 213, an n-side light guide layer 214 composed of n-type GaN doped with Si of lx1017 / cm3 was grown to a thickness of 0.1 μm. Next, on the n-side light guide layer 214, In made of Si doped with 1 × 1017 / cm3. A well layer of 25 Angstrom thickness composed of 2GaQgN, and In doped with Si of lx 10l7 / cm3. The 50 Angstrom barrier layers composed of wGao.wN are alternately stacked to form an active layer 2 1 5 of a multiple quantum well (MQW) structure with a total thickness of 175 Angstroms. Next, on the active layer 215, the band-gap energy is larger than that of the P-side photoconductive layer 217 and also larger than that of the active layer 215. A p-type AluGa doped with Mg of IX 102 ° / cm3 is used. The p-side cap layer 216 made of 9N grows to a thickness of 300 angstroms. Next, on the p-side cap layer 216, the band-side energy of the p-side cap layer 216 is smaller than that of the p-side cap layer 216. A P-side light guide layer 217 composed of P-type GaN doped with Mg lxl018 / cm3 is grown to a thickness of 0.1 μηι. . Next, on the P-side light guide layer 217, a first layer having a thickness of 20 angstroms consisting of p-type Al ^ Ga ^ N doped with Mg of IX 102 ° / cm3, and doped with .1 X 1020 / The second layer with a thickness of 20 angstroms consisting of p-type GaN of Mg of cm3 was alternately stacked to form a P-side cladding layer 218 with a superlattice structure of a total thickness of 0.4 呷. Finally, on the P-side cladding layer 218, the paper size is doped to 2X 102 ° / cin3 62. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). --Quan (Please read the notes on the back before filling this page) Printed by the Ministry of Economic Affairs of the Zhunzhen Bureau of Zhenggong Consumer Cooperative Co., Ltd. * Spit 06445 A7 B7 V. Description of the invention () M p-type GaN p The side contact layer 219 grows to a thickness of 150 Angstroms. The wafers in which the respective nitride semiconductor layers were formed in this way were placed in a nitrogen atmosphere in a reaction vessel and annealed at 700 ° C to make the p-type layer more resistant. After annealing, remove the wafer from the reaction vessel and use! ^ 1 £ 敦 'The top p-side contact layer 219 and p-side cladding layer 218 are etched to form a ridge with a line width of 4 divisions, and on the entire surface of the top surface of the ridge, Ni / The p-side electrode 220 of the Au two-layer structure. Then, in addition to the top surface of the p-side electrode 220, an insulating film 221 'consisting of 3 and 02 is formed on the exposed side surface of the p-side electrode 220, the exposed surface of the p-side cladding layer 218, and the contact layer 219, and the insulation The p-side base electrode 222 electrically connected to the p-side electrode 220 is formed on the film 221. After the p-side pedestal electrode 222 is formed, a η-side electrode 223 ′ of a Ti / Al two-layer structure with a thickness of 0.2 μm is formed on the entire back surface of the Si-doped GaN crystal substrate 1000 and a heat sink is formed thereon. Au / Sn thin film for metallization. Then, the wafer was diced from the electrode 223 side, and the GaN crystal 1000 was cleaved on the M surface ((1100) surface of the GaN crystal substrate 1000; the surface corresponding to the side surface of the hexagonal column in FIG. 3) to provide a step. Shake the surface and make a long body. On either or both sides of the resonance surface of the strip, a dielectric multilayer mold of Si02 and Ti〇2 is formed “last” in a direction parallel to the extending direction of the p-side electrode 22, and the strip is cut off to form an LD element. Wafer. This wafer was placed with its front side facing up, and the p-side base electrode 222 was wire-bonded. This LD element oscillates its laser at room temperature. It is confirmed that it is at room temperature. It can continuously oscillate at a threshold current density of 2.0KA / cm2 and a threshold voltage of 4.0V. And has a life of more than 10,000 hours. 63 This paper size is applicable to China National Standard (CNS) A4 (210X297mm) ---------- installation ----- 1T ------ ^ (please read the back first Please note this page, please fill in this page again) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. 406445 a? ____ B7 V. Description of the invention () 氺 Embodiment 20 This embodiment can refer to FIG. 9. On the pure GaN crystal 16 (supported by the sapphire substrate j 1) obtained in Example 15, n-type Al made of Si doped with IX 10i9 / cm 3 was made. 2Ga. The first layer with a thickness of 20 angstroms composed of gN and the second layer with a thickness of 20 angstroms composed of pure GaN were alternately grown in 100 layers to form a η-side cladding with a superlattice structure of a total thickness of 0.4 μηη. 8 1. Next, on the η-side cladding layer 81, a single quantum well structure with a thickness of 20 Angstroms and a single quantum well structure of In〇4Ga〇6Ν active layer 82, a thickness of 0.3 由, is doped by Mg doped 1 X 1 020 / cm3. Ρ-side cladding layer 83 made of Al0.2Ga0.8N, and P-side contact layer 84 made of GaN doped with M > < i〇2〇 / cm3 Etching and adding from the p-side contact layer 84 exposes the surface of Si-doped GaN crystal 1000 with a large impurity concentration, and an n-side electrode 87 is formed thereon. On the substantially entire surface of the p-side contact layer 84 A light-transmitting p-side electrode 85 is formed thereon, and a solder base electrode 86 is formed thereon. At last. After grinding the sapphire substrate to a thickness of about 50 μm, the sapphire substrate was diced from the side of the polished surface to make a 350 μm square LED element. The LED element thus obtained was compared with the LEp element of Example 18, and its output was approximately Increased by 1.5 times, the electrostatic withstand voltage is also increased by about 1.5 times.氺 Embodiment 2 1 According to the method of Embodiment 15, a low-temperature buffer layer made of GaN was grown on the sapphire substrate 11 of Embodiment 15 by a thickness of 200 angstroms, and a pure GaN layer was grown thereon. 4 After the thickness, the same first choice as in Example 15 was formed. Next, the wafer was moved to a MOVPE device, and doped with 1 X 10u / cm3 64 paper standard Chinese standard (CNS > A4 specification (210X297)) ---------- ^ ------ iT ------ i (Please read the precautions on the back before filling out this page) Consumer cooperation of the Central Government Bureau of the Ministry of Economic Affairs 衽 06445 α7 _ Β7_ V. Description of the invention () A 2 inch diameter sapphire substrate 11 having a main surface composed of the C surface and an ORF surface constituting the A surface was placed in a MOVPE reaction vessel, the temperature was set to 500 ° C, and argon was used as the carrier gas. TMG and ammonia grow a low-temperature buffer layer made of GaN to a thickness of 200 angstroms, and a pure GaN layer is grown thereon to a thickness of 5 nm at a temperature of 1050 ° C. to form a two-layered bottom layer 12. The wafer of the bottom layer 12 is taken out of the MOVPE reaction container. On the surface of the bottom layer 12, a line-shaped photomask is formed. Using a CVD device, the width of each line is 10 μm, and the line interval is 2 nm. The first selection growth mask 13. The wafer on which the selection growth mask 13 has been formed is placed in M again. In the OVPE reaction vessel, the temperature was set to 1050 ° C, and ammonia was passed at a flow rate of 0.27 g molecular weight / min, and TMB was flowed at a rate of 22 μg molecular weight / min (molar ratio: vun ratio = 1200), and pure GaN was crystallized 16 When the grown GaN crystal 16 ′ is grown at a thickness of 30 μπι when observed by a cross-section TEM, the number of crystal defects in the region from the interface of the bottom layer 12 to a height of about 5 μηι is large (10 Vcm2 or more). In the lower region and the upper region, the number of crystal defects (106 / cm2 or less) is sufficient. For nitride semiconductor crystal substrates, the surface of the grown crystal 16 corresponds to Although the central part of each line and the central part of each window show crystal defects, the number of crystal defects is more than two digits smaller than when the molar ratio (hereinafter referred to as the V / II ratio) is greater than 2000. Next, using ammonia and TMG as source gases, and using a silane gas as the dopant gas, an N-side buffer layer 211 made of GaN doped with Si of 3 × 10 18 / cm 3 was grown on the GaN crystal 16 to a thickness of 5 μm. Then 'raw gas With TMG, TM1 and ammonia, at 800 ° C, a 66-sheet scale applies Chinese National Standard (CNS) A4 specifications (210 ^^ 57 nnn III! I n Order I (Please read the notes on the back before filling this page ) Printed by Du Zhongzhuo Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs, Du printed 4〇b445 A7 B7 V. Description of the invention () 2 inches of sapphire with a main surface consisting of the C surface and an 〇RF surface constituting the A surface The substrate 11 was placed in a MovpE reaction container, the temperature was set to 500 ° C, argon was used as the carrier gas, and TM (} and ammonia were used as the source gas to grow a low-temperature buffer layer composed of GaN to a thickness of 200 angstroms. On it, a pure GaN layer was grown at a thickness of 5 以 at a temperature of 1050 ° C to form a bottom layer 12 having a two-layer structure. The wafer having formed the bottom layer 12 was taken out of the movpe reaction container, and a line-shaped photomask was formed on the surface of the bottom layer 12. Using a CVD apparatus, the width of each line was 10 μm, and the interval between the lines was 2 mm. The first selection growth mask 13 with a thickness of 1 μm formed by a plurality of SiO 2 lines. The disc with the selective growth mask 13 formed was placed again in the mOVPE reaction vessel, and the temperature was set to 1050C. The ammonia was flowed at a molecular weight of 0.27 g / min, and the flow rate of τμB was 22 μg molecular weight / min (molar ratio). : Wni ratio = ι2〇〇) flow through 'grow pure GaN crystal 16 with a thickness of 30 μη. When the grown GaN crystal 16 is observed by cross-section TEM, the height from the interface of the bottom layer 12 to about 5 μm In the lower region, the number of crystal defects is larger (more than 108 / cm2), and in the upper region of the lower region, the number of crystal defects is smaller (less than 106 / cm2). Used as a nitride semiconductor crystal substrate. Although the surface of the crystal 16 after the growth is partially corresponding to the central portion of each line and the central portion of each window, although crystal defects appear slightly, the molar ratio (hereinafter referred to as the V / ΙΠ ratio) is greater than 200 ○, the number of crystal defects has been reduced by more than two digits. Next, using ammonia and TMG as raw material gases, and using a silane gas as the dopant gas, an N-side buffer layer 211 composed of GaN doped with 3 X 1018 / cm3 of Si was grown on the GaN crystal 16 to a thickness of 5 μm. Next, the raw material gas is TMG, TMI and ammonia, at 80 ° C, 66 paper sizes. Common Chinese National Standard (CNS) A4 specification (210x297 mm) \ Gutter (please read the precautions on the back before filling in this Page) Printed by the Men ’s Consumer Cooperative of the Central Sample and Standards Bureau of the Ministry of Economic Affairs at 406445 at-B7 V. Description of the invention () On the η-side buffer layer 2 11 so that in. Q6Ga. The crack formed by 94n prevents the growth of Tu 212 with a thickness of 0.15 μm. Then, it is 1050. 〇, make doping! X 10l9 / cm3 of Si-n-type Al. The first layer with a thickness of 25 angstroms (using TMA, TMG, ammonia, and silane gas) composed of 2Ga " N and the second layer (using TMG and ammonia) with a thickness of 25 angstroms composed of pure GaN are alternately grown to form The superlattice structure η side cladding 213 with a total thickness of 0.8 division. Then 'to 1050. (: A η-side light guide layer 214 made of pure GaN was grown to a thickness of 0.1 μm. Next, TMG, TMI, and ammonia were used to form a pure In0.2Ga.8N at a temperature of 80 ° C. The thickness of the well layer of 40 angstroms and the barrier layer of 100 angstroms made of pure Ino.oiGa. Are alternately laminated to form a multiple quantum well structure with a total thickness of 440 angstroms to the end of the barrier layer. Active layer 2 1 5. Next, the temperature is increased to 1050. (: TMG, TMA 'ammonia and CpaMg' are used to make the band gap energy larger than that of the p-side light guide layer 217, and doped by 1x1 〇2 ° / cm3 of Mg p-type Al0.3Ga0 7N p-side capping layer 216 is grown to a thickness of 300 angstroms. Then, using TMG and ammonia, the band gap energy ratio of the p-side capping layer 216 is 10050. The small P-side photoconductive layer 217 made of pure GaN grows to a thickness of 0.1 μη. Then 105 (rc) is made of P-type Al doped with Mg doped at 1 × 10 2 () / cm3. 2Ga0.8N The first layer with a thickness of 25 angstroms and the second layer with a thickness of 25 angstroms made of pure GaN are alternately grown to form a p-side cladding 218 of a super-lattice structure with a total thickness of 0.8 angstroms. Finally, at 1050 ° C 'On the p-side cladding Above 218, a p-side contact layer 219 made of p-type GaN doped with Mg of 1 × 10 2 ° / cm3 is grown to a thickness of 150 angstroms. ___ 67 This paper is in accordance with the Chinese Standard (CNS) A4 specification ( 2ΐ〇χ297mm) 111111 1 Pack — — —- II i Order i! I I Brigade (please read the precautions on the back before filling out this page) Printed by the Men ’s Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 406445 A7 _ B7 V. Description of the invention () The wafer after the vaporized semiconductor layer is grown as described above, is placed in a nitrogen atmosphere in a reaction vessel, and annealed at 700 ° C, so that the layer doped with p-type impurities has lower resistance. After the β annealing, the wafer was taken out of the reaction vessel, and the uppermost p-side contact layer 219 and p-side cladding layer 218 were etched by using a RIE device to form a ridge with a width of 4 lines. It is formed on the surface area where the crystal defect appears, which corresponds to the position of the central part of the line mask 13 and the central part of the window. When a ridge line is formed at a position where there is almost no crystal defect, the crystal defect may be difficult in laser vibration Transfer from substrate to active area Therefore, the life of the element will be extended, and the reliability will be increased. Then, a protective mask is formed on the top surface of the ridge, and the surface of the π-side buffer layer 211 is exposed by RIE etching. The exposed η-side buffer layer 211 is also regarded as The contact layer used to form the η-side electrodes 223a, 223b. Also, "T" is etched into the region where the GaN crystal 16 has many crystal defects, and the exposed surface is used as the contact layer. Next, on the top surface of the ρ-side contact layer 219 constituting the ridge, a linear ρ-side electrode 22〇β composed of Ni and Au is formed. On the one hand, on the surface of the η-side buffer layer 211 exposed by the above name, Formed by! ^ And A1 are linear n-side electrodes 223a and 223b. Then, an insulating film 221 made of SiO 2 is formed on the side surface of the nitride semiconductor layer exposed by the above-mentioned etching, and a p-side base electrode 222 electrically connected to the p-electrode 220 is formed on the insulating film 221. . Next, the obtained wafer is moved to a polishing device, and the diamond sapphire substrate η is used to grind the sapphire substrate η to a thickness of 70 μm from the back of the sapphire substrate 11, and then polished with a finer abrasive to 1 μω, so that the This surface becomes a mirror surface, and the entire surface of the back surface is coated with Au / Sn metal. L-_. ___68

Applicable to China National Standard (CNS) A4 (210X297mm JI nnnn I n I n ^ I n III Order — —— IIII line (Please read the precautions on the back before filling this page) Printed by the consumer cooperative A7 4〇64dFi_ 87__ 5. Description of the invention () Then, the circle is scribed from the Au / Sn side, and it is cleaved into a strip shape in the direction perpendicular to the line electrode to make a resonance. On the resonance surface, a dielectric multilayer film of Si02 and Ti02 is formed, and finally the long body is cut in a direction parallel to the p electrode to form an LD element wafer. The wafer is placed facing up for heat dissipation. On the chip, and lead wires are welded on each electrode. When the LD element is oscillated at room temperature and laser oscillated, it is confirmed that the LD element can have a critical current density of 2.0KA / cm2 and a critical voltage of 4.0V or less. It continuously oscillates at an oscillation wavelength of 405 nm and has a lifetime of more than 10,000 hours. In addition, from the LD elements obtained from the wafer, 500 LD elements were randomly extracted. As a result of measuring the lifetime, more than 70% had 10,000 More than hours of life. During the growth of the crystal, in addition to setting the ammonia flow rate to ο ″ g molecular weight / min, the TMG flow rate was 162 μg molecular weight / min (V / III ratio = 2222) to grow pure GaN crystal 16 to a thickness of 30 μm. The ridge line was formed at an arbitrary position, and an LD device was made in the same manner as in Example 23. Among the 500 LD devices randomly extracted from the obtained LD device, the life span of 10,000 hours or more was 5%. The following: 氺 实施 例 24

An ld element was fabricated in the same manner as in Example 23 except that the GaN crystal was grown to a thickness of 100 Å. As a result, the number of crystal defects on the surface of the GaN crystal 16 tends to be one digit more than that of the ld element of Example 23. From among the 500 LD elements randomly extracted from the obtained LD element, the lifetime reaches 10,000. Hours or more is 50% or more. Embodiment M This embodiment can refer to FIG. 11. In Example 23, when the GaN crystal 16 was grown, in addition to the _______ 69 paper from the Chinese Standards (CNS) Eighty-fourth Secret (21〇 &gt; &lt; 297 public production ~ -------- --1 ------ tr ------ # (Please read the note on the back before filling this page) Central Ministry of Economic Affairs \, printed by the bureau ’s consumer cooperative «. 406445 A7 A 7 B7 V. Description of the invention () The flow rate of ammonia is changed to 0.27 g molecular weight / min, the flow rate of TMB is changed to 150 μg molecular weight / min (V / III ratio = 1800), and a silane gas is added to the raw material gas. 23 In the same way, the Si-doped GaN crystal is grown to a thickness of 30 μm. The GaN crystal 16 has a large number of crystal defects in the region from the interface between the GaN crystal 16 and the bottom layer to a height of about 5 ，. In the upper region higher than the lower region, there are few crystal defects (<0 &lt; s / cm2 or less), which is enough to be used as a nitride semiconductor substrate. The subsequent method is the same as that in Example 23 to form a nitride. The semiconductor layers 211 to 219. Next, 姒 etching is performed, and this time, except that the GaN crystal 16 is removed from the surface of the GaN crystal 16 to about 6 μm, there are many crystal defects. The GaN crystal 16 is exposed in a region 'except that n-side electrodes 223a and 223b are formed on the exposed surface'. In the same manner as in Example 23, an LD element is fabricated. The LD element can also be continuously vibrated at low criticality in the same manner as in Example 23. For those who can reach a lifetime of more than 10,000 hours, more than 50% of the 500 .. * Example 26 is to grow the GaN crystal 16 except that the ammonia flow rate is set to 0.27 g molecular weight / minute TMG flow rate setting An LD device was fabricated in the same manner as in Example 23 except that the molecular weight was 180 μg / min. As a result, an LD device that continuously oscillated at a low critical value and had approximately the same life and number as in Example 23 was obtained. In Example 27, when growing GaN crystal 16, except that the TMG flow rate was increased and the V / III ratio was set to 800, an LD device was fabricated in the same manner as in Example 23. As a result, a similarly low LD device was obtained. The critical value continuously oscillates and has the same life and quantity of LD components as in Example 23. 氺 Example 28 70 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ------- --- install— (Please read the note on the back first Please fill in this page again), π line 406445 A7 B7 V. Description of the invention () ~ 'When growing GaN crystal 16, in addition to setting the ammonia flow rate to 0.15 g molecular weight / min and the TMG flow rate to 5 mg molecular weight / min Except for (ν / πΐ ratio = 3 0), LD elements were fabricated in the same manner as in Example 23. As a result, the same LD elements were continuously vibrated at low critical values, and 500 LD elements were randomly extracted from the obtained LD elements. Among LD devices, the lifetime is more than 10,000 hours, 50% or more. * Example 29 is to grow GaN crystal 16 except that Si is doped to grow the Si-doped GaN crystal to a thickness of 90 μm. In the same manner as in Example 23, nitride semiconductors 211 to 219 were grown. Then, when the wafer was taken out from the reaction container, the wafer was warped due to the difference in thermal expansion coefficient between the sapphire substrate 11 and the Si-doped GaN crystal, so the circle was polished from the sapphire substrate 11 to remove the sapphire substrate Bottom layer 12 and selective growth. Long mask 13. The obtained single GaN crystal was not warped, and was almost flat. Next, as in Example 23, the p-side contact layer 219 and the p-side cladding layer 218 were etched into a ridge shape. After the p-side electrode 22 and the insulating film 221 were formed, the p-side base electrode 222 was formed. At this time, since the selective growth mask 13 has been removed, it is difficult to observe the position of the ridge line with the window by a microscope. On the one hand, n-side electrodes 223a to 223b made of Ti / A1 are provided on the substantially entire surface of the back surface of the GaN crystal 16 with a large number of exposed crystal defects. Then, this structure was processed in the same manner as in Example 23 to obtain an LD device. This LD element also oscillates continuously at a low critical value at room temperature. Among the 500 LD elements randomly extracted, more than 70% have a lifetime of more than 10,000 hours.氺 Example 3 0 71 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 406445 a? B7 V. Description of the invention () This example can refer to Figure 1A to Figure 1C and Figure 5A to Figure 5B . A 2 inch diameter spinel substrate 11 having a main surface composed of the C surface and an ORF surface constituting the A surface was placed in a MOVPE reaction vessel, the temperature was set to 500 ° C, and argon was used as a carrier gas. The gas uses TMG and ammonia to grow a low-temperature buffer layer made of GaN to a thickness of about 200 angstroms, and on top of it, pure GaN is grown to a thickness of 4 Å at 105 ° C. to form a bottom layer 12 having a two-layer structure. The wafer having formed the bottom layer 12 was taken out of the MOVPE reaction container, and a line-shaped photomask was formed on the surface of the bottom layer 12. A CVD apparatus was used to form each line width lOjim, and the line interval was 2 μm. The first selective growth mask 13 with a thickness of 0.5 mm. The wafer having the selective growth mask 13 formed thereon was again placed in a MOVPE reaction vessel at a temperature of 1050 ° C, an ammonia flow rate of 0.27 g molecular weight / minute, and a TMG flow rate of 225 microgram molecular weight. / Min (V / III ratio = 1200), and the pure GaN crystal 16 grows to a thickness of 30 晔. In this way, the V / III molar ratio is set to 2000 or less. When the GaN crystal is grown, the growth end face of the GaN crystal 15 will The dry surface facing the mask 13 constitutes approximately vertical The crystal plane grows in the mold direction on the mask π. Therefore, crystals with very few crystal defects can be obtained. 16 »The grown GaN crystal (MOVPEGaN crystal) 16 has a uniform surface. When the surface area is observed by TEM The crystal defects extended from the window 14 have stopped on the way within the GaN crystal 16 and hardly appeared on the surface. The receiver 'moved the wafer of the gallium-grown GaN crystal 16 to the ηVPE device, using Ga metal as a raw material, Use HC1 gas and ammonia to make pure GaN junction

The crystal (HVPEGaN crystal) 17 grows to a thickness of 200 μm. The number of crystal defects in the surface area of the obtained HVPEGaN crystal 17 was measured by plane TEM observation. The paper size was 72 paper sizes (CNS) A4 (210X297 mm). (Please read the precautions on the back before filling in this. page)

1T 406445 V. Description of the invention () (Please read the notes on the back before filling this page) The result is below 1 X 104 / cm2, that is, it is determined that GaN crystals with good crystallinity have been obtained. In addition, there are very few crystal defects, and only those crystal defects extending in a substantially horizontal direction in a plane. The wafer with the grown HVPEGaN crystal 17 is moved to a polishing device, and the sapphire substrate 11, the bottom layer 12, the selective growth mask 13 and the MOVPEGaN crystal 16 are removed with a diamond abrasive, and the back surface of the HVPEGaN crystal π is exposed to make a total Monocrystalline GaN substrate with a thickness of 195 Å. In addition, the crystal defects on the back surface of the crystal substrate also had a small amount of 1 × 10 5 / em2 or less. * Example 31 is to grow HVPEGaN crystal 17 except that in the raw material gas, Zhao Jiajiaomeng gas-fired vessel 'In the beginning, one side was doped with Si of lxi〇19 / cm3, and GaN was grown along with it. It grows to reduce the flow of silane gas, and finally it is grown by GaN doped with Si of 5 X 10 volt cm3. In this way, G aN with a Si concentration gradient is grown to a thickness of 200 μm. The same method as in Example 30 is used. 'Make a single GaN crystal substrate. The side of this GaN crystal substrate having a small amount of Si was one having the same number of crystal defects as the crystal substrate of Example 30. * Example 32 In the case of growing consumption of MOVPEGaN crystals 16 in the case of consumer cooperation with the Central Bureau of Prototype of the Ministry of Economic Affairs, in addition to adding silane gas to the raw material gas, in the beginning, Si was doped with IX 10i9 / cm3 while GaN grows and extinguishes the flow of silane gas as it grows, and finally it is grown with GaN doped with Si at 1 X 1017 / cm3 to grow GaN with a Si concentration gradient to a thickness of 20 μm, In the same manner as in Example 30, a Si-doped HVPEGaN crystal 17 was grown to a thickness of 200 μηη. Then all 73 of the special sapphire substrate 11, the bottom layer 12, and the selective growth mask 13 are in accordance with the Chinese standard (CNS) M specification (210 × 297 mm) 406445 I7 5. The description of the invention () is removed, and only MOVPEGaN crystals are removed 15 _Thickness. In the GaN crystal substrate having the two-layer structure of MOVPEGaN crystal and HVPEGaN crystal obtained as described above, the number of crystal defects in the main HVPEGaN crystal is approximately the same as that of the GaN crystal substrate of Example 30. However, in the MOVPEGaN crystal, The number of crystal defects on the back surface is approximately i-digits more than the number of major crystal defects in HVPEGaN crystals.氺 Embodiment 3 3 This embodiment can refer to FIG. 12. On the surface of the HVPEGaN crystalline substrate (1000) obtained in Example 30 (opposite to the back surface of the sapphire substrate 11 etc. that has been removed by grinding) "Ammonia and TMG are used as raw material gases, and the impurity gas is a silane gas, with a value of 105 0 ° C. The n-side contact layer 211 composed of GaN doped with 3 × 10u / cm3 of Si was grown to a thickness of 4 μm. On top of the UI-side contact layer 211 ', TMG, TMI, and ammonia are used as raw material gases, and the temperature is set to 800. ○, and the crack prevention layer 212 made of InowGao. ^ N was grown to a thickness of 0.15 呷. Printed by the Consumer Cooperatives of the Central Bureau of Procurement, Ministry of Economic Affairs (please read the precautions on the back, and then fill in this page). Next, on the crack prevention layer 212, use pure Al at 1050 ° C. The first layer with a thickness of 25 Angstroms made of 16Ga0 8? N (using TMA, TMG and ammonia), and the second layer with a thickness of 25 Angstroms made of η-type GaN doped with 1 X lOH / cm3 of silicon (using TMG, ammonia, and silane) are alternately grown to form a η-side cladding layer 213 of a superlattice structure with a total thickness of 1.2. Next, on the η-side cladding layer 213, using the TMG and ammonia, the η-side light guide layer 214 made of pure GaN was grown at a thickness of 1050 ° C. Next, the temperature was set to 800t so that a barrier layer having a thickness of 100 angstroms made of pure InowGaowN and pure In was used. 2Ga (). SN wells with a thickness of 40 angstroms are alternately grown 3 times to form 74 which ends with the barrier layer. The paper size is applicable to the Chinese National Standard (CNS) A4 (210X29 * 7 mm) 406445 5. Description of the invention () Active layer 215 of MQW structure with a total thickness of 520 angstroms. Then, the temperature was raised to 1050 ° C, and TMG, TMA, ammonia, and Cp2Mg were used to make p-type Al doped with Mg doped at 1 × 1020 / cm3. 3Ga. The P-side cap layer 216 made of 7N grows to a thickness of 300 angstroms. Next, on the p-side cap layer 216, a p-side light guide layer 217 composed of GaN doped with 5 × 10 16 / cm3 of Mg was grown to a thickness of 0.1 mm. Then made of pure Al. The first layer with a thickness of 25 Angstroms formed by a 16Ga0 84N structure and the second layer with a thickness of 25 Angstroms consisting of GaN doped with 1 × 1019 / cm3 of Mg are alternately grown to form an ultra-thin layer with a total thickness of 0.6 μm. The p-side cladding layer of the lattice structure 2 1 8 »Finally, a P-side contact layer 219 made of p-type GaN doped with Mg of 1 × 102 &lt; &gt; / cm3 was grown to a thickness of 150 angstroms. Take the wafer on which the nitride semiconductor layer has been grown as described above out of the reaction container, and form a SiO 2 protective film on the surface of the p-side contact layer 219 on the uppermost layer, and use SiCl4 gas etching using RIE to etch the wafer to form The surface of the n-side contact layer 211 of the side electrode is exposed. Printed by the Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Then form a mask of a predetermined shape on top of the p-side contact layer 219. And the ρ-side cladding layer 218 is etched to form a ridge line with a width of 1 μm, a Zr02 insulating film 221 is formed on the ridge side and the exposed surface of the ρ-side cladding layer 218 so that the top of the ρ-side contact layer 219 is exposed, A wide p-side electrode 220 electrically connected to the p-side contact layer 219 is formed on the insulating film 221. On the one hand, an n-side electrode 223 is formed on the surface of the n-side contact layer 211 exposed by etching.

After grinding the wafer GaN crystal substrate 1000 obtained as described above to be thinner, the GaN crystal substrate 1000 was cleaved to form the resonance surface of the LD element on the cleaved surface thereof. For the wafer, the GaN 75 paper size adopts the Chinese National Standard (CNS) A4 specification (210 cents and 297 mm) A7 B7 406445 V. Description of the invention () The back surface of the substrate 1000 is arranged on a heat sink. The [0] element has a critical current density of 1.5KA / cm2 and continuous laser oscillation at room temperature, and has a lifetime of more than 10,000 hours at an output of 20mW. Also, in this embodiment, the substrate obtained in Example 30 is used to make an LD element, but when the structure of the electrodes of both n and p is taken out from the same side, Examples 31 and The nitride semiconductor substrate obtained in Example 32 was provided with a concentration gradient in the n-type impurity. At this time, the η-side contact layer 2 11 is not required, but is engraved by the last name to expose the movpe junction Ba or HVPE crystal provided with a gradient slope 'to form the η-side electrode 223 on the exposed surface.氺 Example 3 4 On the HVPEGaN crystal surface with the impurity Si concentration gradient obtained in Example 3 1 (the surface opposite to the back surface from which the sapphire substrate 11 was removed), the η-side contact layer 2 11 was not formed, and Example 3 3 Similarly, the crack prevention layer 212, the η-side cladding layer 213, the η-side light guide layer 214, the active layer 2 1 5, the ρ side cover layer 21 6, and the ρ side light guide layer 2 1 7, p Side cladding layer 21 8 and P side contact layer 2 1 9 Next, as in Example 33, the ρ side contact layer 219 and the ρ side cladding layer 218 are etched to form a ridge line with a width of 1 π, and an insulating film is formed. 221. A p-side electrode 220 is formed on the p-side contact layer 219. On the one hand, an n-side electrode 223 is formed on the back surface of the GaN crystal substrate. Then, from the back surface of the GaN crystal substrate, it was ground to a cleavable thickness, and cleavage was performed in the same manner as in Example 33 to prepare an LD device. In this embodiment, although the GaN crystal substrate is polished, because the doped impurity concentration is set to a slope, the exposed surface often becomes the surface doped with a high concentration of N-type impurities in a nitride semiconductor substrate The LD element has approximately the same properties as those in Example 33. 76 This paper size applies to China National Standard (CNS) A4 (210X297 mm) {Please read the notes on the back before filling this page) Order &quot; __ Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs, Consumer Cooperatives

V. Description of the invention () Du Du printed by the Ministry of Economic Affairs of the Central Bureau of Standards and Commerce of the People's Republic of China * Rework Example 35 This example can refer to the 7th circle A to 7B. A sapphire substrate 11 having a main surface composed of a C surface and an ORF surface constituting an a surface was put into a MOVPE reaction vessel. The temperature was set to 510 C, argon was used as the carrier gas, and the raw material gas was ammonia and TMG. On the sapphire substrate 11, a low-temperature buffer layer 12 made of GaN was grown to a thickness of about 200 angstroms. Using TMG and ammonia as the raw material gas, the dopant gas is a silane gas, so that the GaN layer 71 doped with Si at IX 1018 / cm3 is grown to a thickness of 2 μm. Then, a line-shaped photomask is formed on the GaN layer 71, and a first silicon dioxide line having a line width of 15 µm, a line interval of 3 µm, and a thickness of 1 µm is formed using an epitaxy device '. Then, it is etched to a halfway depth of the GaN layer 71 by an RIE apparatus to form a trench 72. The GaN layer 71 is exposed only on the side surface and the bottom surface of the groove 72. Each of the silicon dioxide lines extends in a direction perpendicular to the ORF surface of the sapphire substrate u. After the groove 72 is formed in this manner, the second silicon dioxide is formed on the entire structure including the first silicon dioxide mask, the side surface and the bottom surface of the groove 72 using the sputtering device. Except for the part of the bottom surface of the groove 72 and the upper part of the first silicon dioxide layer, only the side surface of the groove 72 is etched with a mixed gas of CF4 and 02 gas as the etching gas. Thereby, a first growth control mask made of the first and second silicon dioxide is formed on the top surface of the side wall between the adjacent grooves 72, and a second silicon dioxide is formed on the bottom of the groove 73. The second growth control cover 74 is constituted. The wafers having the grooves 72 and the first and second growth control masks 73 and 74 formed in the GaN layer 71 are placed in a MOVPE reaction vessel, and the gas is doped with dopant gas at 1050 ° C and TMG and ammonia Silane gas is used to make 77 paper sizes applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page) Order A7 B7 406445 V. Description of the invention (Doping 1 X 10l8 / cm3 of Si GaN crystal 76 grows 30 divisions thick. Take out the wafer that has grown Si-doped GaN crystal 76 from the reaction container. On the one hand, for comparison, on the sapphire substrate 11, a buffer layer is formed. After the growth of 12, a GaN layer having a thickness of 30 μm was formed thereon as a GaN substrate for comparison. The number of crystal defects of the two NaA substrates was measured and observed with a planar tem. The crystal defects of the GaN substrates of Examples 3 to 5 were measured. The number is 6xi〇6 / cm2, and the number of crystal defects of the GaN substrate used for comparison is 1 X i〇i〇 / em2 β 氺 Example 3 6 Using the method of 35, the bottom layer 12 is grown on the sapphire substrate u and doped. The Si-doped GaN layer 71 is formed by cutting the GaN layer 71 by a cutting method. The same groove 72 in Example 35. A silicon dioxide layer was formed on the entire surface of the obtained structure. 'Only the silicon dioxide on the side surface of the groove 72 was removed by etching to form a first growth covering the top surface of the side wall between the grooves 72. The control mask 73 and the second growth control mask 74 covering the bottom of the trench 72 expose the GaN layer 71 only on the side of the trench 72. Using this wafer, the same method as in Example 35 was used to dope Si The GaN crystal 76 was grown. The number of crystal defects of the obtained GaN crystal substrate 76 was measured, and the same good results as in Example 35 were obtained. The Ministry of Economic Affairs, Bureau of Prototype, Shellfish Consumer Cooperative, Printed Tube, Example 3 7 Except that the etching of the GaN layer 71 is deepened to the sapphire substrate u, the same method as in Example 35 is used to grow the Si-doped GaN crystal 76. The GaN crystal is the same as the crystal of Example 35 and has few crystal defects * FExample 38 This example can refer to Figure 8A to Figure 8C. 78 This paper size is applicable + Chinese National Standard (CNS) A4 specification (210X297 mm) 406445 5. Description of the invention () and Examples 35 The same method, the Si-doped GaN crystal 76 grows 200 μη thickness. The wafer's sapphire substrate ^, the bottom layer 12, the GaN layer 71, and the growth control masks 73 and 74 were removed by grinding to form a single Si-doped GaN crystal substrate. A GaN crystalline substrate (substrate 1000) was placed in a MOVPE reaction vessel of a mOVPE device, and was grown on the surface of the substrate by 1 × 1018 / cm3 of Si doped with 1 × 1018 / cm3. A high-temperature buffer layer 81 made of GaN. Next, a single quantum well structure having a thickness of 20 angstroms is sequentially grown on the high-temperature buffer layer 81. 4Ga. 6n active layer 82, thickness 0.3 cm, p-side cladding layer 83 'composed of Al0.2Ga0.8N doped with Mg lxl02Vcm3 and thickness 0.5 Å, formed of Mg doped with lxl02 / cm3 The p-side contact layer 84 is made of GaN. The wafer on which the nitride semiconductor has been formed in this manner is taken out of the reaction container, and the p-side cladding layer 83 and the p-side contact layer 84 are reduced in resistance at 60 ° C. in a nitrogen atmosphere. Then, the p-side contact layer 84 is reduced from the p-side contact layer 84. The side etching process exposes the surface of the GaN crystal substrate 1000. After the etching, a light-transmissive p-electrode 85 made of Ni / Au and having a thickness of 200 angstroms is formed on substantially the entire surface of the surface of the P-side contact layer 84. On the p electrode 85, a solder base electrode 86 with a thickness of 0.5 pm is formed. It is printed by the Consumer Cooperative of the Central Government Office of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Then, on the back of the GaN crystal substrate 1000 An η electrode 87 having a thickness of 0.5 mm is formed on the entire surface. The obtained wafer is diced from the η electrode 87 side, and the GaN substrate 1000 (M (1100) plane) and a plane perpendicular to the M plane are cleaved. , Made into a 300 呷 square LED chip. The LED emits a 520ππ line of light at 200mA. It is the same as the conventional growth of nitride semiconductor devices on sapphire substrates. 79 This paper is applicable to national standards (CNS) Α4. Specifications (210X297 mm) A7 B7 «06445 V. Hair Explanation () Compared with the manufacturer, the output is more than 2 times, and the electrostatic withstand voltage is more than 2 times, which has excellent characteristics. ---------- Shiyi ----- 1T (please first Please read the notes on the back of the page and fill in this page again.) Example 39 This example can refer to the 10th circle. The same method as in Example 35 is used to grow the 8 doped GaN crystal 76 to 200 mesh thickness. The sapphire substrate bottom layer 12, the GaN layer 71 ', and the growth control masks 73 and 74 of the wafer were polished and removed to form a single Si-doped GaN crystal substrate. The Si-doped GaN crystal substrate (Substrate 1) 〇〇) placed in the MOVPE reaction vessel of the MOVPE device, without forming the buffer layer 211 and the crack prevention layer 212 ', on the surface of the doped GaN crystalline silicon substrate 1000, doped by 1 X 1019 / cm3 The η-side cladding layer 213 of Si. Next, 'On the η-side cladding layer 213, the η-side light guide layer 214 composed of n-type GaN doped with Si of lxl0i7 / cm3 is grown by 0.1 thickness. A well layer with a thickness of 25 Angstroms consisting of InO. 2Ga. 8N doped with 1 X lOi7 / cm3, and a thickness of 50 consisting of InOlGa. Doped with Si 1 x 10 &quot; / cm3. Egypt barrier The layers are alternately grown to form an active layer 215 of a multiple quantum well (Mqw) structure with a total thickness of 175 Angstroms. Large and larger than the active layer, p-type Al0 3Ga made of Mg doped with IX 102 V cm 3. The p-side cap layer 216 made of 9N grows to a thickness of 300 angstroms. Next, its band aging energy is smaller than that of the p-side cap layer 216, and the p-side light guide layer 217 composed of p-type GaN doped with Mg of 1 × 1018 / cm3 is grown to a thickness of 0.1 μm. Then, a P-type Al made of Mg doped with 1 × 1 020 / cm3 was made. The first layer with a thickness of 20 Angstroms composed of 2Ga0.8N, and Mg 80 doped with 1 X l02Vcm3. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇) &lt; 297 Ministry of Economic Affairs Printed by the Central Government Bureau of Work and Consumer Cooperatives A7 406445_B7 V. Description of the invention () p-type GaN is the second with a thickness of 20 angstroms; | Alternatively grown to form a superlattice structure p with a total thickness of 0.4 μm Side cladding layer 218. Finally, a P-side contact layer 219 made of p-type GaN doped with 2 × 102Vcm3 of Mg was grown to a thickness of 150 angstroms. A wafer known to form a nitride semiconductor layer was built in a reaction container in Anneal at 700 ° C in a stupid atmosphere to make the p-type layer lower in resistance. After annealing, the wafer is taken out of the reaction container, and the uppermost p-type contact layer 219 and p-type cladding layer 218 are etched using an RIE device. A ridge portion having a width of 4 lines is formed, and a P-side electrode 220 made of Ni / Au is formed on the entire surface of the top surface of the ridge portion. Next, a p-side package other than the p-side electrode 220 is formed. On the exposed surfaces of the layer 218 'and the contact layer 219, a Si02 insulating film 221 is formed, and p and p are formed on the insulating film 221. Side electrode 220 electrically connected to base electrode 222 «Then, on the substantially entire surface of the back surface of the GaN crystal substrate 1000, a η side electrode 223 made of TI / A1 with a thickness of 0.5 μm is formed, A thin film made of Au / Sn is formed on the upper surface and used for the metallization of the heat sink. Then, the wafer is diced from the η electrode 223, and the M surface ((Π 〇〇)) of the GaN crystal 1000; equivalent to FIG. 3 The side surface of the hexagonal column), the GaN substrate 1000 is cleaved into strips to form a resonance surface. A dielectric multilayer film of Si and Ti02 is formed on either or both of the resonance surfaces, and finally, parallel to the p electrode The elongated body is cut in the direction of the substrate to form a laser wafer. Next, the wafer is faced up (in a state where the substrate and the heat sink face each other) on the heat sink ', and leads are soldered to the base electrode 222. The LD element is placed under room temperature laser oscillation, and it is confirmed that it is below the critical current density of 2.0KA / cm2 and the critical voltage of 4.0V, and continuously oscillates at an oscillating wavelength of 405nm, and has a life of more than 1,000 hours. 81 paper Standards apply to China National Standards (CNS) A4 specifications ( 21〇χ297 mm)

In ^^^^ 1 an n — ^ n K m ^ i n (Please read the precautions on the back before filling this page)

1. 1T Printed by Duty Offset and Consumer Co-operation of the Central Bureau of Standards, Ministry of Economic Affairs 406445 A7-B7 V. Description of Invention () Example 40 This example can refer to Figure 8. When growing GaN crystals, pure crystals were grown by the same method as in Example 35 except that Si was not doped. This GaN crystal 76 (substrate 1000) is used in the production of an element member while being supported by a sapphire substrate n. On the substrate 1000, alternately grow a first layer of 20 angstrom thickness consisting of η-type SN doped with IX 1019 / cm3 Si and a second layer of 20 angstrom thickness consisting of pure GaN. 〇〇 layer to form a super-lattice structure cladding layer 81 with a total thickness of 0.4 μm. On the n-side cladding layer 81, InO 4Ga having a single quantum well structure with a thickness of 20 angstroms was sequentially grown. 6N active layer 82, a thickness of 0.3 and a p-side cladding layer 83 'made of AluGao.sN doped with Mg 1 X 1020 / cm3 and a thickness of 0.5 陴 made of doped lx 1 0 2 0 / cm3 The P-side contact layer 84 made of Mg and GaN. Then, the p-side contact layer 84 is etched to expose the surface of the cladding layer 81, and the cladding electrode 87 is formed on the surface. On one side, a light-transmitting p-side electrode 85 is formed on substantially the entire surface of the p-side contact layer 84, and a solder base electrode 36 is formed thereon. Finally, ‘the sapphire substrate is polished from its back surface to a thickness of about 50 μm, and then diced from the polished surface side’ to make a 350 μm square plastic element. Compared with the LED element of Example 38, the obtained LED element has a 1.5-fold improvement in turn out and an electrostatic withstand voltage of about 1.5-fold. 82 This paper size is applicable to China National Standard (CNS) A4 specification (2. 丨 〇X: 297 mm) (Please read the precautions on the back before filling this page) Order -1 'Consumption for Off-site Work Printed by the cooperative 406445 Αΰ77 Description of the 58th invention () /. [A brief description with circle] Figure 1A ~ Figure 1c: Principles of hafnium compound semiconducting hafnium growth according to the first or second aspect of the invention. Schematic cross section (β) of the sequence description: Schematic cross section of a substrate having a main surface forming a slope, which can be used when growing a nitride semiconductor according to the present invention. Figure 3: A unit cell diagram of the crystal structure of a gaseous semiconductor. Circle 4: Planar circle of the support provided with a linear selective growth mask. Figures 5A and 5B: Schematic cross-sections of a nitride semiconductor growth method according to another aspect of the present invention, explained in the order of the process. β FIG. 6A to FIG. 6C: A schematic cross section of a nitride semiconductor growth method according to another aspect of the present invention, which is described in the order of the processes. Fig. 7A to 7D: A schematic cross-section of the principle of an ideal form of the nitride semiconductor growth method according to the third aspect of the present invention is explained in the order of the processes. Fig. 8A is a schematic sectional circle of a nitride semiconductor light emitting diode element supported on a nitride semiconductor substrate of the present invention. Fig. 8B: Planar circle of the light emitting diode element of Fig. 8A v. Fig. 9: A schematic sectional circle of another nitride semiconductor light emitting diode element supported on the nitride semiconductor substrate of the present invention. Fig. 10 is a schematic sectional view of a nitride semiconductor laser diode element supported on a nitride semiconductor substrate of the present invention. Fig. 11 is a schematic sectional view of another nitride semiconductor electron-emitting diode device supported on a nitride semiconductor substrate of the present invention. Fig. 12 is a schematic sectional view of still another nitride semiconductor laser diode element supported on the nitride semiconductor substrate of the present invention. 83 This paper size is applicable to China National Standard (CNS) A4 (210X29 * 7mm) (Please read the precautions on the back before filling this page)

1T% Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 4Q644F_ B7___ V. Description of the invention () [Comparison table of main components] 10 ... support 11 ... heterogeneous substrate 12 ... bottom layer 13, 13a ~ 13f ... Selection of growth masks 14, 14a ~ 14f ..... Windows 15, 16, 17 ... Nitride semiconductor (crystal) 17a ~ 17e ... Space 71 ... Nitride semiconductor layer 71, 72a to 72f ... Recesses 73 '73a to 73g ... Growth control masks 74, 74a to 74f ... Growth control masks 75, 76 ..... Nitride semiconductor (Crystal) 81 ... Buffer layer 82 ... Active layer 83 ... P-side cladding layer 84 ... P-side contact layer 85 ... P-side electrode 86 ... solder base 87 ... n-side electrodes 113, 113a to U3f ... Selection of growth masks 114, 114a to 114f ........ window 115 '116 ... nitride semiconductor ( (Crystallized) 211.... Buffer layer 213... Η side cladding layer 214... Η side light guide layer 215... Active layer 216... ... ... P-side light guide layer 218 ... .... P-side cladding layer 219 ...... P-side contact layer 220 ... ... P-side electrode 221 ... ...... Insulation mold 222 .......... ρ-side base electrode 223, 223a ~ 223b ... n-side electrode 1000 ... Nitride semiconductor substrate (please read first (Notes on the back then fill out this page)

、 1T Μ_ This paper size applies to China National Standard (CNS) Α4 specification (2 丨 0 × 297 mm)

Claims (1)

Scope of Application for Patent No. 87105333 (Amended on January 18, 89) Liu Nian Li Fan Yuan AS B8 C8 D8 Printing and Convergence of Bayer Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs 1. A method for growing nitride semiconductors, including: It is formed on a support composed of a heterogeneous substrate having a main surface formed of a material different from a nitride semiconductor and having a main surface and a bottom layer formed of a nitride semiconductor provided on the main surface of the heterogeneous substrate.] The first selection process of the window is to select a process for exposing the bottom surface of the support; and (b) using a gaseous Group 3 element source and a gaseous gas source to make the nitride semiconductor From the surface, an engineer who grows to the nitride semiconductor grown on an adjacent window selects the upper surface of the long mask. Two limbs stop 2 · If the scope of patent application is the first! The method of growing nitride semiconductors, "I said the above-mentioned bottom layer and the above-mentioned one! The surface area of the portion covered by the selection growth mask is larger than the area of the bottom layer from the above-mentioned window. | The growth method of the nitride semiconductor in item 2 of the blade range in the blade table is called Γ. The selective growth mask is composed of a plurality of individual lines spaced apart from each other and formed as the above-mentioned brothers, while extending in parallel. 4. If the ratio of the width of the nitride semiconductor system in item 3 of the scope of patent application to the width of the first window above, you are greater than 1 and less than 20. 5. If the scope of patent application is 4 items The ratio of the width of each line in the nitride to the above-mentioned second growth method is greater than 1 and is below. The ratio of the width of each of the lines is 6 · As mentioned in the patent claim No. 3 of the above-mentioned nitride window! Each width is the width of the first window in the nitride semiconductor of the growth method 7 as described in item 6 of the patent application range below 5 inches, and its other paper size is suitable for the scope of patent application No. 87105333 ( (Amended on January 18, 89) Liu Nian Li Fan Yuan AS B8 C8 D8 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative 1. A method for growing nitride semiconductors, including: (a) A first substrate having a plurality of first windows is formed on a support made of a nitride semiconductor material with a main substrate and a heterogeneous substrate having a main surface and a bottom layer formed of a nitride semiconductor provided on the main substrate. Selecting a growth mask so that the underlying surface of the support can be selectively exposed; and (b) using a gaseous Group 3 element source and a gaseous gas source to grow the nitride semiconductor from the surface of the underlying layer exposed Engineers who choose to grow the nitride semiconductor on the upper surface of the adjacent window on the upper surface of the selection mask. Both methods are as follows: 2. The method of growing a nitride semiconductor as described in the patent application No.! The surface area of the bottom layer is selected! The surface area of the portion covered by the growth mask is larger than the area of the bottom layer from the above window. | The growth of nitride semiconductors in item 2 of the blade range in the blade table The method is called Γ selection growth mask, which is composed of a plurality of individual lines that are separated from each other and formed as the above-mentioned "mouth", and extend in parallel. 4. If the ratio of the width of the nitride semiconductor to the width of the first window in item 3 of the scope of the patent application, you are greater than 1 and less than 20. 5. If the scope of the patent application (item 4 of the nitride), the respective widths of the above lines and the above-mentioned second growth method 彳 are greater than 1 and the following. The ratio of the widths of each of the 6 is as described in the above. The widths of the windows are as follows: The width of the first window among the nitride semiconductors in the sixth method of the patent application range on the growth method 7 is 5 or less, and its other paper size is suitable for patent application No. 87105333 Revised Chinese Patent Application Scope (May 90) Patent Application Scope A8 B8 C8 D8 Exempt, positive 丨 ^ ii „tii states' cases!. ;;“ 内;-·. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, I. A method for growing nitride semiconductors, including: (a) A heterogeneous substrate formed of a material of a compound semiconductor and having a bevel main surface having an oblique angle of 0 or less, and a t-support formed of a bottom layer made of a nitride semiconductor and provided on the main surface of the bevel of the heterogeneous substrate 1 A process including a first selective growth mask having a plurality of first windows so that the bottom surface of the support can be selectively exposed; and (b) using a gaseous Group 3 element source and a gaseous nitrogen source to make the nitride semiconductor from the above The engineer from the surface of the bottom layer exposed by the window grows until the nitride semiconductor grown in the adjacent window is integrated on the upper surface of the selective growth mask. 2. The method for growing a nitride semiconductor according to item 1 of the patent application, wherein the heterogeneous substrate is formed as a main surface of a stepped slope. 3. For example, the method for growing a nitride semiconductor according to item 1 of the scope of patent application, wherein the growth of the first nitride semiconductor in the above-mentioned project (b) is performed by an organic metal vapor phase growth method, and further includes: b) Process (c) of growing a second nitride semiconductor on the first nitrided Θ semiconductor grown by a halide vapor growth method. 4. The method for growing a nitride semiconductor according to item 1 of the patent application scope, further comprising: forming a second selective growth mask having a plurality of second windows on the first nitride semiconductor grown in the above process (b). To make the surface of the nitride semiconductor selectively exposed (c); and (Please read the precautions on the back before filling out this page) r--I-m ml. Pack &gt; 1T ir This paper Standards are applicable to Chinese National Standard (CNS) A4 specifications (2 丨 0X297 mm) ABCD No. 8 * 71〇5333 printed by the Consumer Cooperatives of the Ministry of Economic Affairs of the Central Government Bureau of Patent Application (Amended on January 18, 89) mum — Scope of patent application 8. The growth method of nitride semiconductors according to item 3 of the scope of patent application, in which each of the above-mentioned lines has a thickness of 0.01 to 5. .., 9. The method for growing a nitride semiconductor according to item 3 of the scope of the patent application, wherein the heterogeneous substrate is a sapphire substrate or a plate whose main surface is a (00001) surface, and the above-mentioned lines are sapphire substrates. The (1120) plane extends vertically. 10. The growth method of the nitride semiconductor according to item 9 of the scope of the application ° The above-mentioned heterogeneous substrate system is formed as the main surface of the inclined surface. U. The growth method of a nitride semiconductor according to item 10 of the application, wherein the heterogeneous substrate is formed as a main surface of a stepped slope. U · The growth method of nitride semiconductors as described in the third item of the patent application °, wherein the heterogeneous substrate is a sapphire substrate whose main surface is a (1120) surface, and the above lines are directed to the (1102) surface of the sapphire Vertical extension. 1 3 The method for growing a nitride semiconductor according to item 12 of the scope of the patent application, wherein the above-mentioned heterogeneous substrate system is formed as a sloped main surface. M. The method for growing a nitride semiconductor according to item 3 of the scope of the patent application, wherein the heterogeneous substrate is a main surface formed with a stepped slope. 15. The method for growing a nitride semiconductor according to item 3 of the scope of the patent application, wherein the heterogeneous substrate is a spinel substrate whose main surface is a (111) plane, and the lines are directed to the (110) plane of the spinel. Vertical extension. 16. The method for growing a nitride semiconductor according to any one of claims 1 to 15 in the scope of the patent application, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied by a molar ratio of less than 2000. 17. The growth method of a nitride semiconductor according to item 16 of the application, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of j 800 or less. 1 8 · If the method of growing a nitride semiconductor is applied for item 16 of the patent scope ’) (210X29 ^ mm) (Please read the precautions on the back before filling this page) 6. Scope of patent application Among them, the above-mentioned gaseous nitrogen source and gas-off supplier. .-Wind 3 family to source is 15 in molar ratio. . 19. If you apply for the semi-cubic nitride of item 16 in the profit-seeking area, where the above-mentioned gaseous nitrogen source and gaseous ion growth method are provided by the supplier. Xing "... The source is in a molar ratio. The above two. For example, the nitridation of item 19 of the scope of patent application where the gaseous nitrogen source and the gaseous Group 3 element source are in molar tb length ratio: method, supplier. 30 years and over 2 years] · If you apply for the growth of nitride semiconductors under item 6 of the patent application, the first nitride semiconductor n method in the above-mentioned plutonium project belongs to the vapor phase growth method. Gold 22. If the nitride of the scope of patent application No. 21 in which the growth of the above-mentioned nitride semiconductor is: method, reduction of the performer "4UU &amp; The vapor phase growth method of the third compound in the above project is carried out, and further includes: long-growth of the second gaseous semiconductor by the first nitrogen phase growth method grown by the organic metal in the project (b) The former ... Chemical 24. For example, the birth of nitride semiconductors in the scope of the patent application No. 23 The area of the bottom layer covered by the first selective growth mask is larger than that of the bottom layer from the above! Window. Product is the big one. = Leaf surface 25. The growth method of nitride semiconductors such as the 23rd in the scope of application for patents = = The gap is composed of four small ones and a plurality of individual lines extending in parallel. '------- --3 sheets from ^ (21〇ϋΐ : ·: The width of the nitride semiconductor of the 25th in the scope of the patent application: the middle width of each line and the width of each of the above:, are greater than _I, and less than 20. 27. For example, for the nitride semiconductor of scope 26 of the patent application, the ratio of the width of each of the lines to the ratio of the first and second windows is greater than 1 and less than 10. Another I8 ·: Method for Growing Nitride Semiconductors in the 26th Patent Application Scope 2 "Each width of the tV window on the application is 8 ㈣ or less' ~ The above is the growth of a nitride semiconductor in the 26th application patent application f The width of the first window described above is less than 5 and ο · 1- more than 30. For example, the method for growing a nitride semiconductor in the 25th item of the patent application, wherein each of the lines has a thickness of 0.01 to 5 μηι. 31. The method for growing a nitride semiconductor according to item 25 of the application, wherein the heterogeneous substrate is a sapphire mask having a main surface of (0Ό01) plane, and each of the lines is a (112〇) plane of sapphire. The vertical direction is extended ^ 32. The growth method of nitride semiconductors according to item 31 of the patent application, wherein the above-mentioned heterogeneous substrate is a main surface formed as an inclined surface. 33. For example, the nitride semiconductor of item 32 of the patent application A growth method in which the above-mentioned heterogeneous substrate is formed as a main surface of a step-like slope. 34. The growth method of a nitride semiconductor as set forth in the scope of the patent application, wherein the above-mentioned different The substrate is a sapphire or stone substrate whose main surface is a (1120) surface, and the above-mentioned lines extend vertically to the (Π 02) surface of the sapphire. 35. A nitride semiconductor such as the 34th in the scope of patent application A growth method in which the aforementioned heterogeneous substrate system is formed as a main surface of an inclined surface. 36. A method for growing a nitride semiconductor as described in claim 35 of the patent scope, wherein the aforementioned heterogeneous substrate system is formed in a stepped inclined surface The scope of patent application No. 87105333 (Amended on January 18, 1989) — ^ 4 ^ 5 6. Application scope of patent 3: For example, the growth method of gaseous semiconductors under the scope of application for patent No. 25, "The above heterogeneous species The substrate is a spinel 'stone substrate whose main surface is constituted by a 011 plane. Each of the lines described above extends in a direction perpendicular to the) 0 plane of the spinel. 38. If the scope of the application for the patent is 23... ^ ^ Fangbing of the conductor of the county "or 7 of the nitride 4, /, the above-mentioned gaseous nitrogen source and gaseous 3-radiating element 湃 is a supplier with a molar ratio of 2000 or less. Source: If the gaseous nitrogen source of the nitride semiconductor and the gaseous Group 3 element source of the nitride semiconductor of the 38th aspect of the patent application are in a molar ratio-= as the growth method of the gaseous semiconductor of the 38th aspect of the patent application, the above-mentioned gaseous nitrogen Source and supplier in gaseous state. Prime source-150 "= ·: a method for growing nitride semiconductors in the range of 38 patent applications, wherein the above-mentioned gaseous nitrogen source and the gaseous Group 3 Yuanxin supplier. Wu Changyuan has a molar ratio of 10 or more ^ The birth of nitride semiconductors, such as the 38th patent, where the above-mentioned gaseous nitrogen source and gas ionize the supplier. U Zhi-su source is at a molar ratio of 3. The above is printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. The growth method for nitride semiconductors in the 38th item,; == The growth of the first nitride semiconductor is ... Reduction of trust = Please use the method for growing a gaseous semiconductor in the first item of the patent scope. The first gaseous semiconductor that is grown by multiple passes is formed into a second pendulum with a large number of second windows. ϋ, ^ ^ 'The process of growing a mask so that the surface of the first nitride-rich conductor can be selectively exposed; &amp; The favorable range uses a gaseous Group 3 element source and a gaseous nitrogen gas from the exposure of the second window, the second nitride and the fourth one, and the fifth method is the growth method of the gaseous semiconductor of the 44th range. Total of the portion covered by the selective growth mask =: Total table of the bottom layer exposed from the first window: 丨 'amplification of & part of the above-mentioned first nitride semiconductor covered by the second selective growth mask # jy Comment from the top of the address ... It is larger than the total surface area of the exposed portion of the second nitride of the first nitride semiconductor. ?. For example, the growth method of nitride semiconductors in the 45th scope of the patent application, Gap Two! The first and second selective growth masks are separated from each other, during which I :: the first and second windows ... a plurality of individual lines extending in parallel 47. The method for growing a nitride semiconductor, such as the 46th item in the patent application Wherein, a ratio of each width of the line to each width of the window is greater than 1 and less than 20. 48. The method for growing a nitride semiconductor according to item 47 of the scope of the patent application, wherein the ratio of each width of the feeding material to the width of each of the openings is greater than 1 and less than 10. 49. For example, the growth method of an atmosphere semiconductor according to item 47 of the scope of application, wherein the width of the window is less than 8 mm and more than 0 μm. 50. For example, the method for growing a nitride semiconductor according to item 49 of the scope of the application, wherein the width of the window is 5 μm or less, 0.1 μn] or more. 51 _ The growth method of a nitride semiconductor according to item 46 of the application, wherein each of the lines described above has a thickness of 0.01 to 5 μm. This paper scale is applicable to the national standard (CNS) of MF (Second Number 297), printed by quasi% Μ Industrial and Consumer Cooperatives, and the scope of patent application No. 87105333 (as amended in January, 1989) Weighing range 52. If applied A method for growing a gaseous semiconductor according to item 46 of the patent, wherein the above-mentioned heterogeneous substrate is composed of a gemstone board with a main surface of (00 ”face, and the above. Each line is a vertical line of ⑴20 of sapphire) Extending the direction ^ 53. The growth method of nitride semiconductors, such as the 52nd patent application, wherein the heterogeneous substrate is formed with the main surface of the inclined surface. 54. The growth of nitride semiconductors, such as the 53th patent application. Method, wherein the above-mentioned heterogeneous substrate is formed as a stepped main surface of the inclined surface. 55. The method for growing a nitride semiconductor according to item 46 of the patent application scope, wherein the above-mentioned heterogeneous substrate is constituted by its main surface as (1120 ) Surface of the sapphire substrate, and the above-mentioned lines extend in the vertical direction of the (1102) plane of the sapphire. The above-mentioned heterogeneous substrates are formed as the main surface of the inclined surface. 57. For example, the method for growing a nitride semiconductor according to item 56 of the patent application, wherein the above-mentioned heterogeneous substrates are formed as the main surface of the stepped inclined surface. 58. For example, a method for growing a nitride semiconductor according to item 46 of the application, wherein the heterogeneous substrate is a spinel substrate whose main surface is a (111) plane, and the lines are directed to the (110) plane of the spinel. 59. The method for growing a nitride semiconductor according to any one of claims 44 to 58 in the scope of patent application, wherein in the above process (b) and / or process (d), the gaseous source and the gaseous phase 3 The source of the group element is at a molar ratio of less than 2000. 60. The growth method of nitride semiconductors such as the 59th in the scope of patent application, wherein the above-mentioned gaseous nitrogen source and the gaseous group 3 source are at a molar ratio of 1 8 61. If the growth method of nitride semiconductors according to item 59 of the patent application scope, wherein the above-mentioned gaseous nitrogen source and gaseous Group 3 element source are supplied at a molar ratio of 1500 or less, To Suitable country's national scale paper-like fiscal registration (⑽ Shu 21 () &gt; &lt; 297 are well Patent Application No. 87105333 range Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (Revision V8) 6. Application for Patent Scope 62. For the growth method of nitride semiconductors under the scope of the patent application No. 59, the above-mentioned gaseous nitrogen source and gaseous Group 3 element source Suppliers with molar ratios _ above 0. _ 63. For example, the method for growing a nitride semiconductor according to item 59 of the application, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of 30 or more. 64. The method for growing nitride semiconductors as described in item 59 of the Shengu patent, wherein the above-mentioned process (b) and / or the growth of nitride semiconductors in the process is performed by an organic metal vapor phase growth method. 65. The method for growing a nitride semiconductor according to item 64 of the application, wherein the growth of the nitride semiconductor in the above process (b) and / or the process is performed under a reduced pressure of 50 to 400 Torr. 66. A method for growing a nitride semiconductor, comprising: forming a first growth mask having a plurality of selective growth masks on a support including a dissimilar substrate formed of a material different from the nitride semiconductor and having a main surface; A process in which a part of the surface of the support is exposed and the total surface area of the support covered by the first selective growth mask is larger than the surface area of the support exposed from the first window, and (b ) Use a gaseous Group 3 element source and a gaseous nitrogen source to cause the i-th nitride to grow from the surface of the support exposed on the window to the nitride semiconductor grown on the adjacent window on the upper surface of the selective growth mask. Projects up to one person. '67. A method for growing a nitride semiconductor according to item 66 of the application, wherein the first selection growth mask is formed by separating each other and forming the above-mentioned first window, and a plurality of individual lines extending in parallel. . 68 · Growth method of nitride semiconductor such as the scope of application for patent No. 67 (Paper rule) A4. C 锖 Please read the notes on the back and fill in this page) Order ab! (Scope of Patent Application No. 898 ^ 33 (Amended on January 18, 1989) P ^ 4 ^ * 1 Benefits A8 B8 C8 D8 Printed by the Consumer Consumption Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, where the above-mentioned heterogeneous substrate is constituted by its main surface For the “⑴” plane, the above lines are in the vertical direction of the spine ’s ⑴0) plane in the vertical direction. The gaseous semiconductor, the molar ratio of the nitrogen source, and the gaseous Group 3 element source are described in Table 81_. For example, the method for growing nitride semiconductors under the scope of patent application No. 80, the above-mentioned gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of 1. M. Such as the scope of patent application No. 80 nitride A method for growing a semiconductor, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of 1 $ 0. 83_ The growth method of a nitride semiconductor according to item 80 of the patent application scope, wherein the above gaseous state The nitrogen source and the gaseous Group 3 element source are suppliers. U 84 'The growth method of a nitride semiconductor, such as the scope of the patent application No. 80, wherein the gaseous nitrogen source and the gaseous Group 3 element source are molar suppliers. 摩尔υ to 8 5 The method for growing nitride semiconductors according to item 80, wherein the growth of the first nitride semiconductor in the above-mentioned project (b) is carried out by a metal-vapor growth method. 86. For example, the scope of the patent application for the nitride of item 85 The semiconductor growth method, wherein the growth of the above-mentioned nitride semiconductor is a decompression practitioner at 50 to 400 Torr. 87. For example, the method for growing a nitride semiconductor according to item 66 of the application, wherein the above-mentioned project (b) The growth of the first nitride semiconductor is carried out with a metal vapor phase growth method, and further includes: (Please read the precautions on the back before filling out this page) Applicable to China National Standard (CNS) ΑΊ specifications (210X297 mm) The scope of the patent application is that the staff of the Central Interim Bureau of the Ministry of Economic Affairs, the Consumer Cooperative Cooperative Printing Co., Ltd., and the above lines are extended in the vertical direction of the (1102) plane of sapphire (such as the method for growing nitride semiconductors in the scope of patent application 帛 97, / The above-mentioned heterogeneous substrate system is formed as the main surface of the inclined surface. Y. If the method of growing a nitride semiconductor is applied in the scope of the patent application item 98, the above-mentioned heterogeneous substrate system is formed as the main surface of the inclined surface of the step. Ϊ́ · If you ask for a method for growing a nitride semiconductor according to item 88 of the patent, wherein the heterogeneous substrate is a spinel substrate whose main surface is an (ill) surface, and each of the lines is directed to the spinel. (110) The vertical direction of the plane. The extender. 101 · The growth method of nitride semiconductor f in any one of the 87th to the 100th scope of the application for a patent, wherein the gaseous nitrogen source and the gaseous Group 3 element source are Suppliers with a molar ratio of less than 2000. 102. For example, a method for growing a nitride semiconductor in the scope of patent application No. 101, wherein the gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of less than 1,800. = 3. If the method for growing a nitride semiconductor according to item 101 of the patent application scope, the above-mentioned gaseous nitrogen source and the gaseous Group 3 element source are supplied by a molar ratio of less than 1,500. = 4 · Please patent as The method for growing a nitride semiconductor in the range of item 1 () 1, the difluoride gas 1, the nitrogen source, and the gaseous group 3 element source are supplied in a molar ratio of 0. 105. For example, the nitride of the scope of application for the patent No. 101 The semiconductor growth method, the above-mentioned gaseous nitrogen source and the gaseous Group 3 element source are the materials for the supplier. Please refer to the patent for the growth method of nitride semiconductors in the scope of 1Q1. The growth is in the 50 to 400 "walker. (Please read the notes on the back before filling out this card) This paper is suitable for Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives: II: The growth method of nitride semiconductors under the scope of patent No. 66, the military department also includes:. Most of the grown nitride semiconductors are formed with semiconductors: (2) a process for selecting a growth mask so that the surface of the first nitride bovine conductor can be selectively exposed; and (c) a gaseous group 3 element source and a gaseous gas source, so that the second nitride semiconductor is grown to an adjacent window丄; Second == Engineering from the surface of the conductor until the second long nitride semiconductor is integrated on the upper surface of the second long mask. Γ Zhongshen "V: The method for growing a nitride semiconductor in the 107th range, which covers Qiu Er's M2 material semiconductor by the second selective growth mask described above. The "f" surface area is larger than the combined surface area of the exposed portion of the nitride half-window. On page 31, No. 2 109. For example, the scope of application for nitrogen in item No. 108 includes the above-mentioned first and second selection growth masks, each of which is composed of a lead / length method. . And most of the individual lines extending in parallel 110. For example, the nitride semiconductor of the scope of the patent application No. 109 is its width and the width of each of the above :: = = If you ask, please refer to the nitride half of the 1G9 Guide: The width of each of the above-mentioned lines and the width of each of the above-mentioned: is less than 10. The ratio of 114 degrees of view 2 is the nitride semiconductor of the patent range item UG. Among them, each width of the i-th window is less than 8 ceramics. Long method, &quot; 3. The nitride semiconductor of the scope of patent application item 10 Of ::::. Please listen to the precautions first and then page 13. The scope of patent application No. 87105333 (revised on January 18, 1989), the width of the first window in the scope of patent application 2 is less than 5 inches, (M swell above 4 · For example, the growth method of nitride semiconductors in the scope of the patent application No. 109, the above-mentioned each. The line system has a thickness of 0.1 G1 to-^ ^ L15 growth method of nitride semiconductors in the range, The L soil plate is a sapphire plate whose main surface is a (0001) surface, and the above-mentioned lines are ⑴2G) of the sapphire. The vertical extension of the surface = Π6. If the scope of the patent application is 115, the growth of nitride semiconductors In the method, the aforementioned heterogeneous substrate system is formed as a main surface of a slope. = 7. If the method of growing a nitride semiconductor according to item 116 of the patent is requested, the above-mentioned heterogeneous substrate is the main surface of a stepped slope. &quot; 8. A method for growing a nitride semiconductor, such as the application of β-month patent scope item i 09, wherein the heterogeneous substrate is a sapphire substrate whose main surface is constituted as a (1120) surface, and the above-mentioned lines are directed to the sapphire. (1102) The vertical extension of the plane. &quot; 9. The method for growing a nitride semiconductor according to item 118 of the application, wherein the heterogeneous substrate is a main surface formed as an inclined surface. 120. The method for growing a nitride semiconductor according to item n8 of the scope of patent application, wherein the heterogeneous substrate is a main surface formed into a stepped slope. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 121. For example, a method for growing nitride semiconductors under the scope of patent application No. 109, wherein the above-mentioned heterogeneous substrate is constituted by a spinel substrate having a main surface of (111), and Each of the lines described above extends in a direction perpendicular to the (no) surface of the spinel. 122. The method for growing a nitride semiconductor according to any one of the claims 107 to 121, wherein in the above-mentioned project (b) and / or engineering project: the gaseous nitrogen source and the gaseous Group 3 element source are Suppliers with molar ratios below 2000. = 3 • If the method for growing a nitride semiconductor according to item 122 of the patent application scope, wherein the above-mentioned gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of less than 800. 如 · If the nitride semiconductor of item 122 of the scope of the patent application == the gaseous nitrogen source and the gaseous Group 3 element source are in a molar ratio of 15 ~ U5. For the growth of the nitride semiconductor of the scope of the patent application item 122, the above-mentioned gaseous nitrogen Sources and sources of gaseous Group 3 elements are 'providers. Dry 1 υ or more 126. For example, please refer to the growth of nitride semiconductors in item 122 of the patent scope ". The above gaseous gas source and gaseous group 3 element source are supplied in a molar ratio. The method for growing a nitride semiconductor: The birth of the nitride semiconductor in the above process (b) and / or (d) is performed by an organic metal vapor phase growth method. 128. If the scope of application for patent is 122 A method for growing a nitride semiconductor, wherein the growth of the nitride semiconductor β in the above process (b) and / or process (d) is performed under a reduced pressure of 50 to 400 Torr. 疋 129. Growth of a nitride semiconductor A method comprising: (i) forming a nitride semiconductor on a support comprising a heterogeneous substrate formed of a material different from a gaseous semiconductor and having a main surface; printed by an employee consumer cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Read the precautions on the back of the mackerel before filling in this page) r 形成 Form a large number of recesses in the vaporized semiconductor, so that the bottom of the recess = is a process that is substantially parallel to the surface of the support; ⑷ A process of selectively forming a first growth control mask 'on the top surface of the nitride semiconductor' to allow the nitride semiconductor layer to be selectively exposed from the side of the recess; and?) Using a gaseous Group 3 element source and gaseous nitrogen Source, the process of growing a nitride semiconductor from the exposed surface of the nitride semiconductor layer. 130. For the growth method of nitride semiconductors under the scope of application for patent No. 129, this paper standard (CNS) A4 ^ (21GX297) The scope of patent application No. 87105333 (Amended on January 18, 89) M44F 6. The scope of patent application where the above-mentioned recesses are separated from each other. The growth method constructed by most individual grooves that extend in parallel is a separate wall, and Individual in. For example, the above-mentioned most individual grooves of the nitride semiconductor in the 130th scope of the application for a patent, the first selective growth mask is formed by a plurality of intermediate grooves formed therebetween. 2 As mentioned above, the total surface area of the nitride semiconductor of item 131 of the patent = top = the first growth control mask is larger than the total surface area of the bottom surface of the above-mentioned groove method 133. If the method for growing a nitride semiconductor in the 132nd scope of the patent application is applied, the width of each of the individual dogmas and the width of each of the grooves are greater than 1 and less than 20. Also, the ratio is U4. The birth of the nitride semiconductor of the 33rd item, wherein the ratio of the width of each of the individual lines to the width of each of the grooves is greater than 1 and less than 10. ', ⑴. For example, the scope of application for patent 帛 131 nitride A method for growing a semiconductor, wherein the depth of each of the grooves is between 500 Angstroms and 5 μm. U6. A method for growing a semiconductor semiconductor, such as the scope of application for patent No. 131, wherein the heterogeneous substrate is constituted by its main surface as (0001 ) Surface of the sapphire substrate, and each of the lines is a vertical extension of the (1120) surface of the sapphire. 137 • The method of living dance of nitride semiconductors according to item 131 of the patent application scope, wherein the heterogeneous substrate is a sapphire substrate whose main surface is a (1120) surface, and the above lines are directed toward the sapphire (丨 102 ) Surface extends vertically. 1 3 8. The method for growing a nitride semiconductor according to item 13 of the scope of patent application, wherein the above-mentioned heterogeneous substrate is a spinel substrate whose main surface is a (111) plane, and the above lines are directed toward the spinel The (1 1 〇) plane of the vertical extension. A8 B8 C8 D8 Patent Application No. 87105333 (Amended on January 18, 89) Patent Application Fan Gumn! Nitrogen semi-s method of any one of 129 ~ 138, in which the above-mentioned gaseous nitrogen source and gaseous Suppliers of Group 3 element sources with a β 'molar ratio of 2p00 or less.疋 Μ: 40 If the scope of the patent application is applied, the growth of nitride semiconductors with 139 items will be provided in the "Group 3 ^ source in a molar ratio of two. For example, the birth of nitride semiconductors with the application scope of 139 items, the above-mentioned gaseous nitrogen sources And gaseous Group 3 element source is the next supplier. The method of growth of nitride semiconductors with a range of 139 in the range of 1500 to 2 is the supplier. The source and the delayed Group 3 element source are in a molar ratio of 1. .The above example please refer to the nitride semiconductor of item 142 of the patent scope ::; the source of the tank and the source of the gaseous Group 3 element are 'in molar ratio :: up v} Practitioner of the growth method. Chang Jiu uses organometallic gas. 145. If printed by the Central Standards Bureau of the Ministry of Economic Affairs, the Ministry of Economic Affairs, the Central Standards Bureau, and the Consumer Cooperatives, the above-mentioned growth of gaseous semiconductors is :: The growth method. M6 under reduced pressure • For example, the nitride half of the 129th scope of the patent application ... which is doped in the 1st and / or 2nd nitride semiconductor-long method '1 47 η-type impurities. "Section 146 of the scope of patent application Half of the above-mentioned η-type impurity doped nitride, based on the tank so that 'a doping concentration smaller person. Types of substrates of ', open', the standard of this paper is ~~-A8 B8 C8 D8 Patent Application Fan Yuanqiao No. 87105333 Application Patent Scope (Revised January 18th) -IQMiS. 148 · If the scope of patent application is No. 129 The method for growing a nitride semiconductor according to the above item, wherein the process (c) further includes:-forming a second nitride semiconductor on the bottom surface of the concave portion so that the nitride semiconductor can be selectively exposed from the side surface of the concave portion; . 149 • A method for growing a nitride semiconductor according to item 148 of the scope of patent application ', wherein the above-mentioned recesses are separated from each other and are formed by numbers extending in parallel. Furthermore, if the growth method of a nitride semiconductor according to item 14 of the patent application range is 15, the above-mentioned most individual grooves are formed by a plurality of individual walls formed therein, and the above-mentioned first selective growth mask is formed by Lines on the top surface of individual walls. 1 5 1. The method for growing a nitride semiconductor according to item 150 of the scope of the patent application, wherein the exposed portion of the nitride semiconductor from the side of the recess has a thickness of 1000 angstroms or more. 152. The method for growing a nitride semiconductor according to claim 150, wherein the exposed portion of the nitride semiconductor from the side of the recess has a thickness of 1 to 10 μm. 1 53. The method for growing a nitride semiconductor according to item 150 of the scope of the patent application, wherein the heterogeneous substrate is a sapphire substrate whose main surface is a (0001) surface, and the above-mentioned lines are sapphire (112) The surface extends vertically. 154. For the method for growing nitride semiconductors in the scope of application patent No. 50, where the aforementioned heterogeneous substrate is a sapphire substrate whose main surface is a (1120) surface, and the above-mentioned lines are directed to the sapphire (1102 ) Surface extends vertically. 155. For example, a method for growing a nitride semiconductor in the scope of application patent No. 50, wherein the heterogeneous substrate is a spinel substrate whose main surface is a (111) surface, and the lines described above are directed toward the spinel (丨丨 0) The vertical extender of the plane. The paper scale is in use_ 家 彳 Monument (CNS) A4 · (21Dx297) (Please read the precautions on the back before filling out this page), 1T * Printed by the Central Bureau of Standards, Ministry of Economic Affairs, and Industrial Consumer Cooperatives. 18 Patent Application Range / No. 156. For example, the scope of patent application for Lin / 147, 148, 149, 150 ⑴, m, or 155 semiconductor growth methods, where upper = gaseous nitrogen source and gaseous. Group 3 elemental source is at a molar ratio of 200. 〇 The following is for 157. For example, the method for the birth and growth of gaseous semiconductors under the scope of application for patent No. 156, wherein the above-mentioned gaseous nitrogen source and gaseous Group 3 element source are supplied by friction. U &gt; 158. For a method for growing a nitride semiconductor according to item 159 of the application, wherein the above-mentioned gaseous nitrogen source and the gaseous Group 3 element source are supplied at a molar ratio of less than or equal to 5%. 159. For the method for growing a nitride semiconductor according to item 156 of the application, wherein the gaseous nitrogen source and the gaseous Group 3 element source are suppliers. Dry i υ or more 160. For example, the method for growing a nitride semiconductor according to the scope of application for patent No. 156, wherein the gaseous nitrogen source and the gaseous Group 3 element source are the supplier.卞 υ Μ 上 161. For example, the method for growing a nitride semiconductor in the scope of application for patent No. 156, wherein the growth of the nitride semiconductor in the above-mentioned process is performed by an organic metal gas phase growth method. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 162. For the growth method of nitride semiconductors under the scope of application for patent No. 161, the growth of the above nitride + conductor is in the range of 50 to 400 trustees. 163. For the method of growing nitride semiconductors under the scope of application for patents Nos. 148, 149, 150, 15 and 152, 153, 154, 155, 157, 158, 159, 160, 161, or 162, wherein the above-mentioned project (d) is It also includes those doped with n-type impurities during the growth of nitride semiconductors. 164. If you apply for the growth method of nitride semiconductors under the scope of patent application No. 163, 'A8 B8 C8 D8 H105333, please apply for the patent scope (as amended on January 8, 1989) ^ 445 — _,-scope of patent application =: =: impurities The doping is to make the doping concentration smaller as it moves away from it. IS is a nitride semiconductor substrate, which is composed of a first main surface and a second Sift semiconductor crystal. It is relatively close to the first two or close to the first main surface. The difference between the two main areas is relatively small. _ The nitride semiconductor substrate of the profit range of item 165 ... On the surface of the main surface, there is an uneven sentence in the second region where the crystal defects are relatively large and the crystal defects are relatively large. Domain The gaseous semiconductor substrate with the scope of patent application No. 165, wherein the nitride semiconductor substrate has a thickness of 78 μm or more. ⑹.- a kind of nitride semiconductor substrate 'which is composed of the crystals of the F-substance conductor with the second main surface], and the crystal defect of the surface area of the first main surface is 1 X 105 / cm2 The following. 169. The nitride semiconductor substrate according to claim 168, wherein the nitride semiconductor substrate is doped with n-type impurities. In the case of a nitride semiconductor substrate of Chinese Patent Application No. 169, the n-type impurity has a concentration gradient in the substrate. Eight Medium The nitride semiconductor substrate of item No. 168 of the patent scope, wherein the above nitride semiconductor substrate is grown by a vapor phase growth method. 172. A nitride semiconductor device comprising a nitride semiconductor device structure supported by a nitride semiconductor substrate according to any one of 171 of the patent application scope. Article 173. If the vaporized semiconductor device according to item 172 of the patent application scope, the above nitride semiconductor substrate is supported by a dissimilar substrate formed of a material different from the nitride semiconductor. A8 B8 C8 D8 No. 87105333 Patent Application Range (Amended January 18, 89) __406445_ Patent Application Range 174.-A method for growing a nitride semiconductor, comprising: growing a nitride semiconductor on a support containing a dissimilar substrate Then, the nitride semiconductor is used as a seed crystal, and a new nitride semiconductor is substantially grown only in the lateral direction while suppressing its longitudinal growth, and then is grown in the longitudinal and lateral directions to obtain the An integrated nitride semiconductor crystal is formed over the entire surface. (Please read the precautions on the back before filling out this page.) Order 21 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) Patent Application No. 87105333 Amended version of patent application scope (May 90) Patent application scope A8 B8 C8 D8 Exempt, positive 丨 ^ ii „tii states' cases!. ;;“ 内;-·. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, I. A method for growing nitride semiconductors, including: (a) A heterogeneous substrate formed of a material of a compound semiconductor and having a bevel main surface having an oblique angle of 0 or less, and a t-support formed of a bottom layer made of a nitride semiconductor and provided on the main surface of the bevel of the heterogeneous substrate 1 A process including a first selective growth mask having a plurality of first windows so that the bottom surface of the support can be selectively exposed; and (b) using a gaseous Group 3 element source and a gaseous nitrogen source to make the nitride semiconductor from the above The engineer from the surface of the bottom layer exposed by the window grows until the nitride semiconductor grown in the adjacent window is integrated on the upper surface of the selective growth mask. 2. The method for growing a nitride semiconductor according to item 1 of the patent application, wherein the heterogeneous substrate is formed as a main surface of a stepped slope. 3. For example, the method for growing a nitride semiconductor according to item 1 of the scope of patent application, wherein the growth of the first nitride semiconductor in the above-mentioned project (b) is performed by an organic metal vapor phase growth method, and further includes: b) Process (c) of growing a second nitride semiconductor on the first nitrided Θ semiconductor grown by a halide vapor growth method. 4. The method for growing a nitride semiconductor according to item 1 of the patent application scope, further comprising: forming a second selective growth mask having a plurality of second windows on the first nitride semiconductor grown in the above process (b). To make the surface of the nitride semiconductor selectively exposed (c); and (Please read the precautions on the back before filling out this page) r--I-m ml. Pack &gt; 1T ir This paper The standard is applicable to Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) A8 Βδ C8 D8 The patent application scope of the Central Sample Rate Bureau of the Ministry of Economic Affairs printed by the Industrial and Commercial Cooperatives uses the gaseous group 3 element source and gaseous nitrogen source, making A process in which a nitride semiconductor is grown from the surface of a second nitride semiconductor exposed in the second window, and the second nitride semiconductor grown in an adjacent window is integrated on the upper surface of the second selective growth mask. By. 5. If the method for growing a nitride semiconductor according to item 4 of the scope of patent application, wherein the total surface area of the bottom layer covered by the above-mentioned selective growth mask is greater than that of the bottom layer exposed from the first window The total surface area is large, and the total surface area of the first nitride semiconductor covered by the second selective growth mask is larger than the total surface area of the first nitride semiconductor exposed from the second window. By. 6. If the growth method of nitride semiconductor is applied in item 5 of the patent scope, the above-mentioned first and second selective growth masks are separated from each other, and the gap is formed in parallel with the above-mentioned first and second windows. Most of the individual lines that extend. 7. The growth method of nitride semiconductors as described in item 4 of the scope of the patent application, wherein the growth of the above-mentioned processes (b) and / or (d) of the &lt; semiconductor semiconductor is performed by an organic metal vapor phase growth method. 8. A method for growing a nitride semiconductor, comprising: (a) a support comprising a heterogeneous substrate formed of a material different from that of the nitride semiconductor and having a beveled main surface with a bevel angle of 0 or less 1 ' Forming a first window with a large number of first selection growth masks' to expose a part of the surface of the support body, and to select the support body 2-This paper size applies the Chinese National Slope (CNS) A4 specification ( 2 丨 〇 &gt; &lt; 297 (published) (Please read the precautions on the back before filling in this page) Pack-* 1T Scope of patent application: Projects in which the surface area of the knife covered by the growth mask printed by the Central Bureau of Standardization, Ministry of Economic Affairs, Shellfish Consumer Cooperative is greater than the surface area of the support exposed from the "port", and (b) Using a gaseous Group 3 element source and poor energy: A Lie Nitrogen source 'causes the first nitride semiconducting bone bean to grow from the surface of the support body exposed at the * opening of the window to the point where the adjacent window grows. The process until the nitride thousands of conductors are integrated on the upper surface of the selective growth mask. 9. A method for growing a nitride semiconductor, including: (a) It contains 1% IL compound + respect different from Weng Fuyu A process of forming a nitride semiconductor on a supporting silicon substrate of a heterogeneous substrate having an oblique angle θ of 1 ° or less &gt; Gen. II, lower &lt; beveled surface; and (b) a nitride semiconductor A process of forming a plurality of recesses so that the bottom surface of the recesses is substantially parallel to the surface of the support body; (c) selectively forming an i-th length control mask on the top surface of the hafnium nitride semiconductor to make the nitride Selectable semiconductor layer A project that is exposed from the side of the recessed portion; and (d) a project that uses a gaseous Group 3 element source and a gaseous nitrogen source to cause a nitride semiconductor to grow from the exposed surface of the nitride semiconductor layer. In the method for growing a nitride semiconductor according to item 9, the above-mentioned heterogeneous substrate is formed as a main surface of a stepped slope. 11. As described in the method for growing a nitride semiconductor according to item 9 of the above patent (c), It further includes: a second growth control mask is formed on the bottom surface of the concave portion so that the nitride semiconductor can be selectively exposed from the side of the concave portion. It (please read the precautions on the back before filling this page). 1T -3- This paper uses Chinese National Standard (CNS) Α4 standard (210 × 297 mm) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, $ L A8 B8 C8 -----————__ ^ ___ VI. Apply for Satoshi ^-12. If the method of growing a nitride semiconductor according to item u of the patent application, wherein the above-mentioned recesses are composed of a plurality of individual samples separated from each other and extending in parallel "S 13 · patent The method for growing a nitride semiconductor in the U-th item, wherein the plurality of individual grooves are formed by a plurality of individual walls in the middle, and the first selection growth mask is composed of individual lines formed on the top surface of each of the individual walls. For example, the method for growing a nitride semiconductor according to item 13 of the patent application, wherein the total surface area of the first growth control mask is greater than the total surface area of the bottom surface of the groove. A method for growing a nitride semiconductor, wherein each depth of the groove is between 500 Angstroms and 5 μm. 16. The method for growing a nitride semiconductor according to item u of the patent application, wherein the exposed portion of the nitride semiconductor from the side of the recess has丨 ⑽Thickness above 10 μm. 17_ The method for growing a nitride semiconductor according to item 9 of the scope of the patent application, wherein the above-mentioned engineering system further includes: doping an n-type impurity in the growth of a nitrogen β semiconductor. 18. For example, a method for growing a nitride semiconductor according to item 17 of the application, wherein the doping of the η-type impurity is such that the more it leaves the heterogeneous substrate, the smaller its doping concentration. 19. For a nitride semiconductor growth method according to any one of claims 1, 4, or 9, in which the growth mask of the above-mentioned bottom layer is selected in the above-mentioned line -4- (please read the note on the back first) (Fill in this page again) Packing, 1T IV This paper size is applicable to China's national rubbing rate (〇 阳) eight 4 rules &gt; Luo (2 丨 〇 &gt; &lt; 297 mm) A8 B8 C8 D8 Central Bureau of Standards, Ministry of Economic Affairs The total surface area of the part printed by the consumer consumer cooperative and covered by the patent application area is greater than the total surface area of the bottom layer exposed from the first window. 20_ The growth method of nitride semiconductors according to item 19 of the scope of the patent application, wherein the above-mentioned first selective growth mask is composed of a plurality of individual lines spaced apart from each other, forming the above-mentioned first window, and extending in parallel. The ratio of the width of the lines to the width of the first window is greater than 1 and less than 20. 21. For the method for growing a nitride semiconductor according to item 9 of the application, wherein each width of the first window is 8 μm or less and 0.1 μm or more. 22. The method for growing a nitride semiconductor according to item 20 of the patent application, wherein each of the lines described above has a thickness of 0.001 to 5 μm. 23. For example, a method for growing a nitride semiconductor according to the scope of application for patent No. 20, wherein the above-mentioned substrate of the Dan type is a sapphire substrate whose main surface is configured as a (001) surface, and the above-mentioned lines are of sapphire (丨G0) Extender in the vertical direction of the plane. 24. For example, a method for growing a nitride 'semiconductor of the scope of application patent No. 20, wherein the above-mentioned heterogeneous substrate is a sapphire substrate whose main surface is configured as a (m〇) plane, and the above-mentioned lines are directed toward the sapphire (1) 〇2) Extender in the vertical direction of the surface "25. For example, the method for growing a nitride semiconductor according to item 20 of the patent application range, wherein the above-mentioned heterogeneous substrate is a spinel substrate whose main surface is a (丨 丨 丨) surface, The above lines are perpendicular to the (丨 1〇) side of the spinel (please read the precautions on the back before filling in this page). * 1T · ν -5- Ministry of Economic Affairs Printed by Consumer Cooperatives A8 B8 C8 --------- _D8 者 Those who have applied for a patent. 6. The method for growing a nitride semiconductor as claimed in item 9 of the patent scope, wherein: in the above process, the growth of the nitride semiconductor is performed by an organic metal vapor phase growth method. 27. The method for growing a nitride semiconductor according to item 3 of the application scope, wherein those who earn dopant impurities during the growth of the first and / or second nitride semiconductor. 28. The method for growing a nitride semiconductor according to item 27 of the scope of the patent application, wherein the doping of the n-type impurity is such that the doping concentration is smaller as it leaves the heterogeneous substrate. 29 .: A kind of nitride semi-conductor substrate, which is on a heterogeneous substrate having an oblique surface below the oblique angle, has a bottom layer formed of a nitride semiconductor obtained by an organic metal vapor phase growth method, and uses the heterogeneous substrate and The bottom layer is a support. The support has a first selective growth mask having a plurality of first windows, and selectively exposes the bottom surface of the support. The first nitride semiconductor is provided from the window. From the surface of the exposed bottom layer, the nitride semiconductor grown by an organic metal 'vapor phase growth method until the nitride semiconductor grown on the adjacent window is integrated on the upper surface of the selective growth mask, and has a second nitride semiconductor, It is based on the above-mentioned first nitride semiconductor, and is grown by a fungal vapor phase growth method, wherein the second nitride semiconductor is composed of a nitride semiconductor crystal having a first main surface and a second main surface. There are relatively many crystal defects in the area close to the first main surface, and the area close to the second main surface is -6- This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page.) Scope of patent application for 1T, 1T. The crystal defects printed by the Central Government Bureau of the Ministry of Economic Affairs of Shellfish Consumer Cooperative are relatively few. 30. For example, please refer to the nitride semiconductor substrate according to item 29 of the patent. In the surface of the first main surface, there is a first region with relatively few crystal defects = a second region with relatively large crystal defects The existence of non-uniformity 31. For example, the nitride semiconductor substrate according to item 29 of the application, wherein the above nitride semiconductor substrate has a thickness of 70 μm or more. 32. For example, the nitride semiconductor substrate with the scope of patent application No. 29, which is composed of nitride semiconductor crystals having first and second main surfaces, and the crystal defect in the surface area of the first surface is 1 X l 〇5 / cm2 or less. 33. The nitride semiconductor substrate according to item 29 of the application, wherein the nitride semiconductor substrate is doped with n-type impurities. 34. The nitride semiconductor substrate according to item 33 of the application, wherein the π-type impurity has a concentration gradient in the substrate. 35. A nitride semiconductor device including a nitride semiconductor device structure supported by a nitride semiconductor substrate according to any one of claims 29 to%. ν 36. For the nitride semiconductor device under the scope of application for patent No. 35, wherein the above nitride semiconductor substrate is made of a material different from that of the nitride semiconductor, please be informed by a heterogeneous substrate formed by λ. National Ladder Standard (CNS) Α4 specification (210 × 297 public envy)