TW406139B - Isolated protection process of the copper metal - Google Patents

Isolated protection process of the copper metal Download PDF

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TW406139B
TW406139B TW88102268A TW88102268A TW406139B TW 406139 B TW406139 B TW 406139B TW 88102268 A TW88102268 A TW 88102268A TW 88102268 A TW88102268 A TW 88102268A TW 406139 B TW406139 B TW 406139B
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layer
copper metal
etching
item
patent application
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TW88102268A
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Chinese (zh)
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Jung-Shi Liou
Jen-Hua Yu
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Taiwan Semiconductor Mfg
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Abstract

This invention provides an isolated protection process of the copper metal, which comprises the steps of: (a) providing a semiconductor substrate having a copper metal layer thereon; (b) forming a liner layer and a etching stop layer on the copper metal layer sequentially, wherein the adhesion of the liner layer toward the copper is better than that of the etching stop layer; and (c) depositing an inter metal dielectrics or a passivation layer on the etching stop layer. This invention improves the problem of poor adhesion between the etching stop layer (such as SiON) and the copper metal and maintains excellent etching stop ability on the same time.

Description

五、發明說明(1) 本發明是有關於半導體製程技術,且特別是有關於一 種銅金屬之隔絕保護製程,用以避免傳統製程的剝離問 題’同時保有良好的蝕刻終止能力。 在Θ半導體積體電路的蝕刻製程中,蝕刻終止層(Etch 〇 P )疋.種;1¾被使用的技術,利用被姓刻層與钱刻終止 層之間明顯的蝕刻選擇比,可確保蝕刻程序的精確度,並 可應用在自動對準接觸窗(SAC)製程中,具有放寬操作範 圍的,效。惟選用蝕刻終止層時,除了考慮蝕刻選擇比之 配合上下方材料層的性冑,以及事後去除時的方 便/、否來作整體性考量,方不至於產生新的問題。 由於一般濕式去光阻所用的溶劑(ACT 69〇)會腐蝕銅 金屬,因此,為了避免銅導線遭到濕式剝除劑的腐蝕,在 銅製程中無論是進行介層窗的蝕刻或是銲墊窗口的蝕刻, 銅導線上都需要一層適當的蝕刻終止層以將蝕刻先行中 =’並在其保護下將光阻錢完畢冑,才 其下的銅導線。 一般而言,氮氧化矽(SiON)比氮化石夕(SlN)更適合用 =為㈣終止層的材料H在鋼導線上使用氣氧化 =來^㈣終止層’ Μ因若干的問題而影響到銅製程 :::度。究其原』,乃是由於氮氧化石夕直接沈積在銅金 ^時,會將銅金屬氧化而在表面出現氣泡狀的缺陷,這 :氧化銅除了會提高電阻值外,帛會影響到介電質對銅金 屬的附著能力,往往致使介電質在後續的熱循環(thermal cycle)中出現剝離(delamination)的情形。因此,在不影 第4頁 五、發明說明(2) 響蝕刻終止層 離現象,便是 有鑑於此 隔絕保護製程 触刻終止能力 為達上述 之前,先在銅 層來改善氮氧 明的方法,其 上具有一銅金 以及一餘刻終 終止層較佳; 在目前已 材質。雖然氮 但疋氮化石夕沈 此在銅介面上 去除上的方便 好小於1 ο ο 〇埃 的隔絕作用為前提下’如何能避免上述的剝 本發明之著眼點所在。 ’本發明的主要目的就是提供一種銅金屬之 ’以解決上述的剝離問題,同時保有良好的 0 目的,本發明的方法係在蝕刻終止層的沈積 金屬上沈積一層較薄的襯墊層,藉由此襯墊 化矽與銅金屬附著性不佳的問題。根據本發 主要步驟包括:(a)提供—半導體基底,其 屬層;(b)於銅金屬層上依序形成一襯墊層 止層,其中襯墊層對銅金屬的附著性比蝕刻 以及(c)於蝕刻終止層上形成一介電層。 知的材料中’氮化矽是—個較適當的襯墊層 化石夕作為蝕刻終止層的特性不妒氮氧化矽, 鋼金屬上卻不會有氣泡缺降的問題,因 2著性質也較氮氧化石夕為佳。料,為了 。降低對產能的影響,此襯蛰層的厚度最 在上述方法中,牛碰 間介電層(IMD)或驟(c)所述的介電層町以是一金屬 續介電層或銲墊窗1 口"(Passivati〇n),因此’為了完成後 列步驟:(d)以—/的餘刻’在步驟(C)之後玎更包括下 口,露出其下之蝕p且為罩幕,蝕刻介電層以形成一開 五、發明說明(3) 4061〇^ 層。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 圖式之簡單說明 第卜4圖為一系列剖面圖,用以說明本發明一較佳實 施例之銅製程。 符號說明 1 0〜介電層; 1 2〜銅金屬層; 1 4〜襯墊層; 1 6〜姓刻終止層; 1 8〜金屬間介電層或護層; 2 0〜光阻; 2卜開口; 23〜介層窗或鲜塾窗口。 實施例 首先請參照第1圖,其顯示本實施例之起始步驟。圖 中10為一内層介電層(ILD)或金屬間介電層(IMD),在介電 層1 0以下的部分,可能包含數層金屬内連線與數個電性上 相互連接的半導體元件,如MOS電晶體、電阻、邏輯元件 等,為方面起見,圖中僅繪出介電層10以上的部分,而介 電層10以下的半導體基底與積體電路元件由於非關本發明 之重點,在此予以省略。V. Description of the invention (1) The present invention relates to semiconductor process technology, and in particular, to a copper metal isolation and protection process to avoid the peeling problem of the traditional process' while maintaining a good etching termination capability. In the etching process of the Θ semiconductor integrated circuit, the etch stop layer (Etch 〇P) 种. Species; 1¾ used technology, using the obvious etch selection ratio between the engraved layer and the money etch stop layer, can ensure the etching The accuracy of the program can be applied in the process of automatic alignment contact window (SAC), which has the effect of widening the operating range. However, when selecting the etching stop layer, in addition to considering the etching selection ratio in combination with the properties of the upper and lower material layers, and the convenience / non-removal of subsequent removals for overall consideration, it will not cause new problems. Since the solvent (ACT 69〇) commonly used in wet photoresist will corrode the copper metal, in order to prevent the copper wire from being corroded by the wet stripping agent, whether it is the etching of the interposer window or the copper process, For the bonding pad window etching, a suitable etch stop layer is required on the copper wire so that the etching can be performed in advance = 'and the photoresist is finished under the protection of the copper wire. Generally speaking, silicon oxynitride (SiON) is more suitable than silicon nitride (SlN). The material used for the termination layer is H. The use of gas oxidation on steel wires to stop the termination layer is affected by several problems. Copper Process ::: Degree. The reason is that when oxynitride is directly deposited on copper and gold, it will oxidize the copper metal and cause bubble-like defects on the surface. This: In addition to increasing the resistance value, copper oxide will affect the dielectric The ability of an electric substance to adhere to copper metal often causes the dielectric substance to delaminate in a subsequent thermal cycle. Therefore, without affecting page 5 of the fifth, the description of the invention (2) the phenomenon of delamination of the etching stop, in view of this, the method of improving the nitroxamine in the copper layer before the termination of the isolation and protection process has reached the above-mentioned method, It is better to have a copper gold on it and a termination layer for a while; it is currently made of material. Although it is nitrogen, the hafnium nitride is easy to remove on the copper interface, and the insulation effect is less than 1 ο ο 〇 Angstrom. The premise of the present invention is how to avoid the above-mentioned peeling. 'The main purpose of the present invention is to provide a copper metal' to solve the above-mentioned peeling problem while maintaining a good 0 purpose. The method of the present invention is to deposit a thin liner layer on the deposition metal of the etch stop layer. As a result, the problem of poor adhesion between silicon and copper metal is padded. The main steps according to the present invention include: (a) providing a semiconductor substrate, a layer thereof; (b) sequentially forming a pad layer stop layer on a copper metal layer, wherein the adhesion of the pad layer to the copper metal is better than etching and (C) A dielectric layer is formed on the etch stop layer. Among the known materials, 'silicon nitride is a more suitable liner layer. The characteristics of the etch stop layer are not jealous of silicon oxynitride, but there is no problem of bubble drop on the steel metal. Nitrogen oxide is better. Material, in order to. Reduce the impact on productivity. The thickness of this lining layer is the most in the above method. The dielectric layer (IMD) or the dielectric layer described in step (c) is a metal continuous dielectric layer or pad. Window 1 (Passivati〇n), so 'in order to complete the next steps: (d) with the remainder of-/', after step (C), it also includes a lower mouth, which exposes the underlying erosion p and is a mask. The dielectric layer is etched to form a layer as described in (3) 4061〇 ^. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings FIG. 4 It is a series of cross-sectional views for illustrating a copper manufacturing process according to a preferred embodiment of the present invention. DESCRIPTION OF SYMBOLS 10 to dielectric layer; 12 to copper metal layer; 1 to 4 liner layer; 16 to etch stop layer; 18 to intermetal dielectric layer or protective layer; 2 to photoresist; 2 Bu opening; 23 ~ interstitial window or fresh window. Example First, please refer to FIG. 1, which shows the initial steps of this example. 10 in the figure is an inner dielectric layer (ILD) or an intermetal dielectric layer (IMD). The portion below the dielectric layer 10 may include several layers of metal interconnects and several electrically connected semiconductors. Components, such as MOS transistors, resistors, logic components, etc. For the sake of illustration, only the part above the dielectric layer 10 is drawn in the figure, and the semiconductor substrate and integrated circuit elements below the dielectric layer 10 are not related to the present invention. The main points are omitted here.

五、發明說明(4) 406i〇9 在介電層10之上具有一銅金屬層12,此銅金屬層可利 用化學氣相沈積法(CVD)、物理氣相沈積法(PVD)或電鍍法-(Electroplating)沈積後,再以化學機械研磨加以平坦化 而成。 明參照第2圖,接下來根據本發明的方法,在沈積触 刻終止層以前,先在銅導線上沈積一較薄的氮化矽襯墊層 14 °此氮化矽層可利用電漿化學氣相沈積法(pE_CVD),在 低於40(TC的操作溫度下,以siH4/NH3為反應氣體沈積而 成。為了製程上的方便,此氮化矽層的厚度以不超過1〇〇〇 =較佳。,了上述襯墊層的覆蓋後,接下來便可以放心地 2層氮氧化矽1 6作為蝕刻終止層,同樣可利用PE-CVD 、以製作,反應氣體可選擇3丨114/\〇/化或3丨114/〇3/〇2。 的製Ϊ積矽層後,若欲繼續進行多重金屬内連線 用的内金屬介化矽層上沈積另一層金屬間介電層。常 或是低介電俜备-材料如氧化矽、硼矽玻璃、硼磷矽玻璃 外,如=”料(如晴、ΡΑΕ —2、⑽、HSQ等)。另 化矽層上沈積多重内連線的製作’則此時可在氣氧 件。常用護層以保護底下剛完成的電路元 璃、氮氧=括:…璃、氮化石夕、_玻 乳乳化矽、或是氧化矽等。 後,C ;第3圖值完成内金屬介電層或護層18的製作 墊窗口 i先”的微影與姓刻程序定義出介電窗或銲 光、顯影驟Ϊ電層18上塗佈一光阻層2。,經過曝 顯〜等步驟後,露出預定形成介電窗或V. Description of the invention (4) 406i09 has a copper metal layer 12 on the dielectric layer 10, and the copper metal layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating. -(Electroplating) After deposition, it is planarized by chemical mechanical polishing. Referring to FIG. 2, according to the method of the present invention, before the deposition stop layer is deposited, a thin silicon nitride liner layer is deposited on the copper wire 14 °. This silicon nitride layer can be plasma chemistry The vapor deposition method (pE_CVD) is deposited at a temperature lower than 40 ° C using siH4 / NH3 as a reactive gas. For the convenience of the process, the thickness of the silicon nitride layer is not more than 1,000. = Better. After covering the above-mentioned liner layer, it is safe to use 2 layers of silicon oxynitride 16 as the etching stopper. PE-CVD can also be used to make the reaction gas. 3114 / \ 〇 / 化 or 3 丨 114 / 〇3 / 〇2. After the deposition of the silicon layer, if you want to continue the multi-metal interconnects, the inner metal dielectric silicon layer is deposited another layer of intermetal dielectric layer. Often or low-dielectric preparations-materials such as silicon oxide, borosilicate glass, borophosphosilicate glass, such as = "materials (such as clear, PAE-2, rhenium, HSQ, etc.). Multiple layers are deposited on the silicon layer The production of the connection can be done at this time with gas and oxygen components. Common protective layers are used to protect the newly completed circuit element glass, nitrogen and oxygen = including: glass, Fossil eve, _ glass emulsion emulsified silicon, or silicon oxide, etc. After that, C; Figure 3 shows the completion of the production of the inner metal dielectric layer or the protective layer 18. The "lithography and name" procedures define the introduction A photoresist layer 2 is coated on the electrical window or the soldering and developing layers 18, and after exposure to display, etc., the dielectric window or

第7頁 五:發明說明⑸ 406山39 ?:之後,沿著光阻層的開口21進行非等向性的蝕 精由蝕刻終止層16將蝕刻停留在銅導線12上方。 並. _ f下,,在進一步去除蝕刻終止層16與襯塾層14之 先依序以乾式去光阻(PSC)與濕式去光 介電層18上的光阻20完全去除。 程序將 有氣雷漿將# ^除乾式去先阻程序是利用含 有乳電黎將先阻㈣去&,m光阻 ^I(ACT690 ) ^ 清除。 讚)將表面上殘餘的光阻與聚合物徹底 去完光阻後,請參照第4圖,以 開口底下的㈣終止層與襯 ;刻法將 露出底下的銅導、:層銲 壁及晶圓表面的聚合物雜質,以::::刻後殘留在側 層去除乾淨’以免造成金屬腐蝕。丨曰固底部的自然氧化 由以上可知’本發明藉由 再沈積氮氧化料為银刻終止層料襯塾層’ 接沈積在銅金屬上所造成“::除氣氧化石夕直 護層或介層的蝕刻能保有良好的控:。_又能確保後序 雖然本發明已以—較佳實施 以限定本發明’任何熟習此技蓺者;如上 '然其並非用 神和範圍$ ’當可作各種之 不脫離本發明之精 護範圍當視後附之申請專利範田二巧飾’因此本發明之保Page 7 Fifth: Description of the invention406 406 Mountain 39 ?: After that, anisotropic etching is performed along the opening 21 of the photoresist layer, and the etching is stopped on the copper wire 12 by the etching stop layer 16. And under _f, the photoresist 20 on the dry photoresist (PSC) and wet photoresist dielectric layer 18 is removed completely in this order before the etch stop layer 16 and the liner layer 14 are further removed. The program will have air mines to remove # ^ dry-type first-blocking procedure is to use the milk containing electric power to remove the first block &, m photoresistance ^ I (ACT690) ^ clear. (Zambia) After the photoresist and polymer on the surface are completely removed, please refer to Figure 4 to terminate the layer and lining with the ytterbium under the opening; the engraving method will expose the copper conductor underneath, the layer welding wall and the crystal. The polymer impurities on the round surface are left with :::: left on the side layer and removed clean after engraving to avoid causing metal corrosion.丨 The natural oxidation of the solid bottom can be seen from the above. 'The present invention causes the silver etch stop layer lining layer by re-depositing a nitrogen oxide material' to be deposited on copper metal. The etching of the interlayer can keep a good control: _ and can ensure the subsequent sequence. Although the present invention has been-preferably implemented to limit the present invention 'anyone who is familiar with this technique; as above', but it is not using God and the scope $ 'when It can be used for various applications without departing from the scope of the present invention.

Claims (1)

406139 1. 一種銅金屬之隔絕保護製程,包括下列步驟: (a) 提供一半導體基底,其上具有一銅金屬層; (b) 於該銅金屬層上依序形成一襯墊層以及一蝕刻終 止層,其中該襯墊層對銅金屬的附著性比該蝕刻終止層較 佳;以及 (C )於該餘刻終止層上形成一介電層。 2. 如申請專利範圍第1項所述之製程,其中該襯墊層 為氮化妙層。 3. 如申請專利範圍第1項所述之製程,其中該襯墊層 的厚度小於1 0 0 0埃。 4. 如申請專利範圍第1項所述之製程,其中該蝕刻終 止層為氮氧化矽層。 5. 如申請專利範圍第1項所述之製程,其中該介電層 為金屬間介電層或護層。 6. 如申請專利範圍第1項所述之製程,其中步驟(c)之 後更包括: (d) 以一光阻為罩幕,蝕刻該介電層以形成一開口, 露出其下之蝕刻終止層; (e) 去除上述光阻;以及 (f )去除上述開口下之蝕刻終止層與襯墊層,以露出 該銅金屬層。 7. 如申請專利範圍第6項所述之製程,其中步驟(f )之 後更包括: 進行一乾式洗淨步驟。406139 1. A process for isolating and protecting copper metal, including the following steps: (a) providing a semiconductor substrate with a copper metal layer thereon; (b) sequentially forming a liner layer and an etching on the copper metal layer A stop layer, wherein the pad layer has better adhesion to copper metal than the etch stop layer; and (C) forming a dielectric layer on the remaining stop layer. 2. The process as described in item 1 of the patent application scope, wherein the liner layer is a nitrided layer. 3. The process as described in item 1 of the scope of patent application, wherein the thickness of the cushion layer is less than 1000 Angstroms. 4. The process as described in item 1 of the patent application scope, wherein the etching stop layer is a silicon oxynitride layer. 5. The process according to item 1 of the scope of patent application, wherein the dielectric layer is an intermetal dielectric layer or a protective layer. 6. The process as described in item 1 of the patent application scope, wherein after step (c) further includes: (d) using a photoresist as a mask, etching the dielectric layer to form an opening, exposing the etching termination below (E) removing the photoresist; and (f) removing the etch stop layer and the liner layer under the opening to expose the copper metal layer. 7. The process as described in item 6 of the scope of patent application, wherein after step (f), the method further comprises: performing a dry cleaning step. 第9頁Page 9
TW88102268A 1999-02-12 1999-02-12 Isolated protection process of the copper metal TW406139B (en)

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