TW404035B - The damascene inner-wiring process which uses the organic polymer of low-dielectrics constant as the etch stop layer - Google Patents

Abstract

The copper metal damascene inner-wiring technique is more and more important in today's multi-layer inner-wiring process; however, since the selectivity of etching is not good between the silicon nitride (SiON) layer used generally as the etch stop layer and the inter-layer dielectrics (IMD) with silicon oxide substance, it could not provide efficient protection, although it could improve this problem by increasing the thickness of the silicon nitride but it will cause the drawback of increasing the parasitic capacitor. Thus, this invention provides a betterment process which utilizes the organic polymer with low dielectrics constant such as poly(arylene ether) polymer as the etch stop layer of the defining damascene opening structure, which could not only elevate the etch selective ratio between it and the inter-layer dielectrics (IMD) but also maintain low dielectrics constant without increasing the parasite capacitance and lowering the RC performance of the devices.

Description

^ 4035 V. Description of the invention (1) [Field of invention] The invention relates to the manufacture of semiconductor integrated circuits, and is particularly relevant; species] using low-constant organic polymers (l0wk organic ^, ) S is a damascene interconnected wire with a termination layer engraved in order to improve the etching selection ratio between it and the interlayer dielectric layer (I MD) and avoid parasitic interlayer dielectric layers The capacitance increases. [Know-how] In the etching process of semiconductor integrated circuits, the use of an etch stop layer (et = h stop) is a common process technology. The obvious selectivity ratio between the etching stopper layer and the layer to be etched can not only improve the name engraving. The accuracy of the program and the effect of relaxing the operating range. "In addition to considering the etching selectivity in actual implementation of the etching stop layer, it is necessary to match the quality of the second layer of the upper and lower parts of the component, and the convenience of removal afterwards. Whether or not to make a holistic test results in side effects. The application range of the etch stop layer technology is general. Almost any process that requires an etch process has a chance. The invention is focused on the application of the interlayer dielectric layer (IMD) process of multilayer interconnect wires. In-layer ^ recording: The advantages of the damaSCene interconnected wire technology are already important. "I have made full use of this-the technology of the process of managing the dielectric layer between the contact window and the wire carefully. = 2 Layer :: Chemical :: Quality = When the engraving terminates, the nitrogen and oxygen selectivity of the layer is not good, because the layer (_ between Ran and I can increase nitrogen oxidation, the layer = fruit but; __MAUs ^ ____ V. Invention Explanation (2) < r will cause the disadvantage of increased parasitic valley. In order to discuss this issue in depth, please refer to Figures 1A to 1E below to explain the manufacturing process of the conventional technology in detail. First, as shown in Figure 1A Alternatively, a semiconductor substrate 10 ′ is provided, for example, is a silicon wafer, and a first layer of metal wires 11 ′ is formed on the surface thereof, for example, an aluminum or copper metal layer. On the surface of the semiconductor substrate 10, a first-dielectric layer is sequentially formed. Layer i 丨 and an etch stop layer i 2. For example, 'the first dielectric layer n made of silicon monoxide is formed first, which may be an undoped stone glass (USG) layer, a fluorine-doped silicon glass (FSG) layer, Or HSQ produced by Dow Corning. Then, NH3 / SiH4 / N2〇 / He raw material gas is used for deposition. Nitrogen oxide (SiO) layer 12, its operating conditions are, for example: a pressure of about 5 Torr, a temperature between 300 ° c and 400 ° C, a power of about 1 30W, a distance between the plates of about 500 mils, and The flow rate of each gas is about Sccm, n20 is about 100 seem, and He is about 2200 seem. Secondly, see FIG. IB. A photoresist layer 13 is coated on the surface of the silicon oxynitride layer 12 and imaged by lithography. The program defines a pattern to form an opening 14. Using this defined pattern of the photoresist layer 丨 3 as a mask, the silicon oxynitride layer 12 is etched to transfer the pattern, exposing the first dielectric layer u to form a contact window (via) After using a suitable organic solvent or the above-mentioned photoresist layer 13, a second dielectric layer 15 is formed to cover the gas-phase oxygen-sequenced desilting layer 12, and again, it may be undoped. Silicon glass (SG) layer, fluorine-doped silicon glass (FSG) layer, or HSQ silicon oxide dielectric layer made by Dow Corning, as shown in Figure 1C. Next, referring to FIG. 1D, another photoresist layer 16 is coated on the surface of the second dielectric layer 15 and a pattern is defined by a lithography imaging program to form an opening.

V. Description of the invention (3) 17, revealing the second use of this definition to form an inner layer 12 as a hard 19, thereby co-fragmenting the layer 12 and the first 1: 3. 7, so there is a lot of loss The silicon oxynitride layer 1 2 Next, the engraving procedure is used to remove the upper groove 18 and the connection. Firstly, the interconnection is completed by electroplating 19 and covering the surface of the chemical mechanical research layer 15 5 to complete the interconnection. The thickness during the process between the electrical layers 11 is also maintained to maintain the parasitic capacitance and increase the operating efficiency.

4040.HE The dielectric layer 15 is intended to form a portion of an interconnecting wire. After that, the photoresist layer 16 of the case is used as a mask, and the second dielectric layer 15 is etched with the grooves 18 filled by the wires, and the silicon nitride oxide mask is used to etch the first dielectric layer 11 to form a The contact window constitutes a mosaic-style opening structure. Its _, because the etching selection ratio between the oxynitride dielectric layers 11 is not large, it is only about the thickness of the silicon oxynitride layer 12 in the above etching process in order to maintain sufficient The thickness of the etching stoppage effect must be increased, for example, between 1000 Angstroms and 2000 Angstroms. Referring to FIG. 1E, after the photoresist layer 16 is etched with an appropriate organic solvent or dry type, a conductive layer 20 is formed to fill the contact window 19 'at the same time to complete a damascene-type interconnecting wire structure. A copper metal layer is formed by way of example, and is filled in the groove 18 and the surface of the second dielectric layer 15 of the contact window; and then a etch or grinding (CMP) process is performed to remove the copper metal layer on the second dielectric portion. The fabrication of the part of the lead and the contact plug structure filled in the groove 18 and the contact window 19 is left. ‘Due to the poor selectivity between the silicon oxynitride layer 12 and the first in the conventional manufacturing process’, there is a lot of loss between the etching metal layer and the electrical layer, so it is necessary to increase the silicon oxynitride layer ^ sufficient etching resistance effect. But in this way, it also makes it large, which leads to the increase of the component RC delay time and affects the product. The effective improvement method is yet to be proposed. V. Description of the invention (4) * In view of this, the copper termination of the termination layer is made with: Π &, providing an improved process using etching #etching termination layer and oxygen = opening structure, which can enhance the building Etching selection between dielectric layers of metal interlayers of the material of Faxi, / 7. The thickness required for the etch stop layer, and can effectively reduce the metal interlayers: the electrical layer ... to avoid reducing the element tilting effect: the efficiency is reduced according to the above And other purposes, the present invention proposes an improved process for mounting inlay-type interconnected wires, which uses a chill-in machine > liluren hole interconnector # IΜ H and uses a low " constant organic polymer, such as It is the extension ^ ^. I [poly (arylene ether) polymer] is taken. „The silicon layer is used to define the oblique u1 of the eroded door when inlaid opening structure is used, in addition to improving the metal layer with the oxidized sand material f. The dielectric layer 2 selects and maintains a low dielectric constant without increasing the parasitic valley and reducing the RC performance of the device. As you can tell, the present invention proposes an organic polymer with a low dielectric constant = contact termination Layer of interconnected wire, including the following steps : The conductor substrate is formed with a first-layer wire above it; formation-none = material's first-dielectric layer is covered on the semiconductor substrate and the first layer surface; the organic dielectric constant is formed by spin coating The polymer layer 'covers the surface 1 of the I dielectric layer and serves as the H-stop layer; a first photoresist layer with a defined pattern is used as a mask, and the organic polymer layer with a low dielectric constant is etched to expose the first The portion of the dielectric layer that is to form a via; after removing the first photoresist layer, a second dielectric layer made of an inorganic material is formed, covering the organic polymer layer with a low dielectric constant and the third dielectric layer. On the exposed surface of the electrical layer; a second photoresist layer with a defined pattern is used as a mask, and the second dielectric layer is etched to form a recess for the inner conductor to fill and

Page 7 --_____--- η V. Description of the invention (5) '' Continue to use the low dielectric constant organic polymer layer as a hard mask, and etch the first dielectric layer to form a contact window, exposing the part The surface of the above-mentioned first layer of wires thus forms a mosaic-type opening structure together; and after the second photoresist layer is removed, a conductive layer is formed to fill the groove and the contact window to complete the mosaic-type interconnection of the present invention. Wire process. According to a preferred embodiment of the present invention, the first dielectric layer and the second dielectric layer are both formed of silicon oxide material, such as an undoped silica glass (USG) layer and a doped fluorite glass (FSG). Layer, or HSQ made by Dow Corning. The selected organic polymer layer with a low dielectric constant may be an extension having a dielectric constant value less than 2.8 and a thickness between 500 angstroms and 1,000 angstroms: a polymer based polymer [p0ly ( arylene ether) polymer], such as FLARE 3.0 produced by A1 1 ied Signal, PAE-2 produced by Schumacher, 3. SILK produced by Dow Chemical, etc. Appropriate materials. As for the subsequent conductive layer used to form the interconnecting wire structure is a copper metal layer, the manufacturing steps include: firstly forming a copper metal layer in an electric ore method to fill the above recesses and contact windows, and cover the second dielectric On the surface of the layer; an etching or chemical mechanical polishing process is then performed to remove the portion of the copper metal layer on the surface of the second dielectric layer, leaving only the portion filled in the groove and the contact window. [Brief description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Section 1 A to 1E are a series of cross-sectional views showing a conventional use of nitrogen

_404035___. V. Description of the invention (6) '^ Copper metal embedded embedded wire routing of oxide dream (SiON) as the button stop layer; and & Figures 2A to 2C are a series of cross-sectional views' It is used to show the manufacturing process according to a preferred embodiment of the improved method of the present invention, which uses a low dielectric constant organic polymer as the etch stop layer. [Detailed description of the invention] First, as shown in FIG. 2A, a semiconductor substrate 10, such as a silicon wafer, is provided, and a first metal wire U, such as a copper or copper metal layer, is formed on the surface. Secondly, the surface of the semiconductor substrate 10 and the first layer of metal wires ^ is covered with a first dielectric layer U made of an inorganic material, such as an undoped silicon glass (USG) layer, a fluorine-doped silicon glass (FSG) layer, Or HSQ manufactured by Dowcrning. Then, a silicon nitride oxide layer 12 different from the conventional technique is used as an etch stop layer. The present invention instead performs a spin coating process to form a low dielectric constant organic polymer layer. A surface of the dielectric layer 11 serves as an etch stop layer. According to the research results of the inventor of the present case, the low-dielectric-constant organic polymer layer 120 may be a poly (arylene ether) polymer, for example, produced by Allied Signal. FLARE 3.0 'PAE-2.3 manufactured by Schumacher or SILK manufactured by Dow Chemical has a dielectric constant value of less than 2.8 and a thickness of 500 Angstroms to 1,000 Angstroms. Then, as shown in FIG. 2A, a photoresist layer 13 is coated on the surface of the organic polymer layer 120 with a low dielectric constant, and its pattern is defined by a lithography imaging program to form an opening 14. Next, a photoresist layer with this defined pattern is used

404035

V. Description of the invention (7) The organic polymer layer 120 uses the transfer dielectric layer 11 to form the contact window 13 as a cover, and the pattern of the photoresist layer 13 with a low dielectric constant is engraved to expose the first hi a) part. = FIG. 2B 'After the photoresist layer 13 is removed with an appropriate organic solvent or dry, an inorganic layer is formed—a dielectric layer covering the surface of the organic polymer layer 12 with a low dielectric constant—a first dielectric layer The electrical layer 15 may be an undoped silica glass (usg) layer, a doped glass (FSG) layer, or a Dow c—product made by the company:

Siliconized dielectric layer. I. Apply another photoresist layer 16 on the surface of the first: dielectric layer 15 and define a pattern using a lithography imaging procedure to form an opening 17 to expose the second dielectric layer Η where the interconnected wires are to be formed. Then the photoresist layer 16 with the defined pattern is used as a mask to etch the second dielectric layer 15 to form a recess 18 for the inner conductor to fill, and continue to use the silicon oxynitride layer 12 as a hard type The mask is etched to form the first dielectric layer 11 to form a contact window 19, thereby collectively forming an inlay opening structure. It should be noted that since the present embodiment uses a low dielectric constant organic polymer layer 120 instead of the silicon oxynitride 12, the etching selection ratio between the etching stop layer and the first dielectric layer 11 can be made from the conventional 1 · 3 · 7 (described in the description of Figure 丨 D) is increased to about 1: 6, so in the above-mentioned etching process, the thickness does not need to be too large to maintain sufficient money to cut off the effect. Next, please refer to FIG. 2C. After the photoresist layer 16 is removed by an appropriate organic solvent or dry etching process, a conductive layer 20 is formed and the groove 18 and the contact window 19 are filled at the same time. Inlay guide

Page 10 ^ 04035 V. Description of the invention (8) Line structure. For example, a copper metal layer is first formed by electroplating, filled in the groove 18 and the contact window 19 and covered on the surface of the second dielectric layer 15; and then a etch back or chemical mechanical polishing (CMP) process is performed. The portion of the copper metal layer located on the surface of the second dielectric layer 15 is removed, and the portion filled in the groove 18 and the contact window 19 is left to complete the fabrication of the interconnecting wires and the contact plug structure. Compared with the conventional technology, the present invention uses a low dielectric constant organic polymer layer 120 instead of silicon oxynitride 2 as an etching stopper layer, which has better resistance to etching, and can improve the interlayer between the metal layer and the metal layer. The choice ratio is' so it is only necessary to use a thickness which is smaller than that of a conventional one; = effective etching resistance. In addition, = 1, even if it is in violation of the living 120, it is also possible to use the organic polymer layer 120 with a low dielectric hanging number to avoid increasing the RC performance of the interlayer dielectric element. . Although the main power reserve 1 or the present invention has been reduced by one # # 慎 竑 办 丨 ancestors, the more conventional examples are disclosed above, the lack of willingness 4f 4 to limit the present invention, anyone who is familiar with this skill ", it is not a god Within the scope and scope of the invention, it should be regarded as attached without departing from the intensive scope of the present invention. Therefore, the scope of the patent protection scope of the present invention shall prevail.

Claims (1)

404035 6. Scope of patent application1. A process using low-dielectric polymer as the final etching process, including the following steps: providing a semiconductor substrate to form an inorganic material base and the first layer of wire table to cover the first layer by spin coating The dielectric layer uses a portion of an organic polymer window (via) that defines a pattern electrical constant. The first photoelectric layer is removed and covered on the exposed surface of the low dielectric; the pattern dielectric layer is defined to form a supply layer. An organic polymer layer with a dielectric constant to form a contact window, which together constitute a mosaic window that is opened to remove the second light. The contact window is 'completed'. 2. If the patent application machine is applied for patent application The electric layer is an organic polymer (10wk organic stop layer-less (damascene) interconnect wire bottom, which is not doped with a constant. A first layer of wire is formed above it; a first dielectric layer of high quality A low dielectric constant organic polymer layer is formed on the semiconductor substrate; on the surface, a first photoresist layer is used as a mask to etch the low dielectric layer to expose the first photoresist layer. Ichinosuke After the layer is to form a contact resistance layer, an organic polymer layer of a second dielectric constant made of an inorganic material and a second photoresist layer of the first dielectric layer are used as a mask, and the recess filled by the second connecting wire is etched. Groove, and continue to use the low layer as a hard mask to etch the surface of the first dielectric exposed portion of the first layer of wire to form a mouth structure; and a resist layer to form a conductive layer to fill the groove Harmonic interconnecting wire process. The encapsulation-type interconnecting wire process with a low dielectric constant and a stopper layer described in item 1, wherein the hetero-silicon glass (USG) layer and fluorine-doped silicon glass (FSG) Page 12 ____ 404035___ Sixth, the scope of patent application layer 'or HSQ produced by Dow Corning. 3. The process of inlaying interconnected wires using a low dielectric constant organic polymer as the termination layer as described in item 1 of the scope of the patent application, wherein the low dielectric constant organic polymer layer is a silane Polyether polymer [poly (arylene ether) polymer]. 4. As described in item 3 of the scope of the patent application, a process of inlaying interconnects using an organic polymer with a low dielectric constant as an etch stop layer, wherein the dielectric constant of the organic polymer layer with the low dielectric constant is constant. The value is less than 2.8. 5. A process of inlaying an interconnected conductor using a low dielectric constant organic polymer as a termination layer as described in item 3 of the scope of the patent application, wherein the thickness of the low dielectric constant organic polymer layer is Between 500 Angstroms and 10,000 Angstroms. 6. As described in item 3 of the scope of the patent application, a process of inlay-type interconnected wires using an organic polymer with a low dielectric constant as the #etch stop layer, wherein the organic polymer layer with a low dielectric constant is made by Miied FLARE 3.0 manufactured by Signal. 7. A process of inlaying interconnects using an organic polymer with a low dielectric constant as the termination layer as described in item 3 of the scope of the patent application, wherein the organic polymer layer with a low dielectric constant is composed of 3 PAE-2 produced by Schumacher. 8. A ballast type interconnected wire process using an organic polymer with a low dielectric constant as a stop layer for money engraving as described in item 3 of the scope of the patent application, wherein the organic polymer layer with the low dielectric constant consists of j ) 〇w chemical company produced SILK. 13 Page 13 404035 6. Scope of applying for patents' --- 9. According to the process of claiming patents, the process of inlay-type interconnected wires using organic polymers with a low dielectric constant as an etch stop layer, It enables the second dielectric layer to be an undoped silicon broken glass layer, a fluorine-doped silicon broken glass (Fsg) layer, or hsQ manufactured by Dow Corning. 10. The process of inlay-type interconnected wires using a low-dielectric constant organic polymer as a termination layer for a rice engraving as described in item 1 of the scope of the patent application, wherein the conductive layer is a copper metal layer. '11. The step of forming the copper metal conductive layer by using a damascene type interconnected wire using a low dielectric constant organic polymer as an etching stop layer as described in item 10 of the scope of the applied patent includes: Forming a copper metal layer to fill the recess and covering the surface of the second dielectric layer; and the contact " perform a one-time-out procedural mechanically abrasive metal layer located in the first-eighth increment process' Remove the copper slot and the part inside the contact window. While leaving to fill in the recess