JPH11233630A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an easy-to-oxidize metal wire of Cu, etc., from oxidizing, when a connecting hole is bored in an organic insulating film on the metal wire. SOLUTION: On a 1st layer meal wire 5, an inorganic insulating film 6 is formed thin, and then a lower-layer organic insulating film 7 and an upper-layer organic insulating film 8 are formed thereupon. Then those organic insulating films are patterned, and then the inorganic insulating film is patterned so as to complete the boring of a connection hole 9. Consequently, oxygen-based active seeds needed for patterning the organic insulating films are prevented from coming into contact with the metal wire in the final boring process of the connection hole. A semiconductor device of a high-speed logic system, etc., requiring a low-resistance wire and a low-permittivity interlayer insulating film can be manufactured with high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device using the same, and more particularly, to a method of forming a connection hole in an organic insulating film formed on an easily oxidizable metal wiring. The present invention relates to a method of manufacturing a highly integrated semiconductor device having a process and a semiconductor device using the same.

[0002]

2. Description of the Related Art ULSI (Ultra Large Scale Integrate)
As the degree of integration of semiconductor devices such as d circuits increases, it is necessary to make wiring and wiring pitch finer. At the same time, in order to meet the demands for low power consumption and high operating speed of semiconductor devices, especially high speed logic semiconductor devices, low dielectric constant interlayer insulating film materials and low resistance wiring materials are required. , And the advancement of these manufacturing process technologies are gaining importance as one of the elemental technologies.

[0003] Insulator film materials conventionally used for interlayer insulating films and the like of semiconductor devices include SiO ₂ (dielectric constant 4),
Inorganic materials such as SiON (relative permittivity 4-6) and Si ₃ N ₄ (relative permittivity 6) was mainly. As a method of reducing the capacitance between wirings of a highly integrated semiconductor device, for example, Japanese Patent Application Laid-Open
As disclosed in Japanese Patent Application Publication No. 7650, it is effective to use an interlayer insulating film made of a material having a lower dielectric constant than these general inorganic materials. Representative examples of the low dielectric constant material include an inorganic insulating film material such as a silicon oxide insulating film containing fluorine atoms (hereinafter, referred to as SiOF) and an organic insulating film material containing carbon atoms.

[0004] SiOF is Si-O constituting SiO _2.
By terminating the F atoms to -Si bonds, that the density decreases, and the Si-F bonds and that O-F bond polarizability is small or the like, a low dielectric constant can be achieved than SiO _2. Since this SiOF is similar in film formation and etching process to conventional SiO ₂ , it can be easily adopted even in a current production apparatus. Also, since it is an inorganic material, it has excellent heat resistance. However, the relative dielectric constant of SiOF is only about 3.7 to 3.2.

On the other hand, as a low dielectric constant insulating film made of an organic insulating film material containing carbon atoms, an organic SOG (Spin On
Organic polymer materials having a relative dielectric constant of about 2.5 to 3.5, such as glass, polyimide, polyparaxylylene (trade name: parylene), benzocyclobutene, and polynaphthalene, are known. The density of these materials is reduced by containing carbon atoms, and a low dielectric constant is achieved by reducing the polarizability of the molecule (monomer) itself. In addition, a certain degree of heat resistance is obtained by introducing a siloxane bond, an imide bond or a benzene ring or a naphthalene ring. By further introducing a fluorine atom into these hydrocarbon-based organic materials, the relative permittivity can be further reduced to about 1.5 to 2.5, and the heat resistance can be further reduced. As the organic material of such a fluororesin, perfluoro group-containing polyimide, fluorinated polyarylether, Teflon (trade name), Flare (trade name) and the like are known. These organic low dielectric constant materials are introduced, for example, in "Nikkei Microdevices" magazine, July 1995, pages 105 to 112.

As one wiring material, a Cu-based metal having lower resistance than an Al-based metal has attracted attention. The specific resistance of Cu is 1.72 μΩ-cm, and the specific resistance of Al is 2.7 μΩ.
The value is about ２ of Ω-cm. It is also excellent in various migration resistances such as electromigration and stress migration.

As a problem in the manufacturing process technology of the interlayer insulating film material and the wiring material, the miniaturization of the wiring width has caused
It is pointed out that not only the high aspect ratio of the cross-sectional shape of the wiring but also the high aspect ratio of the space between the wirings due to the miniaturization of the wiring intervals. As a result, a dry etching technique for patterning a difficult-to-etch and high-aspect-ratio fine-width wiring such as Cu metal, and filling a space between high-aspect-ratio wirings with an interlayer insulating film having a low dielectric constant without generating voids. A burden is imposed on the process technology, leading to complication of the process and a decrease in throughput.

As a method for solving these problems, a dual damascene process has been proposed. In this method, connection holes and wiring grooves formed in an interlayer insulating film are simultaneously buried by reflow sputtering or self-flow sputtering of Cu-based metal or Al-based metal, and unnecessary wiring material deposited on the interlayer insulating film is also removed. This is a technique to obtain a flattened surface while removing by CMP (Chemical Mechanical Polishing). This technology is described in, for example, "Nikkei Microdevice" magazine, 1997.
December 212, pp. 212-217.

An outline of the dual damascene process will be described with reference to FIG. First, as shown in FIG.
An interlayer insulating film 13 is formed on the layer metal wiring 5, and a connection hole 9 is opened here. At the same time, a wiring groove 10 for forming an upper wiring is formed in the interlayer insulating film 13. Next, as shown in FIG. 6B, a second-layer metal wiring layer 11a is formed on the entire surface. The second metal wiring layer 11a is formed to have a thickness equal to or greater than the thickness required to fill the connection holes 9 and the wiring grooves 10. Therefore, the extra second metal wiring layer 11a is also thickly deposited on the interlayer insulating film 13. After that, the unnecessary second metal wiring layer 11a on the interlayer insulating film 13 is removed by CMP and flattened. Thereby, the second-layer metal wiring 11 integrated with the contact plug is obtained.

According to the dual damascene process, an etching technique for a Cu metal which is difficult to etch is unnecessary.
In addition, since the interlayer insulating film may be formed on a flat surface, a technique for embedding in an inter-wiring space having a high aspect ratio is not required, and only the low dielectric constant characteristic may be dedicated. Therefore,
The number of steps can be significantly reduced, and the larger the wiring aspect ratio and the number of wiring layers, the more the total cost can be reduced.

[0011]

In addition to the dual damascene process, a connection hole facing the wiring is opened in an organic insulating film formed on an easily oxidizable wiring such as Cu.
Here, when a contact plug or an upper layer wiring is formed, a case where the contact resistance abnormally increases is seen.

Most of the low dielectric constant insulating films having a relative dielectric constant of less than 3.5 use an organic insulating film containing carbon atoms.
Therefore, in the step of opening the connection hole in the organic insulating film, dry etching using a gas containing oxygen is employed. This reaction mechanism is an oxidation reaction of the organic insulating film by the oxygen active species. Therefore, in the final stage of the opening of the connection hole, the surface of the lower metal wiring exposed at the bottom of the connection hole is irradiated with oxygen active species. Copper is an easily oxidizable metal, and unlike Al-based metals, the oxide film formed on the surface functions as an oxidation-resistant film, and has a weak function of preventing the progress of the subsequent oxidation reaction. Oxidation may progress to this point. That is, it is considered that even if the oxide film on the surface is removed in a later step, the high resistance layer due to the oxygen atoms penetrating inside the wiring remains, so that the contact resistance increases.

The present invention has been made in view of the above-described problems, and has been proposed in the art. When an opening is formed in an organic insulating film formed on an easily oxidizable metal wiring such as Cu, the connection hole facing the metal wiring is opened. And a method of manufacturing a highly reliable highly integrated semiconductor device capable of preventing oxidation of a lower metal wiring and forming a low-resistance contact plug or an upper wiring by a dual damascene process in a subsequent step, and this method. It is an object to provide a semiconductor device manufactured by the method described above.

[0014]

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: opening a connection hole facing a metal wiring in an organic insulating film formed on the metal wiring; A method for manufacturing a semiconductor device having a step, wherein an inorganic insulating film is formed in contact with a metal wiring,
A step of forming an organic insulating film on the inorganic insulating film, a step of patterning the organic insulating film to open a part in a depth direction of the connection hole, and a step of patterning the inorganic insulating film. And a step of opening the remaining portion of the connection hole in the depth direction. The connection hole in the present invention includes not only a mere via hole (Viahole) but also a via hole formed by a dual damascene process or the like in which groove wiring is integrated.

The semiconductor device of the present invention is characterized in that it is a semiconductor device manufactured by such a manufacturing method.

Examples of the inorganic insulating film include silicon oxide, silicon oxynitride, silicon nitride, or those containing fluorine, silicon oxide containing impurities such as PSG, BSG, and BPSG, and SOG. Silicon oxide having fine bubbles such as silica gel (Xerogel) may be used. Alternatively, silicon oxide or the like containing more Si atoms than a normal chemical equivalent composition may be used. It is also effective to use an inorganic insulating film having high thermal conductivity, such as diamond-like carbon or fluorinated diamond-like carbon. Further, these insulating films may be used in a single layer or a multilayer. The thickness of the inorganic insulating film is smaller than the thickness of the organic insulating film.

Further, the step of forming the inorganic insulating film is preferably performed by a spin coating method or a plasma CVD method in a reducing atmosphere. The reducing atmosphere is
For example, it can be obtained by plasma-exciting a mixed gas of a weakly oxidizing NO _x -based gas such as N ₂ O gas or NO gas and a highly reducing SiH ₄ gas or Si ₂ H ₆ gas. The weak oxidizing oxidizing agent, other CO, CO _x based gas such CO ₂ or N ₂ and mixed gas of O _2, is illustrated.

Preferably, the inorganic insulating film is patterned by dry etching using an etching gas containing a fluorine-based gas.

Next, the organic insulating film used in the present invention is not particularly limited as long as it has a lower dielectric constant than the above-mentioned inorganic insulating film. Organic SOG (relative permittivity 3 to 3.
5), polyimide (dielectric constant 3 to 3.5), polyparaxylylene, benzocyclobutene (dielectric constant about 2.6),
Hydrocarbon resins such as polynaphthalene, or polyimides having a perfluoro group introduced (relative permittivity of about 2.7), fluorinated polyparaxylylene (relative permittivity of about 2.4), and fluorinated polyarylether (relative permittivity of about 2.4) Permittivity 2.6), Teflon (trade name, relative permittivity 1.9 to 2.1), Cytop (trade name, relative permittivity 2.1), and organic S
Any of OG randomly copolymerized or Flare (trade name) can be used. Further, these insulating films may be used in a single layer or a multilayer. Also, the manufacturing method is not limited to CVD, PVD, a coating method, or the like.

The metal wiring of the present invention can be preferably applied to easily oxidizable metal wiring such as copper-based metal wiring. The copper-based metal wiring includes pure copper, its alloy, and a stacked wiring of these materials and other wiring materials.

Next, the operation will be described. Easily oxidizable Cu
In the case where an organic insulating film is formed in contact with a metal wiring or the like and a connection hole facing the metal wiring is opened, the surface of the metal wiring exposed at the bottom of the connection hole in the final stage of dry etching is oxygen-activated. Exposure to seeds and oxidation. The longer the over-etching time, the more oxidation of the metal wiring proceeds. Therefore, in the present invention, in the final step of the dry etching of the connection hole opening, oxygen active species were excluded. For this purpose, an inorganic insulating film such as silicon oxide, which can be dry-etched without using oxygen active species, is formed in contact with the metal wiring. If the thickness of the inorganic insulating film is smaller than that of the organic insulating film, an increase in the relative dielectric constant of the laminated interlayer insulating film as a whole can be avoided.

In the step of forming an inorganic insulating film in contact with a Cu-based metal wiring or the like, care must be taken not to oxidize the metal wiring. For example, even in plasma CVD capable of forming a film at a low temperature, generation of excessive oxygen radicals must be avoided. Therefore, in the present invention, a weakly oxidizing nitrous oxide or the like is used as an oxidizing gas when the inorganic insulating film is formed, and a plasma CVD method using a highly reducing silane gas is used. The atmosphere in plasma CVD is maintained at a weak reducing property to prevent oxidation of metal wiring. Also, a coating method such as spin coating can form a film at a low temperature of about room temperature and can prevent oxidation of the metal wiring.

As described above, by minimizing the oxidation of the easily oxidizable metal wiring, a low-resistance contact plug,
In addition, it is possible to provide a method of manufacturing a semiconductor device capable of forming a connection structure with an upper layer wiring by a dual damascene process, and a high-integration semiconductor device with high operation speed and low power consumption using the same.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. First, a semiconductor device manufactured by including the method of manufacturing a semiconductor device of the present invention will be described with reference to a schematic cross-sectional view of a main part shown in FIG.

A MOS transistor (not shown) or Bipol
A lower interlayer insulating film 2 and a lower contact plug 3 are formed on a semiconductor substrate 1 of Si or the like in which an ar transistor or the like is formed. Further, a first-layer interlayer insulating film 4 and a first-layer metal wiring 5 are formed on these surfaces.
The first layer metal wiring 5 is made of an easily oxidizable Cu-based metal.

An organic insulating film having a low dielectric constant is formed on the first-layer metal wiring 5 and the first-layer interlayer insulating film 4, but in the illustrated example, the lower organic insulating film 7 and the upper organic insulating film 7 are formed. It is composed of two layers of the system insulating film 8. Further, an inorganic insulating film 6 is formed in contact with the first-layer metal wiring 5 and the first-layer interlayer insulating film 4.

A dual damascene process is applied to the inorganic insulating film 6, the lower organic insulating film 7, and the upper organic insulating film 8 so that the connection hole 9 is opened and the wiring groove 10 is formed. Have been. In the connection holes 9 and the wiring grooves 10, a second-layer metal wiring 11 is buried, and the surfaces of the upper organic insulating film 8 and the second-layer metal wiring 11 are flattened.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention illustrated in FIG. 1 will be described in detail with reference to FIGS.

Embodiment 1 First, as shown in FIG. 2A, a lower interlayer insulating film 2 is formed on a semiconductor substrate 1 made of silicon or the like on which elements such as MOS transistors are formed.
A connection hole is opened in the lower interlayer insulating film 2 and a lower contact plug 3 is buried. Next, a first-layer interlayer insulating film 4 and a first-layer metal wiring 5 are formed on the lower-layer interlayer insulating film 2 and the lower-layer contact plug 3. The first layer metal wiring 5 is made of Cu
System metal, for example, pure Cu, sputtering method, C
It is formed by a VD method or an electrolytic plating method. The surfaces of the first-layer interlayer insulating film 4 and the first-layer metal wiring 5 are flattened. The steps so far can be formed by a conventional method.

Next, an inorganic insulating film 6 is formed on the first-layer interlayer insulating film 4 and the first-layer metal wiring 5. The thickness of the inorganic insulating film 6 may be, for example, 50 nm because the inorganic insulating film 6 may have a function of protecting the first-layer metal wiring 5 from being irradiated with oxygen active species, that is, oxygen radicals or oxygen ions in a later step.

When silicon oxide is used as the inorganic insulating film 6, a commercially available inorganic SOG containing silanol or a polymer containing silanol as a main component is spin-coated and baked at 150 to 200 ° C. for about 1 minute. Further, curing is performed at 350 to 400 ° C. for 30 to 60 minutes. Silicon oxide may be formed by a plasma CVD method using a reducing atmosphere. In this case, N ₂ O is used as an oxidizing agent, and monosilane, disilane or trisilane is used as a silicon source.
When a parallel plate type plasma CVD apparatus is used, the plasma CVD conditions may be a substrate temperature of 300 to 400 ° C., a plasma power of 350 W, and a pressure of about 1 kPa. Also in this case, the inorganic insulating film 6 is formed to have a thickness of about 50 nm.

When silicon oxynitride is used as the inorganic insulating film 6, a commercially available inorganic SO having an amino group is used.
G is spin-coated, baked again at 150-200 ° C. for about 1 minute, and then at 350-400 ° C. for 30-
It is formed by performing curing for 60 minutes. Silicon oxynitride is obtained by using a silicon source gas such as monosilane, disilane or trisilane, ammonia or hydrazine as a nitriding gas, N ₂ O as an oxidizing gas, and Ar, He or N 2 as a carrier gas.
₂ may be formed by a plasma CVD method.
Also in this case, plasma CVD conditions of a substrate temperature of 300 to 400 ° C., a plasma power of 350 W, and a pressure of about 1 kPa are used.

Similarly, when silicon nitride is used as the inorganic insulating film 6, a commercially available inorganic SOG having an amino group is used.
Is formed by spin coating. When the plasma CVD method is adopted, a silicon source gas such as monosilane, disilane or trisilane and ammonia or hydrazine are used as a nitriding gas. As a carrier gas, Ar, He or N ₂ is used. In this case, the substrate temperature is 300 to 400 ° C., the plasma power is 350 W, the pressure is 1
A plasma CVD condition of about kPa is used. The thickness of each of the inorganic insulating films 6 may be in the range of about 10 to 100 nm. If it is less than 10 nm, the oxidation resistance is not sufficient, and
If it exceeds nm, the dielectric constant of the entire interlayer insulating film cannot be reduced.

Next, a lower organic insulating film 7 is formed to a thickness of 800 nm as an example. As a material for the lower organic insulating film 7, a fluororesin (trade name: amorphous Teflon: Teflon AF) shown in Chemical Formula 1 was adopted and formed by spin coating. As the fluororesin, those having a structural formula other than that shown in Chemical Formula 1 may be used.

[0035]

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In forming the lower organic insulating film 7, first, the surface energy of the inorganic insulating film 1 is increased by irradiating the surface of the inorganic insulating film 1 with plasma. As the plasma processing apparatus, an ordinary parallel plate type plasma processing apparatus was used. Plasma processing conditions N ₂ O 50 sccm pressure 10 Pa RF power 300 W time 2 minutes

Subsequently, CF ₃ (CF ₃ ) was used as a coupling agent.
₂ ) _n CH ₂ SiCl ₃ or CF ₃ (CF ₂ ) _n
CH ₂ Si (OCH ₃ ) ₃ or CF ₃ (CF ₂ )
A solution obtained by diluting _n CH ₂ Si (OH) ₃ or the like in a solvent was spin-coated (where n is a natural number of 2 or more). The coating thickness may be about the thickness of a monomolecular layer. These plasma treatment and coupling agent treatment may be omitted if there is no problem in the adhesion of the lower organic insulating film 7.

Next, the fluororesin represented by the formula (1) is dissolved in a fluorocarbon-based solvent, applied to the inorganic insulating film 6 treated with a coupling agent by a spin coating method, dried, and cured to form a lower layer. The organic insulating film 7 was formed to a thickness of 800 nm. Spin coating condition Viscosity 30 cp Rotation speed 3000 rpm Drying condition Temperature 100 ° C. Atmosphere Nitrogen pressure Atmospheric pressure Time 2 minutes Curing condition Temperature 250 ° C. Atmosphere Nitrogen pressure Atmospheric pressure Time 5 minutes Atmosphere for drying and curing is an inert gas such as Ar. May be used.

Subsequently, the upper organic insulating film 8 is formed to a thickness of 500 nm.
Formed to a thickness of As the material of the upper organic insulating film 8, a material having a structural formula different from that of the lower organic insulating film 7 formed earlier is preferable. This is because if the material of the upper organic insulating film 8 is different from the material of the lower organic insulating film 7 when the wiring groove is patterned in a later step, the function as an etching stopper is provided to the lower organic insulating film 7. Because it can be expected. In this example, a fluorinated polyaryl ether (trade name: Flare) shown in Chemical Formula 2 was used. The method of forming the flare may be the same as that of Teflon AF. However, a resin other than the flare may be used as long as the material is an organic insulating film material having the same or similar structure as in Chemical Formula 2. FIG. 2B shows a state of the sample on which the inorganic insulating film 6, the lower organic insulating film 7, and the upper organic insulating film 8 are formed.

[0040]

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Thereafter, as shown in FIG. 3C, an inorganic mask 1 made of silicon oxide or the like having an opening pattern of a connection hole is formed.
Form 2 As the inorganic mask material, inorganic SOG, silicon oxide by plasma CVD, or the like is used, and its thickness may be about 50 nm. The inorganic mask 12 can be patterned using, for example, a magnetron RIE type plasma etching using a photoresist mask as an etching mask.

Next, using the inorganic mask 12 as an etching mask, the upper organic insulating film 8 and the lower organic insulating film 7 are used.
Is etched to open a portion 9a in the depth direction of the connection hole. In this opening step, as shown in FIG. 3D, it is desirable to stop before the lower organic insulating film 7 is completely etched off. Organic insulating film etching conditions O ₂ 50 sccm He 200 sccm pressure 1 Pa RF power 500 W substrate temperature -10 ° C.

Thereafter, as shown in FIG. 4E, the portion of the inorganic mask 12 corresponding to the wiring groove formed in a later step is further patterned. In this step, the inorganic mask 12 having the opening pattern of the connection hole may be once peeled off, a new inorganic mask layer may be formed, and the opening pattern of the wiring groove and the connection hole may be etched.

Using the newly patterned inorganic mask 12 as an etching mask, the upper organic insulating film 8 is etched to form the wiring groove 10 as shown in FIG. The etching conditions may be in accordance with the above-described etching conditions for the organic insulating film. By this etching process,
The thin lower organic insulating film 7 remaining at the bottom of the portion 9a in the depth direction of the connection hole is also etched away, and the surface of the inorganic insulating film 6 is exposed at the bottom of the portion 9a of the connection hole in the depth direction. .

Subsequently, the etching conditions are switched, and the inorganic insulating film 6 exposed at the bottom of the portion 9a in the depth direction of the connection hole is etched. When the inorganic insulating film 6 is made of silicon oxide, the following etching conditions can be adopted by a parallel plate type plasma etching apparatus. Etching conditions for inorganic insulating film C ₂ F ₆ 14 sccm CO 180 sccm Ar 240 sccm Pressure 1 Pa RF power 1500 W By this etching process, the remaining portion in the depth direction of the connection hole is opened as shown in FIG. Thus, the connection holes 9 are completed, and the inorganic mask 12 is also removed.

Thereafter, as shown in FIG. 5H, a second metal wiring layer 11a is formed, and the connection holes 9 and the wiring grooves 10 are buried. The material of the second metal wiring layer 11a was a Cu-based metal, pure Cu in this embodiment, and was formed to a thickness of 1500 nm by a long-distance sputtering method having excellent step coverage. The second metal wiring layer 11a can also be formed by a CVD method, an electrolytic plating method, or the like. When employing the electrolytic plating method, a thin conductive film of Cu or the like is formed in advance, and this is used as an electrode for electrolytic plating. Also C
When the VD method is used, a plasma CVD method using, for example, an organometallic compound of copper, for example, Cu (hfac) (tmvs) as a source gas is preferable. Cu (hfac) (tmvs) has hfac (Hexafluoroacetylacetate)
tonate) and tmvs (Trimetylvinylsilane).

[0047]

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Subsequently, the unnecessary second metal wiring layer 11a formed on the upper organic insulating film 8 is removed by a known CMP method, and the second metal wiring layer 11a is formed in the connection hole 9 and the wiring groove 10. 11 is buried flat. The unnecessary second metal wiring layer 11a on the upper organic insulating film 8 may be removed by a known etch-back method or the like. The state after the completion of the CMP is shown in the schematic sectional view shown in FIG. 1 described above.

In this embodiment, an inorganic insulating film is formed in contact with a metal wiring such as Cu metal which is easily oxidized, and then an organic insulating film containing fluorine as an organic insulating film, for example, amorphous Teflon and fluoride It was formed by laminating polyaryl ethers. This can prevent oxidation of the metal wiring when opening the connection hole facing the metal wiring, and can expect an etching stopper effect at the time of patterning the wiring groove. Therefore, a dual damascene process having a very low dielectric constant effect and having a low-resistance contact plug can be realized.

[Embodiment 2] In this embodiment, the material of the lower organic insulating film 7 and the upper organic insulating film 8 shown in FIG. Example 1 above except that the top (product name) was adopted
It is based on. The CYTOP film was formed by a spin coating method, for example, once at a thickness of 1.3 μm.

[0051]

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As the cyclic fluororesin, a fluorine-containing resin having a similar repeating structure may be employed in addition to the structural formula shown in [Formula 4]. Further, a copolymer resin of a cyclic fluororesin and a siloxane resin represented by Chemical Formula 5 may be used.

[0053]

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The etching conditions for forming the connection holes 9 and the wiring grooves 10 in the organic insulating film with the cyclic fluororesin may be the same as in the first embodiment. However, since the etching stopper effect cannot be expected when patterning the wiring groove, the etching end point of the wiring groove is determined by controlling the etching time based on the etching rate of the organic insulating film.

According to the present embodiment, a thin inorganic insulating film is formed in contact with a metal wiring which is easily oxidized such as Cu metal, and then, as an example of an organic insulating film containing fluorine, an organic insulating film containing fluorine is used as an organic insulating film. The resin was formed thick. This allows
Oxidation of the metal wiring when opening the connection hole facing the metal wiring can be prevented. Therefore, a dual damascene process having a very low dielectric constant effect and having a low-resistance contact plug can be realized.

[Embodiment 3] In this embodiment, a polyaryl ether represented by Chemical Formula 6 is formed to a thickness of 800 nm as a material of the lower organic insulating film 7 shown in FIG. The film 8 is the same as that of the first embodiment except that the fluorinated polyaryl ether shown in [Formula 2] is formed to a thickness of 500 nm. The film formation method of polyarylether and fluorinated polyarylether was also based on spin coating.

[0057]

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The etching conditions for opening the connection holes 9 and forming the wiring grooves 10 in the lower organic insulating film 7 and the upper organic insulating film 8 may be the same as in the first embodiment. However, at the time of patterning of the wiring groove, by using the difference in the etching rate between the organic insulating film having fluorine atoms and the organic insulating film having no fluorine atoms, while having the same basic skeleton, A more reliable etching stopper effect can be obtained.

In this embodiment, a thin inorganic insulating film is formed in contact with a metal wiring that is easily oxidized such as Cu metal, and then an organic insulating film containing no fluorine and an organic insulating film containing fluorine are formed as the organic insulating film. It was formed by stacking insulating films. This can prevent the metal wiring from being oxidized when the connection hole facing the metal wiring is opened, and can provide a more reliable etching stopper effect in the wiring groove forming step. Accordingly, a dual damascene process having a high effect of lowering the dielectric constant and having a low-resistance contact plug can be realized with high reliability.

Although the present invention has been described in detail with reference to three examples, the present invention is not limited to these examples.

For example, silicon oxide is exemplified as the material of the inorganic insulating film, but silicon oxide containing impurities, silicon oxide containing fluorine, silicon oxide other than chemical equivalents, silicon oxynitride, silicon nitride, diamond-like carbon, etc. Can be used.

Further, in addition to the amorphous Teflon, polyparaxylylene fluoride and Cytop described in the examples as the organic insulating film, fluorinated polyimide represented by Chemical Formula 7, various fluorine-containing resins, or fluorine may be used. Resins that do not contain can be used.

[0063]

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As metal wiring materials, in addition to pure copper, copper-based alloys, silver, and other easily oxidizable metals and their laminated materials, A
Conventionally used wiring materials such as l-based metal and refractory metal silicide can be used.

In addition to the application to the dual damascene process, it goes without saying that the present invention may be used in the step of opening only the connection hole facing the metal wiring.

[0066]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention and the semiconductor device using the same, the step of opening the connection hole facing the easily oxidizable metal wiring is performed by this metal. This can be achieved without oxidizing the wiring. Therefore, by employing the method for manufacturing a semiconductor device of the present invention, a highly integrated semiconductor device having both a low-resistance metal wiring and a low-dielectric-constant interlayer insulating film can be manufactured with high reliability.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a main part of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device of the present invention, showing a step following FIG. 2;

FIG. 4 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the present invention, and shows a step following FIG. 3;

FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the present invention, and shows a step following FIG. 4;

FIG. 6 is a schematic sectional view showing an outline of a dual damascene process.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 lower interlayer insulating film 3 lower contact plug 4 first interlayer insulating film 5 first metal wiring 6 inorganic insulating film 7 lower organic insulating film 8 upper organic insulating film, 9 connection hole, 9a part of the connection hole in the depth direction, 10 wiring groove, 11 second metal wiring, 11a
... second metal wiring layer, 12 ... inorganic mask, 13 ... interlayer insulating film

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a step of opening a connection hole facing a metal wiring in an organic insulating film formed on a metal wiring, wherein the inorganic insulating film is in contact with the metal wiring. Forming a film, forming the organic insulating film on the inorganic insulating film, patterning the organic insulating film, and opening a part of the connection hole in a depth direction, A method of patterning a system insulating film to open a remaining portion of the connection hole in a depth direction, a method of manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the thickness of the inorganic insulating film is smaller than the thickness of the organic insulating film. 3. The method according to claim 1, wherein a relative dielectric constant of the organic insulating film is smaller than a relative dielectric constant of the inorganic insulating film. 4. The method according to claim 1, wherein the step of forming the inorganic insulating film is performed by a spin coating method. 5. The method according to claim 1, wherein the step of forming the inorganic insulating film is performed by a plasma CVD method in a reducing atmosphere. 6. The method according to claim 1, wherein the patterning of the inorganic insulating film is performed by dry etching using an etching gas containing a fluorine-based gas. 7. The method according to claim 1, wherein the metal wiring is a copper-based metal wiring. 8. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.