五、發明說明（ 發明領域 A7 B7 402782 本發明與一種半導體製程有關，特別是一種除去原始 氧化層的方法。 發明背景： 為了符合極大型積體電路（Ultra Large Scale Integrated ; ULSI )的需求，半導體技術已有重大的進步， 新的應用驅使半導體元件的不斷進步，例如用聲音處理、 影像處理或其他通訊介面來操作電腦介面，上述應用都需 要大量的記憶體’近幾年來由於元件縮小導致健存密度進 步’例如當動態隨機存取記憶體（DRAMs )尺寸縮小時， 維持每個電容_夠高的儲存電荷便是一大挑戰，而且此過 程較之以往變得更為關鍵，一些細微的不準 (misalignment )或差錯便會造成整個電路失效。 <請先閱讀背面之注意Ϋ項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 積體電路製造時，各層或各元件間是經由接觸窗 (contact hole )或介層窗（Via hole)來形成電性上的連結，. 對於極大型積體電路來說，在次微米技術上建立有效的電 性連結路徑是重要的任務，目前接觸窗或介層窗結構的形 成都面臨縮減空間的要求，這是一項重要且具挑戰性的任 務’因為個別元件不當隔離時所產生的微量漏電流，對整 個電路來說將會導致相當大的功率消耗》 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消费合作社印製 A7 -^------------- 五、發明說明（） 402782 办 般都是用蝕刻和微影製程技術在絕緣層中形成接觸 =或介層窗，例如在矽基板或矽層上蝕刻一氧化矽層的開 口，就熟知的技術來說，蝕刻劑是氬氣、cHf3與氧氣在電 漿中的混合物’以得到一適當形狀的接觸窗或介層窗，當 2刻進行到矽層或矽基板曝露出來時蝕刻反應方會停止， ’、;'而矽材料在含氧的環境中易被氧化，所以蝕刻後接觸窗 曝露出來的矽材料在含氧的空氣中會被氧化，此氧化層並 非7意形成的所以稱之為原始氧化層（native 〇xide )。原 始孔化層會增加接觸點的電阻而降低電性連結的表現，傳 統上是使用濕浸法（wet dip )來解決此問題，然而效果並 不顯著，而且當元件尺寸降至深次微米範圍時，更應重新 •平估製造連結結構的技術。因此需要一能提供改善連結性 的新穎技術。 ligL目的及概诚： 本發明包含在絕緣層中形成一接觸窗以便將基板或底 層的一部份曝露出來’沿著接觸窗的表面和絕緣層之上形 成一多晶*夕層’然後以離子植入法將摻質離子植入至接觸 窗底下的原始氧化層，以便將原始氧化層轉變為非晶矽 層’換質的種類可為n或p導電性，其中η導電性例如；6^、 或碟等；ρ導電性例如硼等’接著第一導電層形成於該多 晶矽層之上且回填至接觸窗，一般該第一導電層的材質是 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公楚） 、裝--------訂-----------線 (請先聞讀背面之注意事項再填寫本頁) A7 402782 B7V. Description of the invention (Field of invention A7 B7 402782) The present invention relates to a semiconductor process, especially a method for removing the original oxide layer. Background of the Invention: In order to meet the needs of Ultra Large Scale Integrated Circuits (ULSI), semiconductors There have been significant advances in technology. New applications have driven the continuous advancement of semiconductor components, such as operating computer interfaces with sound processing, image processing, or other communication interfaces. All of these applications require a large amount of memory. Storage density improvement 'For example, when the size of dynamic random access memories (DRAMs) is shrinking, maintaining a high enough storage charge for each capacitor is a challenge, and this process becomes more critical than before. Some subtle Misalignment or errors will cause the entire circuit to fail. ≪ Please read the note on the back before filling out this page.) When the printed circuit is manufactured by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the printed circuit is manufactured in various layers or between components. Electrically formed through contact holes or via holes For very large integrated circuits, it is an important task to establish an effective electrical connection path in sub-micron technology. At present, the formation of contact windows or interlayer window structures is facing space reduction requirements. Important and challenging task 'Because the small leakage current generated when individual components are improperly isolated, it will cause considerable power consumption for the entire circuit.' This paper standard applies to China National Standard (CNS) A4 specification (210 X 297 mm) A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-^ ------------- V. Description of Invention () 402782 Insulation is generally performed by etching and lithography process technology. Contact or interlayer window is formed in the layer, for example, the opening of a silicon oxide layer is etched on a silicon substrate or a silicon layer. As is well known, the etchant is a mixture of argon, cHf3 and oxygen in a plasma. A contact window or interlayer window of an appropriate shape is obtained. When the silicon layer or the silicon substrate is exposed in 2 minutes, the etching reaction will stop, and the silicon material is easily oxidized in an oxygen-containing environment, so the etching is performed. Rear contact window Silicon material is exposed is oxidized in an oxygen containing atmosphere, the oxide layer and the non-oxide layer so called original (native 〇xide) 7 is intended to form. The original pore layer will increase the resistance of the contact point and reduce the performance of electrical connection. Traditionally, wet dip is used to solve this problem, but the effect is not significant, and when the component size is reduced to the deep sub-micron range At the same time, the technology of manufacturing connected structures should be re-evaluated. Therefore, there is a need for a novel technology that can provide improved connectivity. Purpose and sincerity of ligL: The present invention includes forming a contact window in an insulating layer so as to expose a part of a substrate or a bottom layer to 'form a polycrystalline layer along the surface of the contact window and the insulating layer', and then Ion implantation implants dopant ions into the original oxide layer under the contact window in order to transform the original oxide layer into an amorphous silicon layer. The type of the metamorphism can be n or p conductivity, where n conductivity is, for example; 6 ^, Or plate; ρ conductivity such as boron, etc. 'Then the first conductive layer is formed on the polycrystalline silicon layer and backfilled to the contact window. Generally, the material of the first conductive layer is the paper standard applicable to the Chinese National Standard (CNS) A4 specifications (21〇X 297), installation -------- order ----------- line (please read the precautions on the back before filling this page) A7 402782 B7
五、發明說明（） 由摻雜的多晶矽與同步摻雜的多晶矽所組成之族群中所選 出的。一光阻圖案形成於該第一導電層之上以定義第一儲 存電極，以該光阻為罩幕進行蝕刻將第一導電層的部份去 除，接著將光阻剝除。沿著第一導電層的表面形成一介電 層，再用傳統的低壓化學氣相沈積法（LPCVD )形成第二 導電層於該介電層之上。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 第一圖為本發明中半導體晶圓之截面圖和形成多晶矽 層於一接觸窗中的步驟。 第二圖為本發明中半導體晶圓之截面圖和進行離子植 入法的步驟。 第三圖為本發明中半導體晶圓之截面圖和形成第一導 電層於該接觸窗中的步驟。 第四圖為本發明中半導體晶圆之截面圖和形成一儲存 電極的步驟。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----------轉 經濟部智慧財產局員工消費合作社印製 A7 402782 五、發明說明（ 發明詳細說明： 本發明提供一種消降历仏s β “原。氧化層的方法，特別是本智 明將形成於矽層之上的®私签a 町原始軋化層轉變為低電阻層，此屬 個別描述的方法包含許客3JJJ A 4 、 吁夕白知技術，但目前為土並沒有朝 組成為具新顆性與進步性 /江之發明。一原始氧化層形成於石j 層或矽基板上，然後以離子楠法 雕卞植入法將離子植入至原始氧U 層，以便將原始氧化層轉變為北曰坊a , 刊·雙马非晶ί夕層，接著，進行加旁 製程將此非晶石夕層轉變為攸雷阳思 ^ , 柯《两低電阻層，一較佳實施例描述女 下，以DRAMs元件上接觸宙沾於# Α 按咽1的形成為例，本發明並不限哀 於此實施例，但卻涵蓋不同的改良。 請參閱第一圖，提供—晶向為<1〇〇>之單晶矽基板2 形成例如厚場氧化層（F0X)或溝渠（trench)的隔離區 (未圊不）’以提供基板2上元件間的隔離例如可用 影製程或乾蝕刻氮化矽與二氧化矽之化合物來形成場氧 層區域，當剝除光阻和濕式清洗之後，在含氧環境中進 熱氧化法使場氧化層成長至厚度約為4〇〇〇至6〇〇〇埃， 後將該化合物層剝除。 (請先閲讀背面之注意事項再填寫本頁) '裝 — I — —^SJ· I —1 — — ——— 經濟部智慧財產局員工消費合作社印製 形成場氧化層之前，先製作二氧化矽（siHcon di〇xide) 層6於基板2之上表面’以作為後續形成之金氧半場效電 晶體（Μ 0 S F E T s )的閘氧化層，在—實施例中，該二氧化 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Α7 402782 ----------Β7___ 五、發明說明（） ""~ [ 碎層6形成於溫度850 ϋοο◦度的含氧環境中，或者是該 -氧化矽層6也可用其他任何的適合方法來形成，例如化 學氣相沈積法。本實施例中，該二氧化石夕層6的厚度約為 20至2。〇埃，再以低壓化學氣相沈積法形成—摻雜的多晶 矽層8於場氧化層區域和二氧化矽層6之上，接著進行標 準的微影和蝕刻製程以形成閘極結構或字元線。通常間隙 壁1 〇形成於閘極結構或字元線的側壁上。然後主動區域工2 (源極和汲極）以習知製程植入適當離子至這些區域來形 成0 一絕緣層14接著形成於上述元件之上，在該絕緣層14 中製作接觸窗16使主動層的一部分曝露出來，在某種狀況 下’該絕緣層1 4可為氧化物，如此被蝕刻物的蝕刻劑可為 氮氣、CHF:、和氧氣在電漿中的混合物，以得到較適當的接 觸窗形狀。一般在進行下一製程而將基板2移出反應室 時，原始氧化層18會在接觸窗所曝露的矽表面上形成•接 著沿接觸窗1 6的表面和絕緣層14之上形成一多晶矽層 20 ’該多晶矽層20最好使用傳統的低壓化學氣相沈積法來 形成’該多晶矽層20最好選自摻雜的多晶矽或同步摻雜的 多晶碎。 經濟部智慧財產局貝工消費合作社印製 > /L·^-----_--------------^ I (請先閱讀背面之注意事項再填寫本頁) 該絕緣層1 4之上的多晶矽層20作為電容第一儲存電 極的一部份’然後以離子植入法經由接觸窗1 6將適當的離 子植入至原始氧化層18，以便將原始氧化層18轉變為一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7V. Description of the invention () It is selected from the group consisting of doped polycrystalline silicon and synchronously doped polycrystalline silicon. A photoresist pattern is formed on the first conductive layer to define a first storage electrode. The photoresist is used as a mask to etch to remove a portion of the first conductive layer, and then the photoresist is stripped. A dielectric layer is formed along the surface of the first conductive layer, and then a second conductive layer is formed on the dielectric layer by a conventional low pressure chemical vapor deposition (LPCVD) method. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: The first figure is a cross-sectional view of a semiconductor wafer in the present invention and a polycrystalline silicon layer is formed in a contact In the window. The second figure is a cross-sectional view of a semiconductor wafer and steps for performing an ion implantation method in the present invention. The third figure is a cross-sectional view of a semiconductor wafer and a step of forming a first conductive layer in the contact window in the present invention. The fourth figure is a cross-sectional view of a semiconductor wafer and a step of forming a storage electrode in the present invention. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page) Loading -------- Order -------- -Printed by A7 402782 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (Detailed description of the invention: The present invention provides a method for reducing calendar 仏 s β “Original. The method of oxide layer, especially Ben Zhiming will be formed on silicon Above the layer, the original rolled layer of the private label a-machi is transformed into a low-resistance layer. This method is described separately. It includes Xu Ke 3JJJ A 4 and Yu Xi Baizhi technology, but the current soil is not composed of new particles. Performance and advancement / Jiang's invention. An original oxide layer is formed on the stone layer or silicon substrate, and then the ions are implanted into the original oxygen U layer by ion implantation method, so as to transform the original oxide layer into Bei Yuefang a, Shuangma Amorphous Twisted Layer, and then performed a side-by-side process to transform this amorphous crystalline layer into a Lei Yangyang ^, Ke "Two low-resistance layers, a preferred embodiment describes female In the following, taking the contact formation of DRAMs on the DRAMs as # Α Pressing the throat 1 as an example, the present invention is not limited to Examples, but covering different improvements. Please refer to the first figure, providing-a single crystal silicon substrate 2 with a crystal orientation of <100; > forming an isolation such as a thick field oxide layer (FOX) or trench Area (not incomplete) to provide isolation between components on the substrate 2. For example, a field process or dry etching of a compound of silicon nitride and silicon dioxide can be used to form a field oxygen layer region. After stripping the photoresist and wet cleaning, The field oxide layer is grown to a thickness of about 4,000 to 6,000 angstroms by thermal oxidation in an oxygen-containing environment, and then the compound layer is peeled off. (Please read the precautions on the back before filling this page) '装 — I — — ^ SJ · I —1 — — — — Before the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy prints and forms a field oxide layer, a silicon dioxide (siHcon di〇xide) layer 6 is formed on the substrate 2 The upper surface is used as a gate oxide layer of the subsequently formed metal-oxide half-field-effect transistor (M 0 SFET s). In the embodiment, the paper size of this dioxide is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) Α7 402782 ---------- Β7 ___ 5. Description of the invention ( ） &Quot; " ~ [Fragmentation layer 6 is formed in an oxygen-containing environment at a temperature of 850 ϋοο◦◦, or the silicon oxide layer 6 may be formed by any other suitable method, such as chemical vapor deposition. This implementation In the example, the thickness of the stone dioxide layer 6 is about 20 to 2.0 angstroms, and then formed by a low-pressure chemical vapor deposition method-a doped polycrystalline silicon layer 8 is on the field oxide layer region and the silicon dioxide layer 6 Then, a standard lithography and etching process is performed to form a gate structure or a word line. Usually, a spacer 10 is formed on a sidewall of the gate structure or a word line. Then the active area 2 (source and drain) implants appropriate ions into these areas in a conventional process to form 0. An insulating layer 14 is then formed on the above elements. A contact window 16 is formed in the insulating layer 14 to make the active A part of the layer is exposed. Under certain conditions, the insulating layer 14 may be an oxide, and the etchant of the etched material may be a mixture of nitrogen, CHF :, and oxygen in a plasma to obtain a more appropriate Contact window shape. Generally, when the next process is performed and the substrate 2 is removed from the reaction chamber, the original oxide layer 18 is formed on the silicon surface exposed by the contact window. Then, a polycrystalline silicon layer 20 is formed along the surface of the contact window 16 and the insulation layer 14 'The polycrystalline silicon layer 20 is preferably formed using a conventional low-pressure chemical vapor deposition method.' The polycrystalline silicon layer 20 is preferably selected from doped polycrystalline silicon or synchronously doped polycrystalline silicon chips. Printed by Shelley Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs > / L · ^ -----_---------------- ^ I (Please read the precautions on the back before filling in this Page) The polycrystalline silicon layer 20 on the insulating layer 14 is used as a part of the capacitor's first storage electrode, and then appropriate ions are implanted into the original oxide layer 18 through the contact window 16 by the ion implantation method, so that the original Oxidation layer 18 is converted into a paper size applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) A7
五、發明說明（ 402782 夕層22,摻質的種類可為 性例如岬、或磷等# '、Τ η等電 換質，Μ ^ 料，最好利珅作為 摻質離子植入時的劑量約在iEl5^1F1Rt , 2 圍，能量約為5。至n〇KeV。 1E16at〇nS/Cm的範 矽層接20著’如第三圖所示，一第—導電層24形成於該多晶 夕層20之上且回填至接觸f 16，典型地，該第一 的材質是選自摻雜的多晶_、 J夕a日y H步摻雜的多晶矽、金屬戋 合金。-光阻圖案26形成於該第—導電層24之上以定義 第儲存電極。如第四圖所π，以言亥光阻Μ為罩幕進行敍 刻：第導電層24的部份去除’接著再將光阻“剝除。 沿著第—導電層24的表面形成—介電層28，該介電層Μ 最好選自t化物/氧化物的雙層薄冑、氧化物/氣化物/氧化 物的三層薄膜或任何其他介電薄膜如五氧化二钽（Ta205 ) 作為材質。再用傳統的低壓化學氣相沈積法（LPC VD )形 成第二導電層30於該介電層28之上。第二導電層3〇提供 另一儲存電極且材質為摻雜的多晶矽、同步摻雜的多晶 石夕、紹、銅、鎢、鈦或合金。最後在充滿N 2的環境中進行 一加熱製程以便將非晶矽22轉變為低電阻層3 2，該加熱 製程溫度約為攝氏7〇〇度至1〇〇〇度。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) '裝-------|甘----%--- ·線 經濟部智慧財產局員工消費合作社印製 A7 B7 402782 五、發明說明（）專利範圍内。 t------------VI裝-----.---訂----------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (402782 XI layer 22, the type of dopant may be, for example, cape, or phosphorus, etc., such as electrical replacement, M ^ material, it is best to use 珅 珅 as the dose for dopant ion implantation Around iEl5 ^ 1F1Rt, 2 and the energy is about 5. To noKeV. 1E16at0nS / Cm Fan silicon layer is connected to 20 'As shown in the third figure, a first-conductive layer 24 is formed on the polycrystalline Above the layer 20 and backfilled to the contact f 16, typically, the first material is selected from the group consisting of doped polycrystalline silicon, polycrystalline silicon doped at step H and step H, and metal hafnium alloy. -Photoresist pattern 26 is formed on the first conductive layer 24 to define the first storage electrode. As shown in the fourth figure, the photoresist M is used as a mask to describe: a part of the second conductive layer 24 is removed, and then the light is removed. Resistive stripping. A dielectric layer 28 is formed along the surface of the first conductive layer 24. The dielectric layer M is preferably selected from the bilayer thin film of tide / oxide, oxide / gaseous / oxide Three layers of thin film or any other dielectric film such as tantalum pentoxide (Ta205) is used as the material. Then a second low-pressure chemical vapor deposition (LPC VD) method is used to form a second conductive layer 30 on the substrate. Electrical layer 28. The second conductive layer 30 provides another storage electrode and is made of doped polycrystalline silicon, synchronously doped polycrystalline silicon, Shao, copper, tungsten, titanium, or an alloy. A heating process is performed in the environment to transform the amorphous silicon 22 into the low-resistance layer 32, and the heating process is performed at a temperature of about 700 ° C to 1000 ° C. The above description is only a preferred embodiment of the present invention. It is not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following application. The paper standards are applicable to Chinese National Standards (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) 'Packing ------- | Gan ----% --- · Consumer Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative A7 B7 402782 V. Description of the invention () Within the scope of patents t ------------ VI equipment ------------- Order --------- -Line (Please read the precautions on the back before filling out this page) The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CN S) A4 size (210 X 297 mm)