4〇a54b 5 0 I 91 w t', d o c 0 0 : A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（ί ) 本發明是有關於一種積體電路的半導體製程，且特別 是有關於一種的半導體製程，用以改善化學機械硏磨法 (chemical mechanical polishing, CMP)的凹陷（dishing)與刮 傷（chatter mark)等問題。 化學機械硏磨法是現在唯一能提供半導體製程全面性 平坦化（global planarization)的一種技術’其係利用機械式 硏磨的原理，配合適當的化學助劑(reagent)，將晶片表面高 低起伏不一的輪廓’一倂加以磨平的平坦化技術。 在化學機械硏磨法製程中所使用的硏漿（slurry)，亦即 所謂的化學助劑中，含有硬度極高的硏磨顆粒，而化學機 械硏磨法即是利用硏磨性(abrasive)極高的微粒，來進行晶 片表面的硏磨。然而，由於上述的硏磨顆粒硬度極高，造 成以化學機械硏磨法在硏磨一些材料的表面時，極容易造 成表面刮傷的現象，使得在後續製程中發生橋接(bridge)， 影響元件的操作，造成可靠度降低。 此外’化學機械硏磨法通常需要依賴一層硬材料層作爲 一終止層(stop丨ayer)以控制製程進行的終點。然而，當化學 機械硏磨同時硏磨軟材料層與硬材料層時，則由於其對於 軟材料層的硏磨速率較硬材料層爲快，使得在以硬材料層 作爲一終止層時，會過度硏磨軟材料層，而造成凹陷的現 象，使得硬材料層與軟材料層的高度差可相差至5〇〇埃。 而凹陷，將使得後續製程在形成金屬層時，造成金屬層塡 入凹陷處無法去除而導致短路等電性上的問題。 有鑑於此，本發明就是在提供一種半導體製程，用以改 (請先閲讀背面之注意事項再填寫本頁) 裝 i----i--Γ 訂---------_ 191'' 1' d 。〇 5 A7 B7 i、發明說明（> ) 善化學機械硏磨法材料層的凹陷，以及避免化學機械硏磨 法硏磨顆粒對材料層表面的刮傷，藉以增進元件可靠度。 (請先閲婧背面之注意事項再填寫本頁) 本發明提供一種半導體製程，在一基底上形成有元件結 構，而;t件結構上更形成有蓋層，之後在基底上形成一介 電材料，覆蓋元件結構。續以蓋層爲終止層，以化學機械 硏磨法硏磨介電材料，而使硬材料層暴露出。接著，在介 電材料與元件結構上形成一具有熱流性質的絕緣材料，藉 以提供一平坦化的表面。 本發明係利用在高溫時具有流動性質的絕緣材料，塡補 因化學機械硏磨法硏磨時在介電材料產生的刮痕以及凹陷 等，故可避免後續電性上的問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A-1D圖係顯示根據本發明較佳實施例之半導體製 程之製造流程剖面圖。。 其中，各圖標號之簡單說明如下： 經濟部智慧財產局貝工消費合作社印製 100 :基底 102 :閘極 104 :間隙 106 :蓋層 108 :緊密區 1 ] 0 :寬鬆區 4 本紙張尺度適用尹國國家標準（CNS)A4規格（210 X 297公爱） A7 B7 402¾48 5 Ο l 9 t w !'. do . 00 5 五、發明說明（）） 112 :介電材料 114 :刮傷 116 :凹陷 118 :具熱流性質之絕緣材料 120 :介電層 122 :導線 實施例 本發明之較佳實施例係利用具有熱流性質之絕緣材料 塡補因化學機械硏磨產生的刮傷，而利用絕緣材料具有流 動性之特性，使凹陷現象亦獲得改善’因此可降低刮傷或 凹陷在後續製程中致使導電材料殘留的可能性’進而改善 元件的可靠度。 第1A-1D圖所示，爲根據本發明一較佳實施例之半導 體製程之製造流程剖面圖。請參照第1A圖，在-基底100 上具有-些元件結構102，元件結構102係以間隙104隔 開。元件結構102例如爲閘極，閘極可以熟此技藝者已知 之技術形成，例如在形成複晶矽層後，進行光阻微影蝕刻 製程而完成。其中元件結構1〇2側邊與頂部覆蓋蓋層（cap layer)】()6，用以徹底保護元件結構102與其他導電材質不 必要的接觸，以防止漏電等情形，蓋層〗〇6 —般以較硬的 材料構成，例如氮化矽層。而由於電路設計（lay〇llt)的緣故’ 在同一晶片上元件結構的排列通常會同時具有較緊密 108與較寬鬆110的排列，如第1A圖所示，而較爲緊密排 列108的元件結構102間之間隙104寬度較小，而較爲寬 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 x297公釐） (請先閱讀背面之注意事項再填寫本頁) * 裝·"T---,---訂---------^· 經濟部智慧財產局員工消费合作社印製 402548 ϊ 9tu | c}< A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（·/) 鬆排列110的元件結構106間則具有較大寬度的間隙丨04。 接著，請參照第1B圖，在元件結構102上形成一介電 材料112，塡入間隙104中，並延伸至元件結構102上，其 中介電材料112例如爲硼磷矽玻璃(BPSG)，以化學氣相沉 積法沉積厚度約爲4500-6000埃左右，其中硼磷矽玻璃中 硼含量約爲3-5%(Wv)，磷含量約爲4-5%(v/v)左右，而硼磷 矽玻璃經由一熱流製程（reflow)後可使其提供較爲平坦的 表面，其中熱流溫度約爲800-950°C，操作時間約爲15-60 分鐘。 仍請參照第1B圖，接著進行化學機械硏磨法，以蓋層 106爲終止層，平坦化介電材料112，使蓋層106暴露出， 而介電材料Π2塡入第1A圖之間隙104中。由於化學機械 硏磨法中的硏磨顆粒較硬，且加上硏磨蓋層106的殘餘顆 粒，使得較軟的介電材料112上會出現刮傷114。此外，由 於寬鬆排列的元件結構102相隔的距離較大，且介電材料 112較軟’因此當進行化學機械硏磨時，寬鬆排列的元件結 構102間隙112就容易產生凹陷116的現象。而上述之刮 傷114與凹陷116將使後續的導電材料沉積時，殘留在刮 傷114與凹陷116中’造成不必要的電性連接而引起橋接 等現象。 爲了預防刮傷與凹陷的產生，則在介電材料與蓋層 106上形成-·具有熱流性質的絕緣材料丨μ，如第1C圖所 示，所謂具有熱流性質的絕緣材料118係指在高溫下具有 流動性質的絕緣材料。因此，在介電材料Π 2上覆蓋具有 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) 裝·'---」--Γ訂---------^ ου: Α7 Β7 五、發明說明（Γ) 熱流性質的絕緣材料118 ’在對此具有熱流性質的絕緣材料 118進行一熱流製程，而其在高溫下將具有流動性’因此可 流動的絕緣材料1 1 8可以塡入第1Β圖中’因化學機械硏磨 法產生的刮傷1 14與凹陷Π 6，同時亦使絕緣材料1 18提供 一較爲平坦的表面，如第1c圖所示。 上述具有熱流性質的絕緣材料Π8例如爲硼磷矽玻 璃，其係爲一種含有少量硼與磷的二氧化矽，其可藉著在 二氧化矽中加入卩出與Β2Η6而構成，或是使用含硼或含磷 的有機化合物作爲反應氣體亦可。其中，當硼磷矽玻璃中 硼的含量愈高時，有助於流動性，在本較佳實施例中硼含 量約爲4-7%(ν/ν)，磷含量約爲l_4%(v/v)，熱流溫度約爲 8〇0-95〇°C，進行約10-45分鐘，而形成厚度約爲2000-5000 埃左右之具有熱流性質的絕緣材料。 在上述絕緣材料II8提供一平坦的表面後，後續的半導 體製程將可較爲順利進行，如第1D圖所示，可在具有流動 性質的絕緣材料1 I8上再形成一介電層12〇，例如爲TE〇S 氧化物’而在介電層120中利用嵌金法（damascene)形成導 線（wmng hne)122、接觸窗（c〇ntact)(未繪出）或插塞 (plug)(未繪出)等內連線結構。由於因化學機械硏磨法造成 的刮傷與凹陷巳以絕緣材料填補而具有一平整的表面，故 可避免導電材料殘餘其中而引起的電性問題。 /本發明之較佳實施例係在介電材料經化學機械硏磨 後’在其上得覆蓋-層具熱流性質的絕緣材料藉以塡補 因化—機械硏齡產生的凹陷與刮傷，以使後續製程順利進 卜紙張尺度過財闕家^(CNS)A4規格（2】〇_ <請先閲讀背面之注意事項再填寫本頁) 裝· T 11 —，ίι-訂------- !产 經濟部智慧財產局貝工消费合作社印製 x 297公釐） 4〇·1. ()()ί Α7 ______Β7____ 五、發明說明（^ ) 行，而增進元件之可靠度。 雖然本發明已以一較佳實施例揭露如上’然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------------- 裝.J---·---L 訂---------_ * » /\ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐）4〇a54b 5 0 I 91 w t ', doc 0 0: A7 B7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (ί) The present invention relates to a semiconductor process for integrated circuits, and in particular A semiconductor process is used to improve the problems of chemical mechanical polishing (CMP) dishing and chatter marks. The chemical mechanical honing method is the only technology that can provide global planarization of semiconductor processes. It uses the principle of mechanical honing and cooperates with appropriate chemical agents to increase and decrease the surface of the wafer. A contouring technique that smoothes out the contours. The slurries used in the chemical mechanical honing process, also known as chemical additives, contain honing particles with extremely high hardness, while the chemical mechanical honing method uses abrasive properties. Very high particles for honing the wafer surface. However, due to the extremely high hardness of the above-mentioned honing particles, when the surface of some materials is honed by chemical mechanical honing, it is extremely easy to cause surface scratches, which causes bridges to occur in subsequent processes and affects components. Operation, resulting in reduced reliability. In addition, the chemical mechanical honing method usually requires a hard material layer as a stop layer to control the end point of the process. However, when chemical mechanical honing honing both the soft material layer and the hard material layer, since the honing rate of the soft material layer is faster than the hard material layer, when the hard material layer is used as a termination layer, Excessive honing of the soft material layer causes the phenomenon of depression, so that the difference in height between the hard material layer and the soft material layer can be as large as 500 Angstroms. The depression will cause electrical problems such as short circuit when the metal layer is inserted into the depression and cannot be removed when the metal layer is formed in subsequent processes. In view of this, the present invention is to provide a semiconductor process for modifying (please read the precautions on the back before filling this page). I ---- i--Γ Order ---------_ 191 '' 1 'd. 〇 5 A7 B7 i. Description of the invention (&); The depression of the material layer of the chemical mechanical honing method and the avoidance of scratches of the material layer surface by the chemical mechanical honing method are used to improve the reliability of the component. (Please read the notes on the back of Jing before filling out this page) The present invention provides a semiconductor process in which a component structure is formed on a substrate, and a cap layer is formed on the t-piece structure, and then a dielectric material is formed on the substrate. , Covering element structure. Continuing to use the cap layer as the termination layer, the dielectric material was honed by chemical mechanical honing, and the hard material layer was exposed. Next, an insulating material having a heat flow property is formed on the dielectric material and the element structure to provide a planarized surface. The present invention uses an insulating material that has flow properties at high temperatures to refill scratches and depressions caused by the dielectric material during honing by the chemical mechanical honing method, so that subsequent electrical problems can be avoided. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: Section 1A- The 1D diagram is a cross-sectional view showing a manufacturing process of a semiconductor process according to a preferred embodiment of the present invention. . Among them, a brief description of each icon number is as follows: Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 100: Base 102: Gate 104: Gap 106: Cover 108: Tight Area 1] 0: Loose Area 4 This paper standard applies Yin National Standard (CNS) A4 specification (210 X 297 public love) A7 B7 402¾48 5 Ο l 9 tw! '. Do. 00 5 V. Description of the invention ()) 112: Dielectric material 114: Scratch 116: Depression 118: Insulating material with heat flow properties 120: Dielectric layer 122: Wire embodiment The preferred embodiment of the present invention uses an insulating material with heat flow properties to compensate for scratches caused by chemical mechanical honing, and the use of an insulating material has The fluidity characteristic also improves the depression phenomenon 'so it can reduce the possibility of scratches or depressions causing the conductive material to remain in subsequent processes', thereby improving the reliability of the device. 1A-1D are cross-sectional views of a manufacturing process of a semiconductor system according to a preferred embodiment of the present invention. Referring to FIG. 1A, there are some element structures 102 on the substrate 100, and the element structures 102 are separated by a gap 104. The element structure 102 is, for example, a gate. The gate can be formed by a technique known to those skilled in the art, for example, after forming a polycrystalline silicon layer, a photoresist lithography process is performed. The side and top of the component structure 102 are covered with a cap layer] () 6, which is used to completely protect the unnecessary contact between the component structure 102 and other conductive materials to prevent leakage and other situations. The cover layer 〖〇6 — Generally composed of a harder material, such as a silicon nitride layer. Because of the circuit design (layout), the arrangement of component structures on the same wafer usually has both a tighter 108 and a looser 110 arrangement, as shown in Figure 1A, and a more closely arranged 108 component structure The gap between 102 and 104 is smaller, but wider 5 The paper size is in accordance with China National Standard (CNS) A4 (210 x 297 mm) (Please read the precautions on the back before filling out this page) * 装 · " T ---, --- Order --------- ^ · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 402548 ϊ 9tu | c} < A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the Invention (· /) There is a large gap between the element structures 106 of the loose arrangement 110. Next, referring to FIG. 1B, a dielectric material 112 is formed on the element structure 102, is inserted into the gap 104, and extends to the element structure 102. The dielectric material 112 is, for example, borophosphosilicate glass (BPSG). The chemical vapor deposition method has a thickness of about 4500-6000 angstroms, of which the boron content in the borophosphosilicate glass is about 3-5% (Wv) and the phosphorus content is about 4-5% (v / v). Phosphosilicate glass can provide a relatively flat surface after a heat flow process (reflow). The heat flow temperature is about 800-950 ° C and the operation time is about 15-60 minutes. Still referring to FIG. 1B, the chemical mechanical honing method is used, and the capping layer 106 is used as a stop layer to planarize the dielectric material 112 to expose the capping layer 106. The dielectric material Π2 penetrates into the gap 104 in FIG. 1A in. Since the honing particles in the chemical mechanical honing method are hard and the residual particles of the honing cap layer 106 are added, scratches 114 may appear on the softer dielectric material 112. In addition, since the loosely arranged element structures 102 are separated by a large distance, and the dielectric material 112 is relatively soft ', when the chemical mechanical honing is performed, the gaps 112 of the loosely arranged element structures 102 are liable to generate the depression 116. However, when the above-mentioned scratches 114 and depressions 116 will cause subsequent conductive materials to be deposited, the residues in the scratches 114 and depressions 116 may cause unnecessary electrical connections and cause bridging and the like. In order to prevent the occurrence of scratches and depressions, an insulating material with heat flow properties is formed on the dielectric material and the cover layer 106. μ, as shown in Figure 1C, the so-called insulation material 118 with heat flow properties refers to high temperature Under the flow of insulating materials. Therefore, the dielectric material Π 2 is covered with 6 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 cm) (please read the precautions on the back before filling this page). 》 --Γ 定 --------- ^ ου: Α7 Β7 V. Description of the invention (Γ) Heat-insulating material 118 'The heat-insulating material 118 has a heat-flow process, and its It will have fluidity at high temperature so the flowable insulating material 1 1 8 can be inserted into the 1B diagram 'scratch 1 14 and depression Π 6 caused by the chemical mechanical honing method, while also providing the insulating material 1 18 A relatively flat surface, as shown in Figure 1c. The above-mentioned insulating material with a heat flow property Π8 is, for example, borophosphosilicate glass, which is a kind of silicon dioxide containing a small amount of boron and phosphorus, which can be formed by adding osmium and B2Η6 to the silicon dioxide, or using Boron or a phosphorus-containing organic compound may be used as the reaction gas. Among them, when the boron content in the borophosphosilicate glass is higher, it contributes to fluidity. In the preferred embodiment, the boron content is about 4-7% (ν / ν), and the phosphorus content is about 1-4% (v / v), the heat flow temperature is about 8000-950 ° C, and it is performed for about 10-45 minutes to form an insulation material with heat flow properties with a thickness of about 2000-5000 angstroms. After the above-mentioned insulating material II8 provides a flat surface, the subsequent semiconductor process will proceed smoothly. As shown in FIG. 1D, a dielectric layer 12 may be formed on the insulating material 1 I8 having flow properties. For example, for the TE ’s oxide ’, a wire (wmng hne) 122, a contact window (not shown), or a plug (not shown) is formed in the dielectric layer 120 by using damascene. Draw) and other interconnect structures. Since the scratches and depressions caused by the chemical mechanical honing method are filled with insulating material and have a flat surface, electrical problems caused by the presence of conductive materials can be avoided. / A preferred embodiment of the present invention is that after the dielectric material is chemically and mechanically honed, it is covered thereon-a layer of insulating material with heat flow properties is used to compensate for the dents and scratches caused by mechanical ageing. Make the subsequent process smoothly enter the paper standard. (CNS) A4 specifications (2) 〇_ < Please read the precautions on the back before filling this page.) Equipment · T 11 — ， ίι-Order ---- ---! Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Industry and Economics x 297 mm) 4〇 · 1. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ------------- Install. J --- · --- L Order ---------_ * »/ \ (Please read the notes on the back before filling in this Page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 * 297 mm)