經漁"屮央標洛局爲工消費合作社印製 401619 五、發明説明（/ ) 發明領域： 本發明係有關於一種積體電路元件之製造，尤指有關於 一種在積邐璽路的製造串結合砍的局部氧也r locos ) mm 溝渠厘ILLgll. 成卒坦化腫離的方法^ 發明背景： 由於裝置技術係降至〇. 25微米的尺度，傳統式矽的局 部氧化（LOCOS )隔離之使用將限定於較小的通道寬度侵佔 物（鳥嘴）。淺溝渠隔離（STI )可被用以消除這些侵佔物， 特別是在超大型積體（ULSI )電路裝置中。爲了在STI後 獲得優良的平坦性，化學機械研磨（CMP )係經常地被使用。 然而，基於班磨墊的塑變，該溝渠的窗Q (open)區域將易於 產电碟狀化(dishing)。 圖1係舉例說明習知技術之部份完成的一積體電路裝 置。一墊氧化層12已被成長或沈積於一半導體基板1〇的表 面上。一氮化矽層14係被沈積於襯墊氧化物層的上方。基 板中之溝渠已被填充以氧化物17。參考圖2，氧化物17係 使用CMP研磨之。氧化物之碟狀化以及所產生之氧化物均勻 度之不足二者皆可見於寬區域19中。 寬區域中之LOCOS與窄區域中之STI的結合將可被用以 解決這些問題。不同的LOCOS與STI的結合已在習知技術中 被提出。例如 Mr. Mehta 之 U. S. Patent 5, 679, 599 揭露了 蝕刻一深溝渠並以氧化物填充之，其次使用場氧化以形成 LOCOS區域並將溝渠隔離區域平坦化。Mr. Chan等人擁有之 U. S. Patent 5, 696, 021則揭露了形成將於後序被部份触刻 2 紙張尺ϋ中國國家標準（CNS ) Λ4規格（ 210X297公釐） (請先閱讀背面之注意事項再填寫本頁)Jingyu " Yuyang Biaoluo Bureau printed 401619 for industrial and consumer cooperatives V. Description of invention (/) Field of the invention: The present invention relates to the manufacture of integrated circuit components, especially to Local oxygen produced by stringing and chopping is also r locos) mm ditch ILLgll. A method to reduce the swelling and death ^ Background of the invention: As the device technology is reduced to the 0.25 micron scale, the traditional local oxidation of silicon (LOCOS) The use of isolation will be limited to smaller channel width encroachment (bird's beak). Shallow trench isolation (STI) can be used to eliminate these encroachments, especially in very large integrated circuit (ULSI) circuit devices. In order to obtain excellent flatness after STI, a chemical mechanical polishing (CMP) system is often used. However, based on the plastic deformation of the pad, the window Q (open) area of the trench will be easily dished. Figure 1 illustrates an integrated circuit device completed as part of a conventional technique. A pad oxide layer 12 has been grown or deposited on the surface of a semiconductor substrate 10. A silicon nitride layer 14 is deposited over the pad oxide layer. The trenches in the substrate have been filled with oxide 17. Referring to Fig. 2, oxide 17 is polished using CMP. Both the dishing of the oxide and the deficiency in the uniformity of the oxide produced can be seen in the wide area 19. The combination of LOCOS in a wide area and STI in a narrow area can be used to solve these problems. Different combinations of LOCOS and STI have been proposed in the prior art. For example, U.S. Patent 5, 679, 599 of Mr. Mehta discloses etching a deep trench and filling it with an oxide, followed by field oxidation to form a LOCOS region and planarize the trench isolation region. US Patent 5, 696, 021, owned by Mr. Chan and others, revealed that the formation will be partially engraved in the subsequent sequence. 2 Paper size: Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the back (Please fill in this page again)
40,1619 經浼部中央搲準功員工消费合作社印裝 B7 五、發明説明（J) 移除的FOX區域。溝渠在後序將被填充以額外場氧化之FOX 區域的角壁將被蝕刻。Mr. Bashir等人之U.S. Patent 5, 683, 932以及5, 411，913二案揭示以氧化物或多晶砂填充 溝渠並以回蝕將表面平坦化於寬區域中的表面以光阻罩幕 覆蓋時。Mr. Madan 之 U. S. Patent 5, 350, 941 則揭露了形 成FOX區域，其次蝕刻穿過FOX以形成均勻寬度之深溝渠。 該溝渠將於後序被填充以氧化物或多晶矽。 發明概述： 因此，本發明之主要目的係爲提供一種在積體電路製造 中形成平坦化隔離用之方法。 .· 一-- 5 本發明之另一目的係爲提供一種f成氧化物碟狀化將 被消除之平坦化隔離的¥法。 本發明之又另一目的係爲提供一種襄虫結合JL0C0S與 STI隔離方法以形成平坦化隔離之方法。 本發明之再一目_爲_提供二種藉由使用寬區域中之 LOCOS與窄區域中之STI以形成平里化 根據本發明之諸言的，p看备由結合LOCOS與STI隔離 方垮以形成平坦化_離用之方法將被獲得。一襯墊氧化物層 係被沈積於一半導體基板的表面。第一層氮化物層係被沈積 於襯墊氧化物層上方。該第一層氮化物層與襯墊氧化物層係 被蝕刻穿過其未爲罩幕所覆蓋之處，以提供半導體基板表面 將被暴露出之窗口（opening)，其中至少有一寬窗口與至少 一窄窗口被暴露出。而第二層氮化物層係被沈積於第一層氮 化物層上以及窗口中，並被回蝕以留下窗口邊緣的間隙g 3 (請先閱讀背面之注意事項再填寫本頁) i#ΐτ • nn m I i— n^i· · 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 401619 A 7 B7 五、發明説明 (spacer)，其中該窄窗口係爲間隙壁所填充。在寬窗口中所 暴露出之半導體基板係被氧化，其中一場氧化物區域係被形 成於寬窗口中。第一層氮化物層與間隙壁的一部份係被蝕刻 移除而使窄窗口中的半導體基板被暴露出。一溝渠將被蝕刻 於窄窗口中所暴露的半導體基板中。一氧化物層係被沈積於 第一層氮化物層以及場氧化物區域上方並填充該溝渠，其中 填充該溝渠之氧化物層將形成一淺溝渠隔離區域。該氧化物 層係被研磨至位於第一層氮化物層之研磨終點。該第一層氮 化物層、諸間隙壁以及襯墊氧化物層係被移除，以在積體電 路裝置的製造中完成一場氧化物區域以及一淺溝渠隔離區 域二者的形成者。 圖式之簡單說明： 圖1及圖2係爲習知技術之較佳實施例的剖面示意圖。 圖3至圖12係本發明之較佳實施例的剖面示意圖。 圖13係以本發明之方法所製造之完整的積體電路裝置 的剖面示意圖。 圖號說明： 泞治部中央掠苹局只工消资合作杜印^. 10 -半導體基板 14 -氮化砂層 17 —氧化物 20 -氮化矽層 26 - FOX 32 —閘極 36 -介電隔離層 12 -墊氧化層 15 -窄區域 19 —寬區域 22 -間隙壁 30 -氧化物層 34 —源/汲極 38 —電性接觸 (請先閲讀背面之注意事項再填寫本頁)40,1619 Printed by the Central Ministry of Economics and Social Work, Consumer Cooperative B7 V. Description of Invention (J) FOX area removed. The trenches will be etched in the corner walls of the FOX region which will be filled with additional field oxidation in the subsequent sequence. US Patent Nos. 5, 683, 932 and 5, 411, 913 by Mr. Bashir et al. Disclose that trenches are filled with oxide or polycrystalline sand and the surface is flattened over a wide area with etchback. When covering. Mr. Madan's U.S. Patent 5, 350, 941 revealed the formation of the FOX area, followed by etching through the FOX to form deep trenches of uniform width. The trench will be filled with oxide or polycrystalline silicon at a later stage. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for forming planarization isolation in the manufacture of integrated circuits. .. 1-5 Another object of the present invention is to provide a ¥ method of f-forming oxide dishing and flattening isolation to be eliminated. Still another object of the present invention is to provide a method for forming a planarized isolation by combining a worm isolation method with JLOCOS and STI. A further aim of the present invention is to provide two types of flattening by using LOCOS in a wide area and STI in a narrow area. According to the words of the present invention, p is prepared by combining LOCOS and STI isolation. A method for forming a flattening_offset will be obtained. A pad oxide layer is deposited on a surface of a semiconductor substrate. A first nitride layer is deposited over the pad oxide layer. The first nitride layer and the pad oxide layer are etched through the area not covered by the mask to provide a window on which the surface of the semiconductor substrate will be exposed. At least one of the wide windows and at least one A narrow window was exposed. The second nitride layer is deposited on the first nitride layer and in the window, and is etched back to leave a gap at the edge of the window. G 3 (Please read the precautions on the back before filling this page) i # ΐτ • nn m I i— n ^ i · · This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 401619 A 7 B7 V. Description of the invention (spacer), in which the narrow window is a space wall filling. The semiconductor substrate exposed in the wide window is oxidized, and a field oxide region is formed in the wide window. The first nitride layer and a part of the spacer are removed by etching to expose the semiconductor substrate in the narrow window. A trench will be etched into the semiconductor substrate exposed in the narrow window. An oxide layer is deposited over the first nitride layer and the field oxide region and fills the trench, wherein the oxide layer filling the trench will form a shallow trench isolation region. The oxide layer is ground to the end point of the first nitride layer. The first nitride layer, the spacers, and the pad oxide layer are removed to complete the formation of both a field oxide region and a shallow trench isolation region in the fabrication of the integrated circuit device. Brief description of the drawings: FIG. 1 and FIG. 2 are schematic sectional views of a preferred embodiment of the conventional technology. 3 to 12 are schematic sectional views of a preferred embodiment of the present invention. Fig. 13 is a schematic cross-sectional view of a complete integrated circuit device manufactured by the method of the present invention. Explanation of drawing number: The Central Government Bureau of the Ministry of Mud and Governance and Industrial Cooperation and Cooperation Du Yin ^. 10-semiconductor substrate 14-nitrided sand layer 17-oxide 20-silicon nitride layer 26-FOX 32-gate 36-dielectric Isolation layer 12-pad oxide layer 15-narrow area 19-wide area 22-spacer 30-oxide layer 34-source / drain 38-electrical contact (please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） 401619 五、發明説明（厶） 發明之詳細說明： 請參考圖3，其係圖示一半導體基板10，一襯墊氧化 矽層12係被成長於半導體基板表面形成大約50至500A之 間的厚度。一氮化矽層14係被沈積於襯墊氧化物層12上方 具有大約1G0G至3G0GA之間的厚度。 請再參考圖4，一未示於圖中的光阻罩幕將被形成於氮 化物層的表面上，其中隔離區域將被形成於其中的窗口係被 留置。使用傳統式光學微影以及蝕刻技術，該氮化物與襯墊 氧化物層係被蝕刻以將隔離區域被形成於其中的半導體基 板暴露出。這些隔離區域包含諸如15之窄區域以及諸如19 之寬區域。該窄區域15將小於大約0.2微米的寬度而寬區 域19將大於大約0. 3微米的寬度。 現參考圖5，一氮化矽層2(3係以化學氣相沈積（CVD ) 沈積大約5GG與2GGGA之間的厚度於基板之表面。 氮化矽層20將被非等向性地回蝕刻以留下間隙壁22於 氮化物層14之側壁，如圖6所示。間隙壁22完全覆蓋窄區 域15中的窗口。氮化矽間隙壁22具有大約500與2000A之 間的寬度。 其次’場氧化步驟係使用傳統場氧化條件。場氧化區域 FOX 26係被形成於寬區域19中，如圖7所示。因爲窄窗口 15中的半導體基板係爲氮化矽間隙壁22所覆蓋，所以窄窗 口中並無場氧化層之形成。 現在’氮化物層14與氮化物間隙壁22係使用諸如熱 H3P〇4或以氮化物相對於氧化物與矽有高度選擇性的乾式蝕 5 本紙浪尺度適用ψΐ國家標( CNS ) A^L格（2獻297公釐) '"— - (請先閱讀背面之注意事項再填荈本頁〕This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) 401619 V. Description of the invention (厶) Detailed description of the invention: Please refer to Figure 3, which shows a semiconductor substrate 10 and a pad of silicon oxide The layer 12 is grown on the surface of the semiconductor substrate to a thickness between about 50 and 500 A. A silicon nitride layer 14 is deposited over the pad oxide layer 12 and has a thickness between about 1 G0G and 3 G0GA. Please refer to FIG. 4 again, a photoresist mask not shown in the figure will be formed on the surface of the nitride layer, and the window system in which the isolation region is to be formed is left in place. Using conventional optical lithography and etching techniques, the nitride and pad oxide layers are etched to expose the semiconductor substrate in which the isolation region is formed. These isolation areas include narrow areas such as 15 and wide areas such as 19. The narrow region 15 will be less than a width of about 0.2 microns and the wide region 19 will be greater than a width of about 0.3 microns. Referring now to FIG. 5, a silicon nitride layer 2 (3 is deposited by chemical vapor deposition (CVD) with a thickness between about 5GG and 2GGGA on the surface of the substrate. The silicon nitride layer 20 will be anisotropically etched back The spacer 22 is left on the sidewall of the nitride layer 14, as shown in Fig. 6. The spacer 22 completely covers the window in the narrow region 15. The silicon nitride spacer 22 has a width between about 500 and 2000 A. Next ' The field oxidation step uses conventional field oxidation conditions. The field oxidation region FOX 26 is formed in a wide region 19, as shown in FIG. 7. Because the semiconductor substrate in the narrow window 15 is covered by a silicon nitride spacer 22, There is no field oxide layer formed in the narrow window. Now the nitride layer 14 and the nitride spacer 22 are dry etching such as hot H3P04 or nitride with high selectivity relative to oxide and silicon. Standards apply to the national standard (CNS) A ^ L grid (2 offering 297 mm) '" —-(Please read the precautions on the back before filling this page]
619 經治部中决¾隼局爲工消费合作杜印裂 A7 ' _ B7 五、發明説明（上） 刻而被部份地蝕刻移除。其結果結構係圖示於圖8。 現在，參考圖9，窄區域15中所暴露的半導體基板係 被蝕刻至大約2GGG與1G00GA之間的深度以形成溝渠。 現在，參考圖10，一層氧化物層30係以CVD沈積於基 板表面上並填充溝渠。氧化物層30具有大約3G00與15000A 之間的厚度。 將氧化物層30以CMP研磨至位於氮化物層14之研磨終 點，如圖11所舉例說明。 寬溝渠之碟狀化將因爲場氧化物區域26的出現而被消 除。因爲場氧化物區域26將填充寬溝渠，所以將無碟狀化 產生。 最後，參考圖12，氮化矽層14與間隙壁22係使用傳 統濕式蝕刻而個別地被移除。其次，墊氧化層12與在場氧 化區域邊緣的氧化物30亦被移除，以完成隔離區域的形成， 亦即窄區域15中的淺溝渠隔離30以及寬區域19中的LOCOS 26 〇 接著，如習知技術之傳統加工將被進行。例如，包含閘 極電極32以及源極與汲極區34的半導體裝置結構將如習知 技術之傳統加工而被形成於隔離區之間的主動區。電性接觸 38將穿過介電隔離層36而製作，如圖13所示。 本發明之方法將藉由結合窄g域中的淺溝渠隔離 _ (STI )與寬區域中的<砍@局部氧化（LOCOS 隔離形成。窄區域中STI的使用將可避免由LOCOS之鳥嘴侵 佔物所引起之通道長度被縮短，而寬區域中LOCOS的使用# 6 本紙張尺度適ϊϋ國國家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁}619 The Ministry of Economic Affairs of the People's Republic of China decided that the Industrial and Commercial Cooperation for Industrial and Consumer Cooperation Du Yincha A7 '_ B7 V. Description of the Invention (above) was partly etched and removed. The resulting structure is shown in FIG. 8. Referring now to FIG. 9, the semiconductor substrate exposed in the narrow region 15 is etched to a depth between about 2GGG and 1G00GA to form a trench. Referring now to FIG. 10, an oxide layer 30 is deposited on the substrate surface by CVD and fills the trenches. The oxide layer 30 has a thickness between approximately 3 G00 and 15000 A. The oxide layer 30 is polished by CMP to the polishing end point of the nitride layer 14, as illustrated in FIG. The dishing of wide trenches will be eliminated by the presence of field oxide regions 26. Because the field oxide region 26 will fill the wide trench, no dishing will occur. Finally, referring to Fig. 12, the silicon nitride layer 14 and the spacer 22 are individually removed using conventional wet etching. Secondly, the pad oxide layer 12 and the oxide 30 on the edge of the field oxidation region are also removed to complete the formation of the isolation region, that is, the shallow trench isolation 30 in the narrow region 15 and the LOCOS 26 in the wide region 19. Then, Traditional processing such as conventional techniques will be performed. For example, the semiconductor device structure including the gate electrode 32 and the source and drain regions 34 will be formed in the active region between the isolation regions as conventionally processed by conventional techniques. Electrical contacts 38 are made through the dielectric isolation layer 36, as shown in FIG. The method of the present invention will be formed by combining a shallow trench isolation (STI) in a narrow g domain with < @@ Local Oxidation (LOCOS isolation) in a wide area. The use of STI in a narrow area will avoid the bird's beak of LOCOS The length of the channel caused by the encroachment is shortened, and the use of LOCOS in a wide area # 6 This paper is sized to the national standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page}
r|〇iai9 A7 B7 五、發明説明（t) 可消除爲寬區域之STI平坦化所引起碟狀 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，且本發明亦可推廣應用到積體電路中任何導 電結構間之隔離，因此熟知此技藝的人士應能明瞭，適當而 作些微的改變與調整，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍，故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 (請先閲讀背面之注意事項再填寫本頁 、\一3 烀#部中央標準局H.T-消费合作社印製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐）r | 〇iai9 A7 B7 V. Description of the invention (t) The dishing caused by the STI flattening of a wide area can be eliminated. The above description uses the preferred embodiments to describe the present invention in detail, but not to limit the scope of the present invention. The invention can also be popularized and applied to the isolation between any conductive structures in integrated circuits. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the invention or depart from it. The spirit and scope of the invention should be regarded as further implementation of the invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. (Please read the notes on the back before filling in this page. \ 一 3 烀 #Ministry of Central Standards Bureau Printed by H.T-Consumer Cooperatives. This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm)