TW400617B - The manufacture method of node contact - Google Patents

The manufacture method of node contact Download PDF

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Publication number
TW400617B
TW400617B TW087120802A TW87120802A TW400617B TW 400617 B TW400617 B TW 400617B TW 087120802 A TW087120802 A TW 087120802A TW 87120802 A TW87120802 A TW 87120802A TW 400617 B TW400617 B TW 400617B
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TW
Taiwan
Prior art keywords
contact window
node contact
manufacturing
patent application
window opening
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Application number
TW087120802A
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Chinese (zh)
Inventor
Jian-Hua Tsai
Guo-Chi Lin
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United Microelectronics Corp
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Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW087120802A priority Critical patent/TW400617B/en
Priority to US09/246,761 priority patent/US6191042B1/en
Application granted granted Critical
Publication of TW400617B publication Critical patent/TW400617B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A manufacture method of node contact. Such method provides a substrate, and forms a dielectrcs on the substrate, using C4F8/Ar/CH2F2 etch agent-first to etch and to form an opening. Next, to use CHF3/CO etch agent to etch part of the dielectrics below the opening until the substrate is naked. Thus, it forms node contact via opening.

Description

經濟部中央標準局員工消費合作社印製 3950twf. doc/006 A 7 B7 五、發明説明（/ ) 本發明是有關於一種動態隨機存取記憶體（D y n a m i c Random Access Memory ; DRAM)的製造方法，且特別是有 關於一種動態隨機存取記憶體之節點接觸窗開□的製造 方法。 在半導體製程逐漸邁入0.25μπι尺寸時，.在動態隨機 存取記憶體的製程中，不論是字元線（Word Line)、位元 線（Bit Line)與節點接觸窗的寬度’以及節點接觸窗至字 元線、位元線的距離，都得隨著設計規則（Design Rule) 縮小。現今以光阻定義電容元件與源極/汲極區的節點接 觸窗製程時，節點接觸窗的最小極限爲直徑〇.24μίη。當進 行個別的光罩（Masking)步驟，源極/汲極區的節點接觸窗 必須對準源極/汲極區，而較大的節點接觸窗則相對有較 少的預留誤差範圍，也相對的擁有較低的對準準確度 (Alignment Accuracy ; AA)，因此容易使得電容元件之節 點接觸與其周圍的位元線接觸，造成元件短路的現象。 習知爲了縮小節點接觸窗之尺寸，提出兩種節點接觸 窗的製造方法，一是光阻熱回流（Photoresist Ref low)之 節點接觸窗開口製造方法，另一是多晶矽間隙壁之節點接 觸窗開口製造方法。 請參照第1A圖至第1C圖，其所繪示爲習知一種光阻 熱回流之節點接觸窗開口製造方法的流程剖面圖。 請參照第1A圖，首先提供一基底100，其上已形成有 介電層102、位元線1〇6與介電層104。接著，於介電層 104上形成具有開口 11〇之光阻層1〇8，以裸露出介電層 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------------^~ 訂 J------ (請先閱讀背面之注意事項再填寫本頁) 3950twf.doc/006 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（；！） 104之部分表面。 請參照第1B圖，進行一熱回流步驟，使光阻108因 爲加熱而流動性增加，形成光阻108a，並具有較小之開口 110a。 請參照第1C圖，以光阻108a爲罩幕，進行節點接觸 窗開口 112之鈾刻製程，在介電層104與102中形成節點 接觸窗開口 112暴露出基底100。 此習知光阻熱回流之節點接觸窗開口製造方法由於 在進行熱回流步驟時，需要使用特殊機器設備進行，爲此 方法不易執行之一項缺點。 請參照第2A圖至第2B圖，其所繪示爲習知一種多晶 矽間隙壁之節點接觸窗開口製造方法之流程剖面圖。 請參造第2A圖，首先提供一基底200，其上已形成有 介電層202、介電層204與位元線206。接著，於介電層 204上形成具有開口 224之多晶矽層210，以裸露出介電 層204之部分表面。之後，於多晶矽層210上形成與開口 224共形之多晶矽層212。 請參照第2B圖，進行蝕刻步驟，去除部分多晶矽層 212，於開口 224之側壁形成間隙壁212a。接著，以多晶 矽層210與間隙壁212a爲罩幕，在進行一蝕刻步驟，在 介電層204與202中形成節點接觸窗開口 220，直到裸露 出基底200之表面。 雖然上述以多晶矽間隙壁製造之節點接觸窗開口可 以縮小節點接觸窗之尺寸，但是，此方法包括形成兩層以 4 本紙張尺度適用中國國家標準（CNS ) A4規格（ilOX297公釐） (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3950twf.doc / 006 A 7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a Dynamic Random Access Memory (DRAM). In particular, it relates to a method for manufacturing a node contact window of a dynamic random access memory. As the semiconductor process gradually moves into the 0.25μπι size, in the process of dynamic random access memory, regardless of the width of the word line, bit line and node contact window 'and node contact, The distance from the window to the character line and bit line must be reduced according to the Design Rule. At present, when a photoresistance is used to define a process of making a contact window between a capacitive element and a node in a source / drain region, the minimum limit of the contact window of the node is 0.224 μίη. When performing individual masking steps, the node contact window of the source / drain region must be aligned with the source / drain region, while the larger node contact window has relatively less reserved error range. Relatively, it has a low alignment accuracy (AA), so it is easy to make the node contact of the capacitor element contact with the bit lines around it, causing a short circuit of the element. Conventionally, in order to reduce the size of the contact window of a node, two methods of manufacturing the contact window of a node are proposed. One is a method for manufacturing a node contact window opening of Photoresist Ref low, and the other is a node contact window opening of a polycrystalline silicon spacer. Production method. Please refer to FIG. 1A to FIG. 1C, which are flow cross-sectional views showing a conventional method for manufacturing a node contact window opening for photoresistive thermal reflow. Referring to FIG. 1A, a substrate 100 is first provided, on which a dielectric layer 102, a bit line 106, and a dielectric layer 104 have been formed. Next, a photoresist layer 108 having an opening 11 is formed on the dielectric layer 104 to expose the dielectric layer 3. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ----- ---------- ^ ~ Order J ------ (Please read the notes on the back before filling this page) 3950twf.doc / 006 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (;!) Part of the surface of 104. Referring to FIG. 1B, a thermal reflow step is performed to increase the fluidity of the photoresist 108 due to heating, forming the photoresist 108a, and having a smaller opening 110a. Referring to FIG. 1C, the photoresist 108a is used as a mask to perform the uranium engraving process of the node contact window opening 112, and the node contact window opening 112 is formed in the dielectric layers 104 and 102 to expose the substrate 100. This conventional method for manufacturing a contact-contact window opening for photoresistive thermal reflow requires special machinery and equipment to perform the thermal reflow step, which is a disadvantage that is difficult to implement. Please refer to FIG. 2A to FIG. 2B, which are cross-sectional views showing a conventional method for manufacturing a contact opening of a node of a polycrystalline silicon spacer. Please refer to FIG. 2A. First, a substrate 200 is provided, on which a dielectric layer 202, a dielectric layer 204, and a bit line 206 have been formed. Next, a polycrystalline silicon layer 210 having an opening 224 is formed on the dielectric layer 204 to expose a part of the surface of the dielectric layer 204. Thereafter, a polycrystalline silicon layer 212 conforming to the opening 224 is formed on the polycrystalline silicon layer 210. Referring to FIG. 2B, an etching step is performed to remove a portion of the polycrystalline silicon layer 212, and a partition wall 212a is formed on a side wall of the opening 224. Next, using the polycrystalline silicon layer 210 and the spacer 212a as a mask, an etching step is performed to form a node contact window opening 220 in the dielectric layers 204 and 202 until the surface of the substrate 200 is exposed. Although the above-mentioned node contact window opening made of polycrystalline silicon spacer wall can reduce the size of the node contact window, this method includes forming two layers to apply the Chinese National Standard (CNS) A4 specification (ilOX297 mm) at 4 paper sizes (please first (Read the notes on the back and fill out this page)

95〇tWf.d〇c/006 A7 B7 經濟部中央標準局員工消費合作社印製 五 ' 發明説明（冬） 上的多晶矽層，且需進行兩次以上的蝕刻步驟，以形成所 爾之節點接觸窗開口，因此提高了製作成本。 因此本發明之目的，就是在提供一種節點接觸窗開口 的製造方法，此方法僅使用特殊之蝕刻劑能簡化製程，且 不需使用特殊之機械設備。， 本發明之另一目的，就是在解決習知之多晶矽間隙壁 之節點接觸窗製造方法中，爲達到縮小節點接觸窗之尺寸 的自的，必須形成兩層以上的多晶矽層，且需進行兩次以 上的蝕刻步驟，使得成本提高等缺點。 爲達成上述和其他目的，本發明提出一種節點接觸窗 的製造方法’此方法簡述如下：提供一基底，且於基底上 形成有一層介電層’於該介電層上，以C4F8/Ar/CH2F2爲蝕 刻劑進行蝕刻步驟’形成開口，接著以CHF3/CO爲蝕刻劑， 再進行蝕刻步驟，蝕刻部份開口下的介電層，直到裸露出 該基底’形成一節點接觸窗開口。本發明之特徵在於僅使 用GFs/Ar/CHA爲蝕刻劑，因此可簡化製程並降低製造成 本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1C圖係顯示習知一種光阻熱回流之節點 接觸窗開口製造方法之流程剖面圖； 第2A圖至第2B圖係顯示習知一種多晶矽間隙壁之節 本紙張尺度適用中國國家插準（CNS )八4规格（2丨〇><297公釐） (請先閱讀背面之注意事項再填寫本頁)95〇tWf.d〇c / 006 A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China on the 5th of the invention description (Winter) polysilicon layer on the surface, and more than two etching steps are required to form the node contact The window openings therefore increase manufacturing costs. Therefore, an object of the present invention is to provide a method for manufacturing a node contact window opening. This method can simplify the manufacturing process by using only a special etchant, and does not require special mechanical equipment. Another object of the present invention is to solve the conventional method for manufacturing a node contact window of a polycrystalline silicon spacer wall. In order to reduce the size of the node contact window, two or more polycrystalline silicon layers must be formed, and it needs to be performed twice. The above etching steps cause disadvantages such as cost increase. To achieve the above and other objectives, the present invention proposes a method for manufacturing a node contact window. This method is briefly described as follows: a substrate is provided, and a dielectric layer is formed on the substrate. On the dielectric layer, C4F8 / Ar is used. / CH2F2 is used as an etchant to perform an etching step to form an opening, and then CHF3 / CO is used as an etchant to perform an etching step, and the dielectric layer under the part of the opening is etched until the substrate is exposed to form a node contact window opening. The present invention is characterized by using only GFs / Ar / CHA as an etchant, thereby simplifying the manufacturing process and reducing the manufacturing cost. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1A Figures 1 to 1C are cross-sectional views showing a conventional method for manufacturing a contact-resistance window opening of a photoresistive thermal reflow node; Figures 2A to 2B show a conventionally known section of a polycrystalline silicon spacer wall. (CNS) 8 4 specifications (2 丨 〇 < 297 mm) (Please read the precautions on the back before filling this page)

3 95 0twf.doc/006 3 95 0twf.doc/006 經濟部中央標準局員工消費合作社印製 A7 _____B7____ 五、發明説明（¥ ) 點接觸窗開口製造方法之流程剖面圖；以及 第3A圖至第3C圖係顯示根據本發明較佳實施例之節 點接觸窗開口的製造方法。 其中，各圖標號與構件名稱之關係如下： 100、200、300 :基底 102、104、202、204、302、304 :介電層 106、206、306 ··位元線 108、108a、308 :光阻層 110、110a、224、310、312 :開口 112、220、316 :節點接觸窗開口 210、212 :多晶矽層 212a:間隙壁 314 :高分子層 實施例 弟3A圖至第3C圖所τρ:，爲根據本發明—較佳實施例 之節點接觸窗開口的製造方法。 S靑爹照第3A圖’首先提供一基底3〇〇，其上已形成有 力電層302、介電層304與fiz·兀線306。其中，介電層302 及介電層304之材質包括氧化矽或硼磷砂玻璃（BpsG)，形 成的方法例如爲化學氣相沈積法。接著，在基底3〇〇上开多 成光阻層308，此光阻層308並具有一開□ 31〇。 請參照第3B圖’以光阻層308爲硬罩幕，進行一触 刻步驟，以GFJAr/CHA爲蝕刻劑，蝕刻介電層3〇4形成 開口 312 ’控制餓刻步驟中各成分蝕刻劑的比例，以形成 6 本&張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）’^-------- (請先閲讀背面之注意事項再填寫本頁> .裝· 訂」 395 0twf.d〇c/006 A7 B7 五、發明说明（g ) ---------裝1.1 (請先閲讀背面之注意事項再填寫本頁) 開口 312，並藉由調整蝕刻劑的成分比例，控制所形成開 口 312之大小，此開口 312的大小將控制後續製程中所形 成節點接觸窗的開口大小，以本發明之方法所形成之開口 312,其開口 312深度，是藉由調配蝕刻劑的比例控制， 並不受蝕刻時間的影響。由於蝕刻劑C4F8/Ar/CH2F2中，C4F8 與ch2f2分子經由碰撞後會形成高分子，因此以 GF8/Ar/CH2F2爲蝕刻劑，進行一蝕刻步驟時，經由c4F8與 CH2F2所形成的高分子會在蝕刻過程中，同時沈積在介電層 304表面形成高分子層314保護介電層304，使其不被鈾 刻去除’介電層304表面因高分子的覆蓋而蝕刻面積逐漸 減小，且開口 312兩側側壁會逐漸累積高分子，藉由累積 高分子的量可控制開口 312大小，所形成的開口 312爲一 曲面，當局分子爲全覆蓋開口 312表面，開口 312即不再 被飩刻312 ’因此開口 312深度不受蝕刻時間影響，且開 口 312側壁上高分子層314的厚度大於開口 312底部高分 子層314之厚度。其中，本實施例以蝕刻劑C4F8/Ar/CH2F2 爲例，其它具有相同性質能在蝕刻過程中產生高分子的餓 刻劑也能應用於本發明。 經濟部中央標準局貝工消費合作社印製 i靑參照第3C圖’以光阻層308和高分子層314爲罩 幕’再進行一蝕刻步驟，此蝕刻之方法包括乾式蝕刻法， 較佳是以CHh/CO爲蝕刻劑，或其它對高分子層314與介 電層302、304具高選擇比的蝕刻劑，進行蝕刻，由於開 .口 312中央底部高分子層314厚度較開口 312兩側薄，且 由於蝕刻劑對高分子層314與介電層302、304具高選擇 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 3950twf.doc/006 A7 B7 五、發明説明（（） 比’亦即高分子層314之蝕刻速率遠低於介電層304，因 此在開口 312中心之極薄的高分子層314經由去除後，會 繼續蝕刻去除由高分子層314暴露出的介電層304與介電 層3 0 2 ’形成節點接觸窗開口 316。由於開口 312兩側高 分子層314厚度較厚在蝕刻過程中，不會完全被去除，仍 能覆蓋住介電層304，保護開口 312兩側高分子層314下 之介電層304被蝕刻，而開口中央極薄的高分子層314經 蝕刻後暴露出之介電層304能輕易的再被繼續蝕刻至介電 層302，直至暴露出基底300，形成較開口 312小之節點 接觸窗開口 316。 然後，在節點接觸窗開口 316中，形成電容結構（未 顯示），其包括一下電極（未顯示），一介電層（未顯示）與 一上電極（未顯示），其中下電極透過節點接觸窗開口 316 與基底中之源極/汲極區（未繪出）其中之一作電性連接。 於是完成本發明之動態隨機存取記憶體結構。其中，下電 極的材料可爲摻雜多晶矽，介電層之材質例如爲氧化矽、 氮化砂層/氧化矽層（NO)結構、氧化矽層/氮化砍層/氧化 矽層（0N0)結構或五氧化二鉬（Ta2〇5)、Pb(Zr, Ti)Ch，即 PZT以及（Ba，Sr)Ti〇3，即BST等高介電常數的材料。上 電極之材質例如爲摻雜多晶矽，形成的方法例如爲化學氣 相沈積法，在沈積多晶矽層的同時摻入雜質。 綜上所述，本發明之特徵在於： 1.在本發明中，不需使用特殊之機械設備，故可解 決習知光阻熱回流之節點接觸窗開口製造方法的缺點。 8 — -—-. —- - 1 丨· 丨丨 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閣讀背面之注意事項再填寫本頁) 訂 3950twf.doc/006 3950twf.doc/006 經濟部中央標準局員工消費合作社印製 A7 ----—------___B7 五、發明説明（？） 、一 2.本發明中，不需形成兩層以上的多晶矽層，以及 進行兩次以上的蝕刻步驟，因此可解決習知多晶矽間隙壁 節點接觸窗開口製程方法成本過高等問題。 3.本發明使用之蝕刻劑，（^扒與⑶而分子經由碰撞 後會形成高分子之原理，簡化製程及降低製造成本。 一 4.本發明中所使用之蝕刻劑在蝕刻過程中’會產生 局分子覆盡介電層’蝕刻介電層形成節點接觸窗開口時， 可藉由f制蝕刻過程中之蝕刻劑中各成分的比例，藉由控 制累積高分子的量’可控制所形成之節點接觸窗開口大 小。 5.以本發明之方法所形成之開口，其開口深度，是 藉由調配蝕刻劑的比例控制，並不受蝕刻時間的影響。. 6·本發明之製程與現有製程相容，極適合廠商生產 安排。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限疋本發明’任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 本紙張適用中關家( cns》八槻^(nox π7公瘦5 ---------------I I (請先閲請背面之注意事項再填寫本頁) .T-1TJ-----®----------------3 95 0twf.doc / 006 3 95 0twf.doc / 006 A7 printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs _____B7____ 5. Description of the invention (¥) Process sectional view of the manufacturing method of point contact window openings; and Figures 3A to 3D FIG. 3C shows a method for manufacturing a node contact window opening according to a preferred embodiment of the present invention. The relationship between each icon number and the component name is as follows: 100, 200, 300: substrates 102, 104, 202, 204, 302, 304: dielectric layers 106, 206, 306 · bit lines 108, 108a, 308: Photoresist layer 110, 110a, 224, 310, 312: openings 112, 220, 316: node contact window openings 210, 212: polycrystalline silicon layer 212a: spacer 314: polymer layer embodiment 3a to 3c τρ : Is a method for manufacturing a node contact window opening according to the present invention-a preferred embodiment. First, according to FIG. 3A, a substrate 300 is provided, on which a force layer 302, a dielectric layer 304, and a fiz · line 306 have been formed. The material of the dielectric layer 302 and the dielectric layer 304 includes silicon oxide or borophosphate sand glass (BpsG), and the method of forming the dielectric layer is, for example, a chemical vapor deposition method. Next, a photoresist layer 308 is formed on the substrate 300, and the photoresist layer 308 has a photoresist 3110. Please refer to FIG. 3B. 'Using the photoresist layer 308 as a hard mask, perform a touch-etching step, and use GFJAr / CHA as an etchant to etch the dielectric layer 304 to form an opening 312. Ratio to form 6 copies of & Zhang scales applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) '^ -------- (Please read the precautions on the back before filling out this page >. Binding and ordering ”395 0twf.d〇c / 006 A7 B7 V. Description of the invention (g) --------- 1.1 (Please read the precautions on the back before filling this page) Opening 312, and borrow The size of the opening 312 is controlled by adjusting the composition ratio of the etchant. The size of this opening 312 will control the opening size of the node contact window formed in the subsequent process. The opening 312 formed by the method of the present invention has a depth of the opening 312. , Is controlled by the proportion of the etchant, and is not affected by the etching time. In the etchant C4F8 / Ar / CH2F2, the molecules of C4F8 and ch2f2 will form a polymer after collision, so GF8 / Ar / CH2F2 is used as the etching Agent, a polymer formed by c4F8 and CH2F2 during an etching step During the etching process, a polymer layer 314 is deposited on the surface of the dielectric layer 304 to protect the dielectric layer 304 from being removed by uranium. The surface of the dielectric layer 304 is gradually reduced due to the coverage of the polymer, and Macromolecules will gradually accumulate on both sides of the opening 312. The size of the opening 312 can be controlled by the amount of accumulated polymer. The formed opening 312 is a curved surface. The molecules of the authority completely cover the surface of the opening 312, and the opening 312 is no longer engraved. 312 'Therefore, the depth of the opening 312 is not affected by the etching time, and the thickness of the polymer layer 314 on the side wall of the opening 312 is greater than the thickness of the polymer layer 314 at the bottom of the opening 312. In this embodiment, the etchant C4F8 / Ar / CH2F2 is used as an example. Other hungry engraving agents with the same properties that can generate polymers during the etching process can also be applied to the present invention. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, referring to Figure 3C, with the photoresist layer 308 and the polymer layer 314 is a mask, and another etching step is performed. The etching method includes a dry etching method, preferably using CHh / CO as an etchant, or other polymer layers 314 and dielectric layers 302 and 304. Select a ratio of etchant for etching, because the thickness of the polymer layer 314 at the bottom of the opening 312 is thinner than the sides of the opening 312, and the etchant has a high selection of the polymer layer 314 and the dielectric layers 302 and 304. 7 papers Standards are applicable to Chinese National Standard (CNS) A4 (210X297 mm). Printed by Beige Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs and printed by 3950twf.doc / 006 A7 B7. 5. Description of the invention (() ratio, that is, the etching of the polymer layer 314 The rate is much lower than the dielectric layer 304. Therefore, after the very thin polymer layer 314 in the center of the opening 312 is removed, the dielectric layer 304 and the dielectric layer 304 exposed by the polymer layer 314 will continue to be removed by etching. A node contact window opening 316 is formed. Because the polymer layers 314 on both sides of the opening 312 are thick, they cannot be completely removed during the etching process, and still cover the dielectric layer 304. The dielectric layer 304 under the polymer layer 314 on both sides of the opening 312 is protected from being etched. The extremely thin polymer layer 314 in the center of the opening after etching can be easily etched to the dielectric layer 302 until the substrate 300 is exposed, forming a node contact window opening 316 smaller than the opening 312. . Then, in the node contact window opening 316, a capacitor structure (not shown) is formed, which includes a lower electrode (not shown), a dielectric layer (not shown) and an upper electrode (not shown), wherein the lower electrode contacts through the node The window opening 316 is electrically connected to one of the source / drain regions (not shown) in the substrate. Thus, the dynamic random access memory structure of the present invention is completed. The material of the lower electrode may be doped polycrystalline silicon. The material of the dielectric layer is, for example, silicon oxide, a nitrided sand layer / silicon oxide layer (NO) structure, a silicon oxide layer / nitride layer / silicon oxide layer (0N0) structure. Or molybdenum pentoxide (Ta205), Pb (Zr, Ti) Ch, that is, PZT and (Ba, Sr) Ti03, that is, high dielectric constant materials such as BST. The material of the upper electrode is, for example, doped polycrystalline silicon, and the formation method is, for example, a chemical vapor deposition method, in which impurities are deposited while the polycrystalline silicon layer is deposited. To sum up, the present invention is characterized by: 1. In the present invention, no special mechanical equipment is needed, so the disadvantages of the method for manufacturing the contact window opening of a node that is known for photoresistive thermal reflow can be solved. 8 — -—-. —--1 丨 · 丨 丨 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) Order 3950twf.doc / 006 3950twf.doc / 006 A7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ---------------- B7 V. Description of the Invention (?) Ⅰ. In the present invention, it is not necessary to form more than two layers Polycrystalline silicon layer, and performing more than two etching steps, so that the conventional polycrystalline silicon spacer wall node contact window opening process method is too expensive and so on. 3. The etchant used in the present invention, the principle that the polymer will form a polymer after collision with the molecule, which simplifies the process and reduces the manufacturing cost. A 4. The etchant used in the present invention will When a local molecule is formed to overwhelm the dielectric layer, when the dielectric layer is etched to form a node contact window opening, the formation can be controlled by the proportion of each component in the etchant during the f-etch process, and the amount of accumulated polymer can be controlled The size of the opening of the contact window of the node. 5. The depth of the opening formed by the method of the present invention is controlled by the proportion of the etchant and is not affected by the etching time. 6. The process of the present invention and the existing The manufacturing process is compatible, which is very suitable for the manufacturer's production arrangement. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention to "any person skilled in the art" without departing from the spirit and scope of the present invention. When various changes and retouching can be made ', the scope of protection of the present invention shall be determined by the scope of the attached patent application. 9 This paper is suitable for Zhongguanjia (cns) 槻 槻 ^ (nox π7 公 瘦 5- - ------------ II (Please read the notes on the back before filling this page) .T-1TJ ----- ® ------------- ---

Claims (1)

經濟部中央標隼局員工消費合咋tfc印裝 A8 B8 3950twf.d〇c/006 C8 D8 7T、申請專利範圍 1. 一種節點接觸窗開口的製造方法’其適用於—基 底，且該基底上已形成有一介電層’包括： 進行一第一蝕刻步驟，以於該介電層中大約形成一開 口，且於該開口的側壁形成一高分子層；以及 進行第二蝕刻步驟’以該開口側壁之該高分子層爲罩 幕，繼續蝕刻部份該開口下的該介電層，直到裸露出該基 底，以形成該節點接觸窗開口。 2. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法，其中該第一蝕刻步驟的鈾刻劑包括 C4Fs/Ar/CH2F2。 3. 如申請專利範圍第2項所述之節點接觸窗開口的 製造方法，該蝕刻劑在蝕刻過程中或在該開口的側壁形成 高分子層。 4. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法，其中該第一蝕刻步驟的蝕刻劑包括可在蝕刻過 程中形成高分子的蝕刻劑。 5. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法’其中在第二触刻步驟中》該局分子層與該介電 層具有不同之蝕刻率。 6. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法，其中該第二蝕刻步驟包括乾式蝕刻法。 7. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法，其中該第二蝕刻步驟的蝕刻劑包括CHh/CO。 8. 如申請專利範圍第丨項所述之節點接觸窗開口的 10 本紙張纽適用中國國家標準（CNS ) ( 210X297公釐) ~ — (請先閱讀背面之注意事項再填寫本頁) C 裝_ 訂 線 3950twf.doc/006 C8 D8 六、申請專利範圍 製造方法，其中該第二蝕刻步驟的蝕刻劑包括對該高分子 層與該介電層具有高選擇比的蝕刻劑。 9. 如申請專利範圍第1項所述之節點接觸窗開口的 製造方法，其中更包括在該節點接觸窗開口中，形成一電 容結構。 10. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該電容包括一下電極，一介電層與一上電 極，該下電極透過該儲存節點開口而與該基底中之一源極 /汲極區作電性連接，該介電層介於該下電極與該上電極 之間。 11. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該下電極之材質包括摻雜複晶矽。 12. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該介電層之材質包括氧化矽。 13. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該介電層之材質包括氮化矽層/氧化矽層 結構。 經濟部中央標準局員工消費合阼；ϋίρ裂 (請先閱讀背面之注意事項再填寫本頁) 14. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該介電層之材質包括氧化矽層/氮化矽層/ 氧化矽層結構。 15. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該介電層之材質包括五氧化二鉅。 16. 如申請專利範圍第9項所述之節點接觸窗開口的 製造方法，其中該上電極之材質包括摻雜複晶矽。. 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Consumption of employees of the Central Bureau of Standards of the Ministry of Economic Affairs tfc printed A8 B8 3950twf.doc / 006 C8 D8 7T, patent application scope 1. A method of manufacturing a node contact window opening 'it is applicable to-substrate, and on the substrate A dielectric layer has been formed, including: performing a first etching step to form an opening in the dielectric layer, and forming a polymer layer on a side wall of the opening; and performing a second etching step to use the opening The polymer layer on the side wall is a mask, and the dielectric layer under the opening is etched partly until the substrate is exposed to form the node contact window opening. 2. The method for manufacturing a node contact window opening as described in item 1 of the scope of patent application, wherein the uranium etchant in the first etching step includes C4Fs / Ar / CH2F2. 3. According to the method for manufacturing a node contact window opening as described in item 2 of the patent application scope, the etchant forms a polymer layer during the etching process or on the sidewall of the opening. 4. The method for manufacturing a node contact window opening according to item 1 of the scope of patent application, wherein the etchant in the first etching step includes an etchant that can form a polymer during the etching process. 5. The method for manufacturing a node contact window opening according to item 1 of the scope of patent application ', wherein in the second contacting step, the molecular layer of the bureau and the dielectric layer have different etch rates. 6. The method for manufacturing a node contact window opening according to item 1 of the patent application scope, wherein the second etching step includes a dry etching method. 7. The method for manufacturing a node contact window opening according to item 1 of the scope of patent application, wherein the etchant in the second etching step includes CHh / CO. 8. As for the 10 papers of the node contact window openings described in Item 丨 of the scope of the patent application, the Chinese National Standard (CNS) (210X297mm) ~ ~ (Please read the precautions on the back before filling this page) C Pack _ Ordering line 3950twf.doc / 006 C8 D8 6. The manufacturing method of the patent application range, wherein the etchant in the second etching step includes an etchant having a high selectivity ratio between the polymer layer and the dielectric layer. 9. The method for manufacturing a node contact window opening according to item 1 of the scope of patent application, further comprising forming a capacitor structure in the node contact window opening. 10. The method for manufacturing a node contact window opening as described in item 9 of the scope of patent application, wherein the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, and the lower electrode passes through the storage node opening and communicates with the substrate. A source / drain region is electrically connected, and the dielectric layer is interposed between the lower electrode and the upper electrode. 11. The method for manufacturing a node contact window opening as described in item 9 of the scope of patent application, wherein the material of the lower electrode includes doped polycrystalline silicon. 12. The method for manufacturing a node contact window opening as described in item 9 of the scope of patent application, wherein the material of the dielectric layer includes silicon oxide. 13. The method for manufacturing a node contact window opening as described in item 9 of the scope of patent application, wherein the material of the dielectric layer includes a silicon nitride layer / silicon oxide layer structure. Consumption of employees of the Central Standards Bureau of the Ministry of Economic Affairs; cracks (please read the precautions on the back before filling out this page) 14. The manufacturing method of the contact window opening of a node as described in item 9 of the patent application scope, in which the dielectric layer The material includes a silicon oxide layer / silicon nitride layer / silicon oxide layer structure. 15. The method for manufacturing a node contact window opening according to item 9 of the scope of patent application, wherein the material of the dielectric layer includes pentoxide. 16. The method for manufacturing a node contact window opening as described in item 9 of the scope of patent application, wherein the material of the upper electrode includes doped polycrystalline silicon. . This paper size applies to China National Standard (CNS) A4 (210X297mm)
TW087120802A 1998-12-15 1998-12-15 The manufacture method of node contact TW400617B (en)

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KR100272510B1 (en) * 1997-12-30 2000-12-01 김영환 Method for forming contact hole
KR100727834B1 (en) * 2000-09-07 2007-06-14 다이킨 고교 가부시키가이샤 Dry etching gas and method for dry etching
US7560385B2 (en) * 2001-10-17 2009-07-14 Texas Instruments Incorporated Etching systems and processing gas specie modulation
US6716766B2 (en) * 2002-08-22 2004-04-06 Micron Technology, Inc. Process variation resistant self aligned contact etch
US7795152B2 (en) * 2006-05-10 2010-09-14 Micron Technology, Inc. Methods of making self-aligned nano-structures
US11594420B1 (en) * 2021-08-30 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof

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US5369048A (en) * 1993-08-26 1994-11-29 United Microelectronics Corporation Stack capacitor DRAM cell with buried bit-line and method of manufacture
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