2 7 56twfl .doc / 002 第87105613號說明浴修 A7 B7 修正曰期2 7 56twfl .doc / 002 No. 87105613 Description Bath repair A7 B7 Revised date
經濟部智慧財產局員工消费合作社印製 五、發明說明（1) 質。然後利用微影融刻技術定義此層多晶砂物質，以形成 多晶砂層116。 接著例如使用低壓化學氣相沉積法沉積一層內多晶矽 介電物質（Inter-poly Dielectric layer)，覆蓋多晶砂層 116。 然後，使用低壓化學氣相沉積法在此內多晶矽介電物質上 形成另一層多晶矽物質。接著’利用微影蝕刻技術定義此 層多晶矽物質並往下蝕刻內多晶矽介電物質，藉以形成多 晶矽層120與內多晶矽介電層118。其中，週邊電路區的 元件區上同時也形成有多晶矽層120。 然後，例如使用低壓化學氣相沉積法，沉積一層氧化 物質覆蓋整個半導體基底結構表面。接著，使用回蝕刻方 式，藉以使得此層氧化物質在NM0S元件區107與PM0S 元件區108之多晶矽層120的側壁上形成間隙壁128。同 時，此回蝕刻步驟也會在記憶區109中多晶矽層120、介 電層1 18與多晶矽層116之側壁上形成間隙壁128。 請參照第2B圖，利用微影蝕刻技術並且以多晶矽層 120爲罩幕，進行蝕刻步驟，進一步定義多晶矽層116。 其中，多晶矽層1 16作爲浮置閘，而多晶矽層120作爲控 制閘，即字元線。接著，以另一罩幕覆蓋記憶胞區109與 PMOS元件區108，並進行傳統的N型離子植入步驟，藉 以在NMOS元件區107的基底中形成濃度較淡的N型離 子佈植區124，接著移除此罩幕。然後，以另一罩幕覆蓋 記憶胞區109與NMOS元件區107，並進行傳統的P型離 子植入步驟，並在PMOS元件區108的基底中形成濃度較 淡的P型離子佈植區126，接著移除此罩幕。其中，此傳 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — I — — In — — — — — /1 - — — 111 — — ^ ·1111111« ^ ► (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印装 2756twf.doc/006 A7 B7_ 五、發明説明（/) 本發明是有關於一種記憶體，且特別是有關於一種一 次可程式唯讀記憶體（One Time Programmable Read Only Memory ; OTP-ROM)。 當電腦微處理器(Microprocessor)的功能越來越強，軟 體所進行的程式與運算越來越龐大時，記憶體的需求也就 越來越高。因此，如何製造容量大且便宜的記憶體以滿足 這種需求，便成了半導體製造商的一大課題。依據讀/寫 功能的差異，記憶體可以簡單的區分爲兩類：唯讀記憶體 (Read Only Memory ; ROM)與隨機存取記憶體。其中，唯 讀記憶體是只能做“讀”的動作，而隨機存取記憶體則具備 了“讀”與“寫”的雙重功能。依照資料存入的方式，唯讀記 憶體一般可以細分爲罩幕式唯讀記憶體(Mask ROM)、可 程式唯讀記憶體(Programmable ROM ; PROM)、可抹除可 程式唯讀記憶體(Erasable Programmable ROM ; EPROM)、 電子式可抹除可程式唯讀記憶體（Electrically Erasable Programmable ROM ; EEPROM)等’而隨機存取記憶體則 依照資料在記憶體內的處理方式可以細分爲靜態隨機存取 記憶體與動態隨機存取記憶體(Dynamic RAM ; DRAM)兩 種。 唯讀gB憶體已廣泛應用於迷你電腦，微處理器系統等 一類的數位設備中，其可用來儲存一些系統資料，例如 BIOS等常駐程式。由於唯讀記憶體（簡稱R〇M)的製程非 常複雜，而且需要很多耗費時間的步驟及材料的處理，因 此，客戶通常是先將程式資料交給記憶體製造工廠，再由 --------—裝------訂-----^0 (.請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 2756twf. doc/006 八7 _____B7____ 五、發明説明（x) 工廠將其編碼在唯讀記億體中以製成成品。 大部分的唯讀記憶體元件除了在程式化階段所存入的 資料不同之外，其餘的結構均相同，因此，唯讀記憶體可 先製作到程式化之前的步驟，並將此未程式化的半成品庫 存起來，待客戶送來特定程式的訂單之後，即可迅速製作 光罩以進行程式化，再出貨給客戶，故上述的後程式化光 罩式唯讀記憶體已成爲業界慣用的方法。 一般常用的唯讀記憶體係利用通道電晶體當作記憶單 元(Memory Cell)，並於程式化階段，選擇性地植入雜質到 指定通道區，以藉改變起始電壓（Threshold Voltage)而達 到控制記憶單元導通（ON)或關閉（OFF)的目的。其中唯讀 記憶體的結構部份，多晶矽字元線WL(Word Line)跨過位 元線BL(Bit Line)，記憶單元的通道則形成於字元線WL 所覆蓋的下方，及位元線BL之間的區域。而唯讀記憶體 即以通道的離子植入與否，來儲存二階式位元數據>0"， 免1夕〇 第ΙΑ、1B與1C圖係繪示習知可程式唯讀記憶體之製 造流程剖面圖。其中，第1B與1C圖係具有相同的剖面方 向，且都與第1A圖之剖面方向呈垂直。 請同時參照第1A圖，首先，提供一基底1〇，此基底 10上已界定出記憶胞區9與週邊電路區’此週邊電路區中 包括NMOS元件區7與PMOS元件區8。其中，PMOS元 件區8之基底10中已形成有N型井區11。接著使用熱氧 化法在此基底10上形成一墊氧化層(未顯示）。然後例如使 4 (請先閲讀背面之注意事1再填寫本頁) •裝. 'tr i丨線. 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） 2756twf.doc/006 A7 B7 五、發明説明（彡） 用區域氧化法在基底10上形成場氧化層14(Field Oxide Layer)以定義出元件區(Active Area)。然後，例如使用濕 蝕刻法淸除墊氧化層。接著，使用熱氧化法，使元件區的 表面形成一層氧化層12。然後例如使用低壓化學氣相沉積 法在此氧化層12上形成一層多晶砂物質。然後利用微影 蝕刻技術定義此層多晶矽物質，以形成多晶砂層16。 接著例如使用低壓化學氣相沉積法沉積一層內多晶0 介電物質（Inter-poly Dielectric Layer)，覆蓋多晶砂層μ。 然後，使用低壓化學氣相沉積法在此內多晶矽介電物質上 形成另一層多晶矽物質。接著，利用微影蝕刻技術定義止匕 層多晶矽物質並往下蝕刻內多晶矽介電物質，藉以形成& 晶矽層20與內多晶矽介電層18。其中，週邊電路區的元 件區上同時也形成有多晶矽層20。 請參照第1B圖，利用微影蝕刻技術並且以多晶矽靥2〇 爲罩幕，進行蝕刻步驟，進一步定義多晶矽層16。然後， 以一罩幕覆蓋週邊電路區，且暴露出記憶胞區9。接奢， 同樣以多晶矽層20爲罩幕進行N型離子植入步驟，自行 對準多晶矽層並植入濃度較濃的離子，以形成離子佈値遲 22。接著，以另一罩幕覆蓋記憶胞區9與PM0S元件區8， 並進行傳統的N型離子植入步驟，藉以在NM0S元件區7 的基底中形成濃度較淡的N型離子佈植區24，接著移除 此罩幕。然後，以另一罩幕覆蓋記憶胞區9與NM0S元件 區7，並進行傳統的P型離子植入步驟，並在PMOS元件 區8的基底中形成濃度較淡的P型離子佈植區26，接著移 5 本紙張尺度適用中國困家標準（CNS ) A4祝格（210X297公嫠） I I I I I I 訂 I )線 (，請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作杜印製 2756twf.d〇c/006 A7 B7 經濟部中央標準局貝工消費合作社印繁 五、發明说明（子） .除此罩幕。 請參照第1C圖，例如使用低壓化學氣相沉積法，沉 積一層氧化物質覆蓋整個半導體基底結構表面。接著，使 用回蝕刻方式，藉以使得此層氧化物質在NMOS元件區7 與PMOS元件區8之多晶矽層20的側壁上形成間隙壁28 ^ 同時，此回蝕刻步驟也會在記憶區9中多晶矽層20、介電 層18與多晶矽層16之側壁上形成間隙壁28。 然後，以一罩幕覆蓋NMOS元件區7，進行傳統的離 子植入步驟，在PMOS元件區8的基底中形成濃度較濃的 P型離子佈植區30，接著移除此罩幕。以另一罩幕覆蓋 PMOS元件區8，並進行離子植入步驟，藉以在NMOS元 件區7的基底中形成濃度較濃的N型離子佈植區32。此 離子植入步驟同時也會在記憶胞區9的基底中形成濃度較 濃的N型離子佈植區34。 接著，進行後續的步驟以完成可程式唯讀存取記憶體 之製造。此後續製程爲熟習此技藝者所能輕易達成，故此 處不在贅述。 此習知可程式唯讀記憶體，因爲具有間隙壁結構28， 因此會降低編程的效率。而形成濃度較濃的N型離子佈植 區34雖然可以補救一部份，但是卻使得製程變得更爲複 雜。再者，因爲間隙壁會形成於記憶胞區中，因此無可避、 免地需要進行回蝕刻步驟，所以此回蝕刻步驟會造成記憶 胞區中複晶表面及場氧化層受損，而導致遺漏電流。 因此本發明的主要目的就是在提供一種一次可程式唯 6 本紙張尺度適用中國囷家梂準（CNS ) Α4規格（2丨0X297公羞） n HI —.1 1 —I---1 - - - 1 - (_請先閲讀背面之注f項再填寫本頁) ,ιτ 丨線 756twf- doc/006 A7 B7 經濟部中央梂準局負工消費合作社印犁 五、發明説明（彡） .讀存取記憶體，用以改善習知可程式唯讀記憶體之缺點。 根據本發明的目的，提出一種一次可程式唯讀存取記 憶體，包括一由下往上堆疊之浮置閘、介電層、與控制閘 位在基底上。在此記憶體結構中’浮置閘、介電層、與控 制閘之側壁不具有間隙壁。並且’―離子佈植區位於浮置 閘兩側下方之基底中。 本發明之一次可程式唯讀存取記憶體結構中，間隙壁 只位於週邊電路區中多晶矽層之側壁，而不會位於記憶胞 區中，因此可增加編程的效率。 本發明之一次可程式唯讀記億體結構可簡化製程，並 且因爲間隙壁不介入記憶胞區中，所以不需要額外植入濃 度較濃的離子，以彌補間隙壁所降低的編程效率。 此外，因爲間隙壁係在定義多晶矽層以形成浮置閘結 構之前就已經形成。所以可以避免在形成間隙壁所需之回 蝕刻步驟中，損害場氧化層，因此可以避免產生遺漏電流。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下·· 圖式之簡單說明： 第1A圖至第1C圖係繪示習知可程式唯讀記憶體之製 造流程剖面圖；以及 第2A圖至第2C圖係繪示依照本發明一較佳實施例的 一種一次可程式唯讀存取記憶體之製造流程剖面圖。 圖示標記說明： 7 -- I I— I t - I— I I I- - I ('請先閲讀背面之注意事項再填寫本頁) 订 線 本紙張尺度連用中國國家棣準（CNS ) A4規格（210X297公漦） 經濟部中央標準局負工消費合作社印聚 2756twf.doc/006 八7 _________B7_ 五、發明説明（6) 10、 110 :基底 11、 111 :井區 12、 112 :閘極氧化層 14、114 :場氧化層 16、20、116、120 :多晶砂層 28、128 :間隙壁 22、24、26、30、32、34、122、124、126、132、134 : 離子佈植區 18、118 :介電層 實施例 第2A至2C圖係繪示依照本發明一較佳實施例的一種 一次可程式唯讀存取記憶體之製造流程剖面圖。其中，第 2B與2C圖係具有相同的剖面方向，且都與第2A圖之剖 面方向呈垂直。 請同時參照第2A圖，首先，提供一基底110，此基底 110上已界定出記憶胞區109與週邊電路區，此週邊電路 區中包括NMOS元件區107與PMOS元件區108。其中， PMOS元件區108之基底110中已形成有N型井區111。 接著使用熱氧化法在此基底110上形成一墊氧化層(未顯 示）。然後例如使用區域氧化法在基底Π0上形成場氧化 層 14(Field Oxide Layer)以定義出元件區(Active Area)。然 後，例如使用濕蝕刻法淸除墊氧化層。接著’使用熱氧化 法，使元件區的表面形成一層氧化層112。然後例如使用 低壓化學氣相沉積法在此氧化層Π2上形成一層多晶矽物 (請先閲讀背面之注f項再填寫本頁) ：--------------------1^------1T----------------------- 2 7 56twfl .doc / 002 第87105613號說明浴修 A7 B7 修正曰期Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Quality. The lithographic melting technique is then used to define this layer of polycrystalline sand material to form a polycrystalline sand layer 116. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inter-poly silicon dielectric layer, covering the polycrystalline sand layer 116. Then, another layer of polycrystalline silicon material is formed on the polycrystalline silicon dielectric material by using a low pressure chemical vapor deposition method. Next, lithographic etching technology is used to define this layer of polycrystalline silicon material and then etch the inner polycrystalline silicon dielectric material down to form the polycrystalline silicon layer 120 and the inner polycrystalline silicon dielectric layer 118. The polycrystalline silicon layer 120 is also formed on the element region of the peripheral circuit region. Then, for example, a low pressure chemical vapor deposition method is used to deposit a layer of oxide material to cover the entire surface of the semiconductor substrate structure. Next, an etch-back method is used so that this layer of oxide material forms a partition wall 128 on the sidewalls of the polycrystalline silicon layer 120 of the NMOS device region 107 and the PMOS device region 108. At the same time, this etch-back step also forms a spacer 128 on the sidewalls of the polycrystalline silicon layer 120, the dielectric layer 118, and the polycrystalline silicon layer 116 in the memory area 109. Referring to FIG. 2B, the polysilicon layer 116 is further defined by using the lithography etching technique and using the polysilicon layer 120 as a mask to perform an etching step. Among them, the polycrystalline silicon layer 116 serves as a floating gate, and the polycrystalline silicon layer 120 serves as a control gate, that is, a word line. Next, another memory screen is used to cover the memory cell region 109 and the PMOS device region 108, and a conventional N-type ion implantation step is performed to form a lighter N-type ion implantation region 124 in the substrate of the NMOS device region 107. , Then remove this mask. Then, another memory screen is used to cover the memory cell region 109 and the NMOS element region 107, and a conventional P-type ion implantation step is performed, and a lighter-type P-type ion implantation region 126 is formed in the substrate of the PMOS element region 108 , Then remove this mask. Among them, 9 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) — I — — In — — — — — / 1-— — 111 — — ^ · 1111111 «^ ► (Please (Please read the notes on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 2756twf.doc / 006 A7 B7_ V. Description of the Invention (/) The present invention relates to a memory, and in particular to A type of One Time Programmable Read Only Memory (OTP-ROM). As the functions of computer microprocessors become more and more powerful, and the programs and calculations performed by software become more and more massive, the demand for memory will also increase. Therefore, how to make large-capacity and cheap memory to meet this demand has become a major issue for semiconductor manufacturers. According to the difference of read / write function, the memory can be simply divided into two types: Read Only Memory (ROM) and Random Access Memory. Among them, the read-only memory can only perform the action of “read”, while the random access memory has the dual functions of “read” and “write”. According to the method of data storage, the read-only memory can generally be subdivided into Mask ROM, Programmable ROM (PROM), and Programmable ROM (Erasable) Erasable Programmable ROM (EPROM), Electronic Erasable Programmable ROM (EEPROM), etc. 'and random access memory can be subdivided into static random access according to how data is processed in the memory Memory and dynamic random access memory (Dynamic RAM; DRAM). The read-only gB memory has been widely used in digital devices such as mini computers, microprocessor systems, etc. It can be used to store some system data, such as resident programs such as BIOS. Because the manufacturing process of read-only memory (referred to as ROM) is very complicated, and requires many time-consuming steps and material processing, customers usually first give program data to the memory manufacturing factory, and then ---- ----— Installation ------ Order ----- ^ 0 (. Please read the notes on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 2756twf. Doc / 006 8 7 _____B7____ V. Description of the invention (x) The factory encodes it in a read-only memory to make a finished product. Most of the read-only memory components have the same structure except for the data stored in the programming phase. Therefore, the read-only memory can be made to the steps before programming, and this is not programmed. After the semi-finished products are in stock, after the customer sends an order of a specific program, the photomask can be quickly made for programming, and then shipped to the customer. Therefore, the above-mentioned post-programmed photomask-based read-only memory has become the industry's usual method. The commonly used read-only memory system uses the channel transistor as a memory cell, and in the programming stage, selectively implants impurities into the designated channel area to achieve control by changing the threshold voltage. The purpose of the memory unit being ON (ON) or OFF (OFF). Among the structural parts of the read-only memory, the polysilicon word line WL (Word Line) crosses the bit line BL (Bit Line), and the channel of the memory cell is formed below the word line WL and the bit line The area between BL. The read-only memory uses the channel's ion implantation or not to store the second-order bit data > 0 ", so that the 1st, 1B, and 1C diagrams show the conventional programmable read-only memory. Manufacturing process section. Among them, Figs. 1B and 1C have the same cross-sectional direction, and both are perpendicular to the cross-sectional direction of Fig. 1A. Referring to FIG. 1A at the same time, first, a substrate 10 is provided. A memory cell region 9 and a peripheral circuit region have been defined on the substrate 10. The peripheral circuit region includes an NMOS element region 7 and a PMOS element region 8. Among them, an N-type well region 11 has been formed in the substrate 10 of the PMOS element region 8. A thermal oxidation method is then used to form a pad oxide layer (not shown) on the substrate 10. Then for example make 4 (please read the note 1 on the back before filling in this page) • Install. 'Tr i 丨 line. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 2756twf.doc / 006 A7 B7 V. Description of the Invention (ii) A field oxide layer 14 (Field Oxide Layer) is formed on the substrate 10 by an area oxidation method to define an active area. Then, the pad oxide layer is removed using, for example, a wet etching method. Next, an oxide layer 12 is formed on the surface of the element region by a thermal oxidation method. A layer of polycrystalline sand material is then formed on this oxide layer 12 using, for example, a low pressure chemical vapor deposition method. Lithographic etching technology is then used to define this layer of polycrystalline silicon material to form a polycrystalline sand layer 16. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inter-poly-dielectric layer (Inter-poly Dielectric Layer) to cover the polycrystalline sand layer μ. Then, another layer of polycrystalline silicon material is formed on the polycrystalline silicon dielectric material by using a low pressure chemical vapor deposition method. Next, the lithography etching technology is used to define the polycrystalline silicon material of the stopper layer and the inner polycrystalline silicon dielectric material is etched downward to form the & crystalline silicon layer 20 and the inner polycrystalline silicon dielectric layer 18. The polycrystalline silicon layer 20 is also formed on the element area of the peripheral circuit area. Referring to FIG. 1B, the polysilicon layer 16 is further defined by performing an etching step using a lithographic etching technique and using polycrystalline silicon 20 as a mask. Then, the peripheral circuit area is covered with a curtain, and the memory cell area 9 is exposed. Next, the N-type ion implantation step is also performed using the polycrystalline silicon layer 20 as a mask, and the polycrystalline silicon layer is self-aligned and implanted with a higher concentration of ions to form an ion cloth. Then, another memory screen is used to cover the memory cell region 9 and the PMOS element region 8 and a conventional N-type ion implantation step is performed to form a lighter N-type ion implantation region 24 in the substrate of the NMOS element region 7 , Then remove this mask. Then, another memory curtain is used to cover the memory cell region 9 and the NMOS element region 7, and a conventional P-type ion implantation step is performed, and a lighter-type P-type ion implantation region 26 is formed in the substrate of the PMOS element region 8. , And then shift 5 paper standards to apply Chinese Standards for Households (CNS) A4 Zhuge (210X297 Gong) IIIIII Order I) line (Please read the precautions on the back before filling this page) Staff consumption of the Central Bureau of Probationary Affairs of the Ministry of Economic Affairs Cooperative Du Printing 2756twf.doc / 006 A7 B7 Yin Fan, Cooperative Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, 5. Description of Invention (Sub). Please refer to FIG. 1C. For example, a low pressure chemical vapor deposition method is used to deposit an oxide layer to cover the entire surface of the semiconductor substrate structure. Next, an etch-back method is used so that this layer of oxide material forms a spacer 28 on the sidewalls of the polycrystalline silicon layer 20 in the NMOS device region 7 and the PMOS device region 8 ^ At the same time, this etch-back step also forms a polycrystalline silicon layer in the memory region 9 20. A spacer 28 is formed on a sidewall of the dielectric layer 18 and the polycrystalline silicon layer 16. Then, the NMOS element region 7 is covered with a mask, and a conventional ion implantation step is performed to form a P-type ion implantation region 30 with a higher concentration in the substrate of the PMOS element region 8. Then, the mask is removed. The PMOS device region 8 is covered with another mask, and an ion implantation step is performed to form a N-type ion implantation region 32 with a higher concentration in the substrate of the NMOS device region 7. This ion implantation step also forms a N-type ion implantation region 34 with a higher concentration in the base of the memory cell region 9. Then, the subsequent steps are performed to complete the manufacture of the programmable read-only memory. This follow-up process can be easily achieved by those skilled in this art, so I will not go into details here. The conventional programmable read-only memory has a partition wall structure 28, which reduces programming efficiency. Although the formation of the N-type ion implantation region 34 with a higher concentration can remedy a part of the process, the process becomes more complicated. In addition, because the gap wall will be formed in the memory cell area, an etch-back step is unavoidable and inevitable, so this etch-back step will cause damage to the polycrystalline surface and field oxide layer in the memory cell area, resulting in Missing current. Therefore, the main purpose of the present invention is to provide a program that can be programmed only once. The paper size is applicable to the Chinese family standard (CNS) A4 specification (2 丨 0X297). N HI —.1 1 —I --- 1-- -1-(_Please read the note f on the back before filling in this page), ιτ 丨 line 756twf-doc / 006 A7 B7 Yinli, the Consumer Work Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (彡). Read Memory access to improve the shortcomings of conventional programmable read-only memory. According to the purpose of the present invention, a single-programmable read-only access memory is provided, which includes a floating gate, a dielectric layer, and a control gate stacked on the substrate from bottom to top. In this memory structure, the sidewalls of the 'floating gate, dielectric layer, and control gate do not have a gap wall. And the ―-ion implantation area is located in the base below both sides of the floating gate. In the programmable read-only access memory structure of the present invention, the gap wall is only located on the side wall of the polycrystalline silicon layer in the peripheral circuit area, and is not located in the memory cell area, so the programming efficiency can be increased. The one-time programmable read-only memory structure of the present invention can simplify the manufacturing process, and because the gap wall does not intervene in the memory cell area, it is not necessary to implant more concentrated ions to compensate for the reduced programming efficiency of the gap wall. In addition, because the bulkhead is formed before the polysilicon layer is defined to form a floating gate structure. Therefore, the field oxide layer can be prevented from being damaged during the etch-back step required to form the spacer, and thus a leakage current can be avoided. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: · Brief description of the drawings: Figure 1A to FIG. 1C is a cross-sectional view showing a manufacturing process of a conventional programmable read-only memory; and FIGS. 2A to 2C are drawings showing a one-time programmable read-only memory according to a preferred embodiment of the present invention Manufacturing process cross-section. Explanation of icon marks: 7-II— I t-I— II I--I ('Please read the precautions on the back before filling this page) Alignment This paper size is in accordance with China National Standard (CNS) A4 specification ( 210X297 public money) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 2756twf.doc / 006 8 7 _________B7_ V. Description of the invention (6) 10, 110: substrate 11, 111: well area 12, 112: gate oxide layer 14 , 114: field oxide layers 16, 20, 116, 120: polycrystalline sand layers 28, 128: spacers 22, 24, 26, 30, 32, 34, 122, 124, 126, 132, 134: ion implantation area 18 , 118: Dielectric layer embodiments 2A to 2C are cross-sectional views showing a manufacturing process of a one-time programmable read-only access memory according to a preferred embodiment of the present invention. 2B and 2C have the same cross-sectional direction, and both are perpendicular to the cross-sectional direction of FIG. 2A. Referring to FIG. 2A at the same time, first, a substrate 110 is provided. A memory cell region 109 and a peripheral circuit region have been defined on the substrate 110. The peripheral circuit region includes an NMOS device region 107 and a PMOS device region 108. Among them, an N-type well region 111 has been formed in the substrate 110 of the PMOS device region 108. A thermal oxidation method is then used to form a pad oxide layer (not shown) on the substrate 110. Then, for example, a field oxide method is used to form a field oxide layer 14 on the substrate UI0 to define an active area. Then, the pad oxide layer is removed using, for example, a wet etching method. Next, a thermal oxidation method is used to form an oxide layer 112 on the surface of the element region. Then, for example, a low-pressure chemical vapor deposition method is used to form a layer of polycrystalline silicon on the oxide layer Π2 (please read the note f on the back before filling this page): --------------- ---- 1 ^ ------ 1T ----------------------- 2 7 56twfl .doc / 002 No. 87105613 Description Bath Repair A7 B7 modified date
經濟部智慧財產局員工消费合作社印製 五、發明說明（1) 質。然後利用微影融刻技術定義此層多晶砂物質，以形成 多晶砂層116。 接著例如使用低壓化學氣相沉積法沉積一層內多晶矽 介電物質（Inter-poly Dielectric layer)，覆蓋多晶砂層 116。 然後，使用低壓化學氣相沉積法在此內多晶矽介電物質上 形成另一層多晶矽物質。接著’利用微影蝕刻技術定義此 層多晶矽物質並往下蝕刻內多晶矽介電物質，藉以形成多 晶矽層120與內多晶矽介電層118。其中，週邊電路區的 元件區上同時也形成有多晶矽層120。 然後，例如使用低壓化學氣相沉積法，沉積一層氧化 物質覆蓋整個半導體基底結構表面。接著，使用回蝕刻方 式，藉以使得此層氧化物質在NM0S元件區107與PM0S 元件區108之多晶矽層120的側壁上形成間隙壁128。同 時，此回蝕刻步驟也會在記憶區109中多晶矽層120、介 電層1 18與多晶矽層116之側壁上形成間隙壁128。 請參照第2B圖，利用微影蝕刻技術並且以多晶矽層 120爲罩幕，進行蝕刻步驟，進一步定義多晶矽層116。 其中，多晶矽層1 16作爲浮置閘，而多晶矽層120作爲控 制閘，即字元線。接著，以另一罩幕覆蓋記憶胞區109與 PMOS元件區108，並進行傳統的N型離子植入步驟，藉 以在NMOS元件區107的基底中形成濃度較淡的N型離 子佈植區124，接著移除此罩幕。然後，以另一罩幕覆蓋 記憶胞區109與NMOS元件區107，並進行傳統的P型離 子植入步驟，並在PMOS元件區108的基底中形成濃度較 淡的P型離子佈植區126，接著移除此罩幕。其中，此傳 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — I — — In — — — — — /1 - — — 111 — — ^ ·1111111« ^ ► (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 S99306 2756twfl.doc/002 A7 _ B7 五、發明說明（i?) 統之P型或N型離子植入步驟，包括使用些微傾斜之離子 植入角度。 請參照第2C圖，然後，以一罩幕覆蓋NMOS元件區 1〇7，進行傳統的離子植入步驟，在PMOS元件區108的 基底中形成濃度較濃的P型離子佈植區130，接著移除此 罩幕。以另一罩幕覆蓋PMOS元件區108，並進行離子植 入步驟，藉以在NMOS元件區107與記億元件區109的基 底中形成濃度較濃的N型離子佈植區132與122。 接著，進行後續的步驟以完成一次可程式唯讀存取記 億體之製造。此後續製程爲熟習此技藝者所能輕易達成， 故此處不在贅述。 本發明之一次可程式唯讀存取記憶體結構中，間隙壁 只位於週邊電路區中多晶矽層120之側壁，而不會位於記 憶胞區中，因此可增加編程的效率。 並且本發明可簡化製程，因爲間隙壁不介入記憶胞區 中，所以不需要額外植入濃度較濃的N型離子，以彌補間 隙壁所降低的編程效率。 此外，因爲間隙壁128係在定義多晶砂層116以形成 浮置閘結構之前就已經形成。所以可以避免在形成間隙壁 128所需之回蝕刻步驟中，損害場氧化層114，因此可以 避免產生遺漏電流。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 10 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） (請先閲讀背面之注意事項再填寫本頁) 裝 !| 訂---------Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Quality. The lithographic melting technique is then used to define this layer of polycrystalline sand material to form a polycrystalline sand layer 116. Then, for example, a low-pressure chemical vapor deposition method is used to deposit an inter-poly silicon dielectric layer, covering the polycrystalline sand layer 116. Then, another layer of polycrystalline silicon material is formed on the polycrystalline silicon dielectric material by using a low pressure chemical vapor deposition method. Next, lithographic etching technology is used to define this layer of polycrystalline silicon material and then etch the inner polycrystalline silicon dielectric material down to form the polycrystalline silicon layer 120 and the inner polycrystalline silicon dielectric layer 118. The polycrystalline silicon layer 120 is also formed on the element region of the peripheral circuit region. Then, for example, a low pressure chemical vapor deposition method is used to deposit a layer of oxide material to cover the entire surface of the semiconductor substrate structure. Next, an etch-back method is used so that this layer of oxide material forms a partition wall 128 on the sidewalls of the polycrystalline silicon layer 120 of the NMOS device region 107 and the PMOS device region 108. At the same time, this etch-back step also forms a spacer 128 on the sidewalls of the polycrystalline silicon layer 120, the dielectric layer 118, and the polycrystalline silicon layer 116 in the memory area 109. Referring to FIG. 2B, the polysilicon layer 116 is further defined by using the lithography etching technique and using the polysilicon layer 120 as a mask to perform an etching step. Among them, the polycrystalline silicon layer 116 serves as a floating gate, and the polycrystalline silicon layer 120 serves as a control gate, that is, a word line. Next, another memory screen is used to cover the memory cell region 109 and the PMOS device region 108, and a conventional N-type ion implantation step is performed to form a lighter N-type ion implantation region 124 in the substrate of the NMOS device region 107. , Then remove this mask. Then, another memory screen is used to cover the memory cell region 109 and the NMOS element region 107, and a conventional P-type ion implantation step is performed, and a lighter-type P-type ion implantation region 126 is formed in the substrate of the PMOS element region 108. , Then remove this mask. Among them, 9 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) — I — — In — — — — — / 1-— — 111 — — ^ · 1111111 «^ ► (Please (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs S99306 2756twfl.doc / 002 A7 _ B7 V. Description of the invention (i?) General P-type or N-type ion implantation steps, Including the use of slightly inclined ion implantation angle. Referring to FIG. 2C, the NMOS device region 107 is covered with a mask, and a conventional ion implantation step is performed to form a thicker P-type ion implantation region 130 in the substrate of the PMOS device region 108. Then, Remove this mask. The PMOS device region 108 is covered with another mask, and an ion implantation step is performed to form N-type ion implantation regions 132 and 122 with a higher concentration in the substrates of the NMOS device region 107 and the memory device region 109. Then, the subsequent steps are performed to complete the manufacture of a programmable read-only memory. This subsequent process can be easily achieved by those skilled in this art, so it will not be repeated here. In the one-time programmable read-only memory structure of the present invention, the gap wall is only located on the side wall of the polycrystalline silicon layer 120 in the peripheral circuit area, and is not located in the memory cell area, so the programming efficiency can be increased. In addition, the present invention can simplify the manufacturing process, because the gap wall does not intervene in the memory cell region, so it is not necessary to additionally implant N-type ions with a higher concentration to compensate for the reduced programming efficiency of the gap wall. In addition, because the partition wall 128 was formed before the polycrystalline sand layer 116 was defined to form the floating gate structure. Therefore, it is possible to avoid damaging the field oxide layer 114 during the etch-back step required to form the spacer 128, and thus to prevent a leakage current. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 10 This paper size applies to China National Standard (CNS) A4 specification (21〇 X 297 public love) (Please read the precautions on the back before filling this page) Binding! | Order ---------