A7 B7 334 5twf.doc/005 五、發明説明（I ) 本發明是有關於一種記憶體’且特別是有關於一種一 次可程式唯讀記憶體（〇ne Time Pr〇grammable Read 〇nly Memory ; OTP-ROM)。 當電腦微處理器(Microprocessor)的功能越來越強，軟體 所進行的程式與運算越來越龐大時’記憶體的需求也就越 來越高。因此，如何製造容量大且便宜的記憶體以滿足這 種需求，便成了半導體製造商的一大課題。依據讀/寫功 能的差異，記憶體可以簡單的區分爲兩類：唯讀記憶體 (Read Only Memory ; ROM)與隨機存取記憶體。其中，唯 讀記憶體是只能做“讀”的動作，而隨機存取記憶體則具備 了“讀”與“寫”的雙重功能。依照資料存入的方式，唯讀記 憶體一般可以細分爲罩幕式唯讀記憶體(Mask ROM)、可 程式唯讀記憶體(Programmable ROM ; PROM) '可抹除可 程式唯讀記憶體(Erasable Programmable ROM ; EPROM)、 電子式可抹除可程式唯讀記憶體（Electrically Erasable Programmable ROM ; EEPROM)等，而隨機存取記憶體則 依照資料在記憶體內的處理方式可以細分爲靜態隨機存取 記憶體（Static RAM ; SRAM)與動態隨機存取記億體 (Dynamic RAM ; DRAM)兩種。 唯讀記憶體已廣泛應用於迷你電腦，微處理器系統等 一類的數位設備中’其可用來儲存一些系統資料，例如 BIOS等常駐程式。由於唯讀記憶體(簡稱R0M)的製程非 常複雜’而且需要很多耗費時間的步驟及材料的處理，因 此’客戶通常是先將程式資料交給記憶體製造工廠，再由 本紙張尺度適用中國國家標準（cns ) μ規鼇) (請先閱讀背面之注意事項再填寫本頁)A7 B7 334 5twf.doc / 005 V. Description of the Invention (I) The present invention relates to a type of memory, and in particular to a one-time programmable read-only memory (〇ne Time Pr〇grammable Read 〇nly Memory; OTP -ROM). As the capabilities of computer microprocessors become more and more powerful, and the programs and calculations performed by software become more and more huge, the demand for memory will also increase. Therefore, how to make large-capacity and cheap memory to meet this demand has become a major issue for semiconductor manufacturers. According to the difference of read / write function, memory can be simply divided into two types: Read Only Memory (ROM) and Random Access Memory. Among them, the read-only memory can only perform the action of “read”, while the random access memory has the dual functions of “read” and “write”. According to the method of data storage, the read-only memory can generally be subdivided into Mask ROM and Programmable ROM (PROM). 'Erasable Programmable Read-Only Memory (PROM) Erasable Programmable ROM (EPROM), electronic erasable programmable read-only memory (Electrically Erasable Programmable ROM; EEPROM), etc., while random access memory can be subdivided into static random access according to how data is processed in the memory Memory (Static RAM; SRAM) and dynamic random access memory (Dynamic RAM; DRAM). Read-only memory has been widely used in digital devices such as mini computers and microprocessor systems. It can be used to store some system data, such as resident programs such as BIOS. Because the process of read-only memory (referred to as ROM) is very complicated 'and requires a lot of time-consuming steps and materials processing, therefore,' customers usually first give program data to the memory manufacturing factory, and then this paper size applies Chinese national standards (Cns) μ Regulations (Please read the notes on the back before filling in this page)
'1T 經濟部中央標率局員工消费合作社印製 A7 B7 334 5twf.doc/005 五、發明説明（> ) 工廠將其編碼在唯讀記憶體中以製成成品。 大部分的唯讀記憶體元件除了在程式化階段所存入的 資料不同之外，其餘的結構均相同，因此，唯讀記憶體可 先製作到程式化之前的步驟，並將此未程式化的半成品庫 存起來，待客戶送來特定程式的訂單之後，即可迅速製作 光罩以進行程式化，再出貨給客戶，故上述的後程式化光 罩式唯讀記憶體已成爲業界慣用的方法。 —般常用的唯’讀記憶體係利用通道電晶體當作記憶單 元(memory cell)，並於程式化階段，選擇性地植入雜質到 指定通道區，以藉改變起始電壓(threshold voltage)而達到 控制記憶單元導通（ON)或關閉（OFF)的目的。其中唯讀記 憶體的結構部份，多晶矽字元線WL(Word Line)跨過位元 線BL(Bit Line)，記憶單元的通道則形成於字元線WL所 覆蓋的下方，及位元線BL之間的區域。而唯讀記憶體即 以通道的離子植入與否，來儲存二階式位元數據〜〇"， 丫 〇 第1圖係繪示習知可程式唯讀記憶體之佈局(Lay Out) 圖。第2圖係繪示從第1圖I-Ι剖面方向所得之剖面圖， 而第3圖係繪示從第1圖II-II剖面方向所得之剖面圖。此 習知可程式唯讀記憶體之製造方法則如下所述。 請同時參照第1、2與3圖，首先，提供一基底10， 接著例如使用熱氧化法在此基底10上形成一墊氧化層(未 顯示）。然後例如使用區域氧化法在基底10上形成場氧化 層 14(Field Oxide Layer)以定義出元件區(Active Area)。然 4'1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 334 5twf.doc / 005 V. Description of Invention (>) The factory encodes it in read-only memory to make a finished product. Most of the read-only memory components have the same structure except for the data stored in the programming phase. Therefore, the read-only memory can be made to the steps before programming, and this is not programmed. After the semi-finished products are in stock, after the customer sends an order of a specific program, the photomask can be quickly made for programming, and then shipped to the customer. Therefore, the above-mentioned post-programmed photomask-based read-only memory has become the industry's usual method. -The commonly used read-only memory system uses channel transistors as memory cells, and in the programming stage, selectively implants impurities into designated channel regions to change the threshold voltage and To achieve the purpose of controlling the memory unit to be turned ON or OFF. Among the structural parts of the read-only memory, the polycrystalline silicon word line WL (Word Line) crosses the bit line BL (Bit Line), and the channel of the memory cell is formed below the word line WL and the bit line The area between BL. The read-only memory is to store the second-order bit data by the ion implantation of the channel or not. The first figure is a diagram showing the layout of the conventional programmable read-only memory (Lay Out). . FIG. 2 is a cross-sectional view obtained from the direction of the cross-section of FIG. 1-I, and FIG. 3 is a cross-sectional view obtained from the direction of the cross-section of FIG. 1-II. The manufacturing method of this conventional programmable read-only memory is as follows. Please refer to FIGS. 1, 2 and 3 at the same time. First, a substrate 10 is provided, and then a pad oxide layer (not shown) is formed on the substrate 10 by using a thermal oxidation method, for example. A field oxide layer 14 is then formed on the substrate 10 using, for example, an area oxidation method to define an active area. Ran 4
本紙張尺度適用中國國家榡準（CNS ) A4規輅（210x297公FT ---;------/,V------IT------1 - - (請先閱讀背面之注項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 A7 B7 3345twf.doc/005 五、發明説明o ) 後，例如使用濕蝕刻法淸除墊氧化層。接著，例如使用熱 氧化法，使元件區的表面形成一層氧化層12。然後例如使 用低壓化學氣相沉積法在此氧化層12上形成一層多晶矽 物質。然後利用微影蝕刻技術定義多晶矽物質，以形成多 晶砂層16。 接著例如使用低壓化學氣相沉積法沉積一層內多晶砂 介電物質(Inter-poly Dielectric layer)，覆蓋多晶砂層 16。 然後，使用低壓化學氣相沉積法在此內多晶矽介電物質上 形成另一層多晶矽物質。接著，利用微影蝕刻技術定義此 層多晶矽物質並往下蝕刻內多晶矽介電物質，藉以形成多 晶矽層20與內多晶矽介電層18。 然後，利用微影蝕刻技術並且以多晶矽層20爲罩幕， 進行蝕刻步驟，進一步定義多晶矽層16。接著，同樣以多 晶矽層20爲罩幕進行離子植入步驟，植入濃度較濃的離 子，以形成離子佈植區22。然後例如使用低壓化學氣相沉 積法沉積一層介電層24覆蓋整個基底結構。並且使用微 影蝕刻技術在介電層24上形成接觸窗口 26。並且例如使 用低壓化學氣相沉積法沉積一層金屬層28，於接觸窗口 26 中，且接觸離子佈植區22。其中，金屬層28係作爲位元 線之用。然後進行後續的製程以完成可程式唯讀記憶體之 製造。然而，此後續製程爲熟習此技藝者所能輕易達成， 故此處不再贅述。 然而此習知胞受限於接觸窗口之尺寸，因此無法有突 破性的縮小化。並且因爲形成有場氧化層，所以縮小幅度 5 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公嫠） ϋ— u —It m In ^^^1 ^^^1 n fl^^i I ^^4 . i (請先閱讀背面之注意事項再填寫本頁) 經清部中央標準局貝工消費合作社印犁 經濟部中央標率局貝工消費合作社印裝 3345twf.doc/005 五、發明説明（f ) 有限，且平坦度不佳。若是要在此結構上定義圖案，例如 當進行乾式蝕刻法時，因所欲蝕刻的垂直厚度不同’有的 區域會過厚而有的區域會過薄，在鈾刻時會造成蝕刻不均 勻的情形，導致不易控制適當的蝕刻時間長短。再者，因 爲接觸窗口中需塡入金屬層以作爲位元線之用，因此無法 避免金屬層反射的干擾。 另一種習知可程式唯讀記憶體，則是形成埋入式位元 線(Buried Bit Line)於場氧化層下方，用以縮小尺寸。但是 這種可程式唯讀記憶體因爲存在有場氧化層，所以尺寸縮 小的幅度也有限且平坦度不佳。並且其位元線係形成於場 氧化層下方，因此阻値較高。再者，在這種可程式唯讀記 憶體的製造方法中，因爲場氧化層係形成於埋入式位元線 上方，因此無法以自行對準的方式來形成位元線》 因此本發明的主要目的就是在提供一種一次可程式唯 讀記憶體之製造方法，用以改善習知可程式唯讀記憶體之 缺點。 根據本發明的目的，提出一種一次可程式唯讀記憶體， 包括堆疊之控制閘、內金屬介電層、與浮置閘位於基底上。 此堆疊結構之兩側下方的基底中具有離子佈植區，並且離 子佈植區上形成有金屬砂化物。其中，內金屬介電層包括 氧化層與氮化矽層，並且氧化層係覆蓋浮置閘，而氮化矽 層則包括覆蓋浮置閘與金屬矽化物。此外，控制閘爲覆蓋 內金屬介電層之氮化矽層。 本發明的特徵爲利用自行對準的方式形成埋入式位元 6 本紙張尺度適用中國困家標準（CNS ) A4規格（210X297公楚) ϋ i^i 1^1 1^1 HI In ^^1 In ^HI I m m - J/% i (諳先閱讀背面之注意事項再填寫本頁) 3345twf.doc/005 A7 B7____ 五、發明説明（y) 線，所以不需額外的光罩，也不需形成接觸窗口及塡入金 屬層，因此不會有金屬層反射的干擾。此外本發明中位元 線的電阻値約可比習知技藝中的位元線電阻値降低10至 100倍，所以能夠大幅增加效能。並且，在製程中不需形 成場氧化層，因此依據本發明之方法所獲得之一次可程式 唯讀記憶體胞，具有較佳的平坦度，並且可以大幅縮小尺' 寸。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖係繪示習知可程式唯讀記憶體之佈局圖； 第2圖係繪示從第1圖I-Ι剖面方向所得之剖面圖； 第3圖係繪示從第1圖II-II剖面方向所得之剖面圖； 第4圖係繪示依據本發明之一較佳實施例之一種一次 可程式唯讀記憶體之佈局圖；以及 · 第5A至5E圖繪示依照本發明一較佳實施例之一種一 次可程式唯讀記憶體之製造流程剖面圖，其中第5A與5E 圖是沿著第4圖中III-III方向所得之剖面圖；以及 第6圖係繪示第5E圖的步驟中沿著第4圖IV-IV方 向所得之剖面圖。 10、50 :基底 12、52、56 :氧化層 W:場氧化層 7 本紙張尺度ϋ用中關轉CNS)續^ (2K)X297公楚_) ~ (請先閲讀背面之注意事項再填寫本頁)This paper size applies to China National Standards (CNS) A4 regulations (210x297 male FT ---; ------ /, V ------ IT ------ 1--(please first Read the note on the back and fill out this page) After printing A7 B7 3345twf.doc / 005 by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the invention o), for example, using a wet etching method to remove the pad oxide layer. Next, for example, a thermal oxidation method is used to form an oxide layer 12 on the surface of the element region. A layer of polycrystalline silicon is then formed on the oxide layer 12 using, for example, a low pressure chemical vapor deposition method. The polycrystalline silicon material is then defined using a lithographic etching technique to form a polycrystalline sand layer 16. Then, a low-pressure chemical vapor deposition method is used to deposit an inter-polydielectric layer (16) covering the polycrystalline sand layer 16. Then, another layer of polycrystalline silicon material is formed on the polycrystalline silicon dielectric material by using a low pressure chemical vapor deposition method. Next, the lithographic etching technology is used to define this layer of polycrystalline silicon material and the inner polycrystalline silicon dielectric material is etched down to form a polycrystalline silicon layer 20 and an inner polycrystalline silicon dielectric layer 18. Then, using the lithography etching technology and using the polycrystalline silicon layer 20 as a mask, an etching step is performed to further define the polycrystalline silicon layer 16. Next, the polysilicon layer 20 is also used as a mask to perform an ion implantation step, and a relatively dense ion is implanted to form an ion implantation region 22. A dielectric layer 24 is then deposited over the entire substrate structure, for example using a low pressure chemical vapor deposition method. A contact window 26 is formed on the dielectric layer 24 using a lithographic etching technique. For example, a low-pressure chemical vapor deposition method is used to deposit a metal layer 28 in the contact window 26 and contact the ion implantation region 22. Among them, the metal layer 28 is used as a bit line. Subsequent processes are then performed to complete the manufacture of the programmable read-only memory. However, this subsequent process can be easily achieved by those skilled in this art, so it will not be repeated here. However, this cell is limited by the size of the contact window, so it cannot be dramatically reduced. And because the field oxide layer is formed, the reduction scale is 5 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 cm) ϋ — u —It m In ^^^ 1 ^^^ 1 n fl ^^ i I ^^ 4. I (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Clearance, Shellfish Consumer Cooperatives, India, and the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, printed 3345twf.doc / 005 V. Invention Explanation (f) is limited and the flatness is not good. If you want to define a pattern on this structure, for example, when dry etching is performed, due to the vertical thickness to be etched, some areas will be too thick and some areas will be too thin, which will cause uneven etching when uranium is etched. This makes it difficult to control the length of the appropriate etching time. Furthermore, since a metal layer needs to be inserted into the contact window for use as a bit line, interference from reflection of the metal layer cannot be avoided. Another type of conventional programmable read-only memory is to form a buried bit line under the field oxide layer to reduce the size. However, because of the field oxide layer, the programmable read-only memory has a limited size reduction and poor flatness. And its bit line is formed under the field oxide layer, so the resistance is high. Furthermore, in such a method of manufacturing a programmable read-only memory, since the field oxide layer is formed over the buried bit line, the bit line cannot be formed in a self-aligned manner. The main purpose is to provide a manufacturing method of programmable read-only memory to improve the shortcomings of conventional programmable read-only memory. According to the purpose of the present invention, a one-time programmable read-only memory is provided, which includes a stacked control gate, an inner metal dielectric layer, and a floating gate on a substrate. The substrate below both sides of the stacked structure has an ion implantation area, and a metal sand is formed on the ion implantation area. The inner metal dielectric layer includes an oxide layer and a silicon nitride layer. The oxide layer covers the floating gate, and the silicon nitride layer includes a floating gate and a metal silicide. In addition, the control gate is a silicon nitride layer covering the inner metal dielectric layer. The feature of the present invention is to form the embedded bit 6 by self-alignment. The paper size is applicable to the Chinese Standard for Household Standards (CNS) A4 (210X297). Ϋ i ^ i 1 ^ 1 1 ^ 1 HI In ^^ 1 In ^ HI I mm-J /% i (谙 Please read the notes on the back before filling in this page) 3345twf.doc / 005 A7 B7____ 5. Description of the invention (y) line, so no additional photomask is needed, nor The contact window and the metal layer need to be formed, so there will be no interference from the reflection of the metal layer. In addition, the resistance 位 of the bit line in the present invention can be reduced by about 10 to 100 times than the resistance 位 of the bit line in the conventional art, so the performance can be greatly increased. In addition, no field oxide layer needs to be formed in the manufacturing process, so the one-time programmable read-only memory cell obtained according to the method of the present invention has better flatness and can be greatly reduced in size. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 is a drawing Figure 2 shows the layout of the programmable read-only memory; Figure 2 is a cross-sectional view obtained from the direction of the cross-section of Figure 1-I; Figure 3 is a cross-sectional view obtained from the direction of the cross-section of Figure 1-II Sectional view; FIG. 4 is a layout view of a programmable read-only memory according to a preferred embodiment of the present invention; and FIGS. 5A to 5E are views of a preferred embodiment according to the present invention One-time programmable read-only memory manufacturing process cross-sectional view, where FIGS. 5A and 5E are cross-sectional views taken along the III-III direction in FIG. 4; Fig. 4 is a sectional view taken in the direction of IV-IV. 10, 50: substrates 12, 52, 56: oxide layer W: field oxide layer 7 This paper is scaled to CNS) Continued ^ (2K) X297 Gong Chu_) ~ (Please read the notes on the back before filling (This page)
經濟部中央樣隼局貝工消費合作社印装 3345twf·doc/005 A7 B? 五、發明説明（ 16、20 ' 54、70 .多晶砂靥 18 :內多晶矽介電層 22、58 :離子佈植區 26 :接觸窗口 28 :金屬層 57 :光阻 60、68 :氮化矽層 62 :氮化矽間隙壁 64 :金屬層 66 :金屬矽化物 實施例 施例；1第程:二二係繪示依據本發明之-較佳實 施例之一種一次可程式唯讀記憶體之 請參照第5A至5E圖，其繪 ° milh _ 糌7^依照本發明一較佳實施 例的一種一次可程式唯讀記愴牌 丨私職之製造流程剖面圖。苴 中，第5Λ與5E圖即是沿著第4 l流桎〇」囬圆- π国祖< 給一始^ ^ 圖中出·111方向所得之剖 ®的歩驟中沿著第4圖― 方向所得之剖面圖。 請參照第5A圖，提供〜基隐c cn U ^ 低5 ^，接著例如使用熱氧 化法在此基底50上形成一層翁仏‘ /um与扣uu面白/, k 1七物°然後例如使用低壓 化學氣相沉積法在此層氧化物上 <心成一層多晶矽物質。接 著，_腿雜麵積_^層__蓋此層多 晶矽物質。接著上光阻57依序定義氧化物層 '多晶矽物 質與另一層氧化物，並使用蝕刻技術藉以形成氧化層52、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注•項再填寫本頁)Printed by the Central Engineering Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 3345twf · doc / 005 A7 B? V. Description of the invention (16, 20'54, 70. Polycrystalline sand 靥 18: Inner polycrystalline silicon dielectric layer 22, 58: Ion cloth Planting area 26: contact window 28: metal layer 57: photoresist 60, 68: silicon nitride layer 62: silicon nitride spacer 64: metal layer 66: metal silicide embodiment example; 1 pass: 22 series For a one-time programmable read-only memory according to the preferred embodiment of the present invention, please refer to FIGS. 5A to 5E, which show ° milh _ 糌 7 ^ A one-time programmable according to a preferred embodiment of the present invention Read-only note 怆 The section of the manufacturing process for private employment. In the figure, Figures 5Λ and 5E are along the 4th stream. ○ ″ Circle-π 国 祖 < To the beginning ^ ^ In the picture · Section 4 of the section obtained in the 111 direction is taken along Figure 4-the section obtained in the direction of the direction. Please refer to Figure 5A and provide ~ 基基 c cn U ^ 低 5 ^, and then, for example, using a thermal oxidation method on this substrate 50 A layer of onium oxide is formed on the oxide layer and the core is formed on the oxide layer, for example, using a low pressure chemical vapor deposition method. The silicon material. Next, the _leg area_ ^ layer__ covers this layer of polycrystalline silicon material. Then the photoresist 57 sequentially defines the oxide layer 'polycrystalline silicon material and another oxide, and uses the etching technology to form the oxide layer 52 、 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the note and item on the back before filling this page)
訂 經濟部中央標隼局貝工消費合作社印掣 334 5twf·doc/005 A7 B7 經濟部中央標準局貝工消费合作社印製 五、發明説明（Ί ) 多晶砂層54與氧化層56。 請參照第5B圖，然後使用此光阻57爲罩幕進行自行 對準離子植入步驟，使摻質植入於多晶矽層54兩側下方 的基底50中，當離子佈植區58形成之後，則去除光阻57， 以曝露出氧化層56。隨後使用回火(Anneal)步驟，藉以使 得離子佈植區58的摻質擴散，此離子佈植區58即是作爲 埋入式位元線之用。然後例如使用電漿化學氣相沉積法， 沉積一層氮化矽60覆蓋整個基底結構表面，包括覆蓋氧 化層56的表面》 請參照第5C圖，接著使用回蝕刻法，回蝕刻氮化砂 層60藉以形成氮化矽間隙壁62。然後例如使用濺鍍法， 形成一層金屬層64覆蓋整個基底結構的表面，包括覆蓋 基底50、間隙壁62、與氧化層56的表面。其中，金屬層 64的材質包括鈦金屬。 請參照第5D圖，接著使用快速加熱製程，使得與基 底50接觸之金屬層64形成金屬矽化物層66 ^所以，若金 屬層64之材質爲鈦，則金屬矽化物層66爲矽化鈦。接著， 剝除金屬層64中，其餘未參與反應之金屬。 請參照第5E圖，然後例如使用電漿化學氣相沉積法， 沉積一層氮化矽68覆蓋整個基底結構表面，包括覆蓋氧 化物56、間隙壁62、與金屬矽化物層66。接著，例如使 用低壓化學氣相沉積法形成一層多晶矽物質覆蓋在此層氮 化矽層68上。其中，氮化矽層68與氧化層56共同組成 一內金屬介電層。然後，利用傳統的微影蝕刻技術定義多 9 本紙張尺度適用中國國家標準·（ CNS ) A4規棺（210X297公t ) (請先閱讀背面之注項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印笨 334 5twf.doc/005 A/ ___5Z_ 五、發明説明（g ) 晶矽物質，藉以形成多晶矽層70，此多晶矽層70係作爲 控制閘之用。然後以多晶矽層70爲罩幕，進一步往下蝕 刻多晶矽層54，藉以使得多晶矽層54成爲浮置閘。隨後 進行離子植入步驟。此時沿著第4圖中IV-IV方向所得之 剖面圖則如第6圖所示。 接著，進行後續的製程以完成可程式唯讀記憶體之製 造。然而，此後續製程爲熟習此技藝者所能輕易達成，故 此處不再贅述。 因此，本發明的特徵爲位元線可自行對準多晶矽層 54，並且浮置閘可自行對準多晶矽層70。 本發明的特徵爲埋入式位元線可對準自行對準多晶矽 層54，此外本發明中因爲形成有金屬矽化物層66，所以 位元線的電阻値約可比習知技藝中的位元線電阻値降低10 至100倍，所以能夠大幅增加效能。並且本案不需形成接 觸窗口也不需塡入金屬層，因此不會有金屬層反射的干 擾。 並且，在本發明之製程中不需形成場氧化層，因此依 據本發明之方法所獲得之一次可程式唯讀記憶體，具有較 佳的平坦度，並且可以大幅縮小尺寸。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準》 本紙張尺度適用中國國家標半（CNS ) Λ4说格（210Χ297公犮） ^^^1 ^^1 1^1 In ^^1 ^^1 1^1 I 1^1 . . .(¾ (請先閱讀背面之注意事項再填寫本頁)Order printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 334 5twf · doc / 005 A7 B7 Printed by Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (Ί) Polycrystalline sand layer 54 and oxide layer 56. Please refer to FIG. 5B, and then use the photoresist 57 as a mask to perform self-aligned ion implantation steps, so that dopants are implanted into the substrate 50 below the sides of the polycrystalline silicon layer 54. After the ion implantation region 58 is formed, Then, the photoresist 57 is removed to expose the oxide layer 56. An annealing step is subsequently used to diffuse the dopants in the ion implantation region 58. This ion implantation region 58 is used as a buried bit line. Then, for example, a plasma chemical vapor deposition method is used to deposit a layer of silicon nitride 60 to cover the entire surface of the base structure, including the surface of the oxide layer 56. Please refer to FIG. 5C, and then use the etch-back method to etch back the nitrided sand layer 60. A silicon nitride spacer wall 62 is formed. Then, for example, a sputtering method is used to form a metal layer 64 covering the entire surface of the base structure, including the surface covering the substrate 50, the spacer 62, and the oxide layer 56. The material of the metal layer 64 includes titanium. Referring to FIG. 5D, a rapid heating process is used to form a metal silicide layer 66 on the metal layer 64 in contact with the substrate 50. Therefore, if the material of the metal layer 64 is titanium, the metal silicide layer 66 is titanium silicide. Next, the remaining metal in the metal layer 64 that is not participating in the reaction is stripped. Please refer to FIG. 5E, and then, for example, plasma chemical vapor deposition is used to deposit a layer of silicon nitride 68 covering the entire surface of the substrate structure, including covering the oxide 56, the spacer 62, and the metal silicide layer 66. Next, a layer of polycrystalline silicon is formed on the silicon nitride layer 68, for example, using a low pressure chemical vapor deposition method. Among them, the silicon nitride layer 68 and the oxide layer 56 together form an inner metal dielectric layer. Then, use traditional lithographic etching techniques to define 9 more paper sizes. Applicable to Chinese National Standards ((CNS) A4 Regulation Coffin (210X297g)) (Please read the note on the back before filling this page) Order the Central Bureau of Standards of the Ministry of Economic Affairs Employee Consumer Cooperative Co., Ltd. Yinben 334 5twf.doc / 005 A / ___5Z_ 5. Description of the Invention (g) A crystalline silicon substance is used to form a polycrystalline silicon layer 70, which is used as a control gate. Then, using the polycrystalline silicon layer 70 as a mask, the polycrystalline silicon layer 54 is further etched downward, so that the polycrystalline silicon layer 54 becomes a floating gate. This is followed by an ion implantation step. The cross-sectional view taken along the IV-IV direction in Figure 4 is shown in Figure 6. Then, the subsequent process is performed to complete the manufacture of the programmable read-only memory. However, this follow-up process can be easily achieved by those skilled in this art, so it will not be repeated here. Therefore, the present invention is characterized in that the bit line can be aligned with the polycrystalline silicon layer 54 by itself, and the floating gate can be aligned with the polycrystalline silicon layer 70 by itself. The feature of the present invention is that the buried bit line can be aligned with the self-aligned polycrystalline silicon layer 54. In addition, since the metal silicide layer 66 is formed in the present invention, the resistance of the bit line can be compared with the bit in the conventional art. The line resistance 値 is reduced by 10 to 100 times, so the performance can be greatly increased. In this case, it is not necessary to form a contact window or penetrate the metal layer, so there is no interference from the reflection of the metal layer. In addition, a field oxide layer is not required to be formed in the process of the present invention. Therefore, the once-programmable read-only memory obtained according to the method of the present invention has better flatness and can be greatly reduced in size. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. "The paper size is applicable to the Chinese National Standard Half (CNS) Λ4 grid (210 × 297). ^^^ 1 ^^ 1 1 ^ 1 In ^^ 1 ^^ 1 1 ^ 1 I 1 ^ 1... (¾ (Please read the notes on the back before filling this page)
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