565931 A7 B7 五·、發明說明（ 【技術領域】 本發明係提供-種用於製造永久性記憶體元件之儲存 皁兀的方法’乃相關EEPR0M*快閃記憶體元件的永久性 記憶體元件，特別的是關於減少各儲存單元大小的製造方 【技術背景】 EEPROM，或是快閃記憶體的永久性記憶體元件，近 年使用在數位電話、數位式資訊轉換器、數位相機、個人 電腦、數據機、傳真機、數位式錄影機、DVD等周邊易接 觸的家電用品上。還有，為了達成前述家電用品的小型化 及高機能化，積極對EEPR0M，或快閃記憶體的高密集化 進行研究。 此類EEPROM，或快閃記憶體的儲存單元有眾所皆知 的NOR型和NAND型。 NOR型儲存單元如第1圖所示，位元線扯是連結各儲 存單元的汲極D，字元線WL是連各儲存單元的閘電極G , 即連結於控制閘，源極線队是連㈣存單元的源極s的構 造。圖示符號fg是表示浮置閘極。 1 局 員 工 消 費 社 印 但是，雖然此類型NOR型儲存單元的優點是速度快， 卻因在各單元容量受限制，不易使密集度提高。換言之， NOR型儲存單元因位元線BL是連結各儲存單元的汲極d， 源極線SL連結各單元的源極s的構造。在各儲存單元内必須 準備一定接觸點面積的情況下，提高密集度是很困難的。 NAND型儲存單元如第2圖所示，第丨位元線bli連結谷 本紙張尺ί適用甲國國家標準（CNS)A4規格（21〇 χ挪公髮 565931 A7 B7 五、發明說明（ 個儲存單元和2個選擇電電晶體™、TR2’第2位元線BL2 也連結8個儲存單元和2個選擇電電晶體TR3、TR4。㈣立 元線BL1和第2位元線BL2的另一側，即選擇電電晶體丁^、 TR4的源極s連結源極線SL，這個結果是⑹固儲存單元成為 一個單位的構造。 此NAND型儲存單元在全部的儲存單元内不存在任接 觸點’有提咼岔集度的優點。換言之，nand型儲存單元的 位元線BL1、BL2是連結第存單元的汲極D，其他的電晶 體以直列連結’源極線儿連結最終儲存單元的源極s。如 此，儲存單元的連結面積為最小化，易提高密集度。但是， 訂 NAND型儲存單元因為須有16個儲存單元及4個選擇電晶 體’速度慢是其缺點。 此外，前述的>!011型及>1八^[]：)型在儲存單元上是由元 件隔離膜、浮置閘極、控制閘極、源/汲電極、源極線、位 線 元線所構成，這時，儲存單元在理論上得到各構成要素的 最小體積。 濟 部 智 員 工 消 費 為對應在形成中產生罩幕的誤差整列及臨界尺寸等變 化，孤立各儲存單元所形成的浮置閘極，做了元件隔離膜 和特定區域重疊的設計。即為第3A圖的表示，在元件隔離 膜及浮置閘極形成時使用的元件分離罩幕3〇2和浮置閘極 罩幕304的各邊緣特定區域設計呈相互重疊狀態。 第3B圖是習習知浮置閘極罩幕3〇4和控制閘極罩幕 的平面示意圖。 因此，假定以0_ 1 8 # m技術來製造儲存單元，理論上最 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）565931 A7 B7 V. Description of the invention ([Technical Field] The present invention provides a method for manufacturing a storage memory device of a permanent memory element, which is a permanent memory element of the related EEPROM * flash memory element, In particular, the manufacturer of reducing the size of each storage unit [Technical Background] EEPROM, or permanent memory elements of flash memory, has been used in recent years in digital phones, digital information converters, digital cameras, personal computers, data Machines, facsimiles, digital video recorders, DVDs, and other household appliances that are easily accessible. Also, in order to achieve the miniaturization and high performance of the aforementioned household appliances, EEPR0M or flash memory has been actively increased. Research. The memory cells of this type of EEPROM or flash memory are well-known NOR type and NAND type. The NOR type memory cell is shown in Figure 1. The bit line is the drain D connecting the memory cells. The character line WL is the gate electrode G connected to each storage cell, that is, connected to the control gate, and the source line is the structure of the source s of the continuous storage cell. The symbol fg in the figure indicates a floating gate. However, although the advantage of this type of NOR-type storage unit is fast, it is difficult to increase the density because of the limited capacity of each unit. In other words, the NOR-type storage unit is connected to each other because of the bit line BL. The structure in which the drain d and the source line SL of the storage unit are connected to the source s of each unit. In the case where a certain contact point area must be prepared in each storage unit, it is difficult to improve the density. As shown in Figure 2, the bit line li is connected to the Guben paper ruler. It is applicable to the National Standard A (CNS) A4 specification (21〇χ 公公 发 565565 A7 B7. 5. Description of the invention (storage unit and 2 selection transistors) ™, TR2 '2nd bit line BL2 also connects 8 memory cells and 2 selection transistors TR3, TR4. The other side of the Lithuanian line BL1 and the 2nd bit line BL2, that is, the selection transistor D1, The source s of TR4 is connected to the source line SL. As a result, the solid-state storage unit becomes a unit structure. This NAND-type storage unit does not have any contact points in all the storage units. In other words, nand The bit lines BL1 and BL2 of the memory cell are the drain electrodes D connected to the first memory cell, and the other transistors are connected to the source s of the final memory cell in series. It is easy to increase the density. However, ordering a NAND type storage unit requires 16 storage units and 4 selection transistors. 'Slow speed is its disadvantage. In addition, the aforementioned >! 011 type and > 1 八 ^ [] :) type is composed of element isolation film, floating gate, control gate, source / drain electrode, source line, bit line element line on the storage unit. At this time, the storage unit theoretically obtains each constituent element. The smallest volume. In order to respond to changes in the error alignment and critical dimensions of the mask during the formation, the Ministry of Economic Affairs has isolated the floating gates formed by each storage unit, and designed a component isolation film that overlaps with a specific area. That is, FIG. 3A shows that the specific regions of each edge of the element separation mask 300 and the floating gate mask 304 used in forming the element isolation film and the floating gate are designed to overlap each other. Fig. 3B is a schematic plan view of a conventional floating gate shield 300 and a control gate shield. Therefore, it is assumed that the storage unit is manufactured with 0_ 1 8 # m technology. Theoretically, the paper size is in accordance with China National Standard (CNS) A4 (210 X 297 public love).
I 565931 A7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 小體積是變成元件隔離膜的大小〇· 18 // m和浮置閘極的大 小0 · 18 // m ’合計〇 · 3 6 // m。但依習知方法製造的話，實際 十月況是，考慮在理論上最小體積0 _ 3 6 // m罩幕的誤整列及臨 界尺寸的變化，大約又加了 0.06//m，成為〇·48//ηι。結果， 以習知技術製造儲存單元的情形是，實際的大小會比理論 上的大上33% 。 根據習知技術製造NOR型及NAND型的情形，為了增 加元件隔離膜和浮置閘極間的重疊領域的單位儲存單元大 小’結果是NOR型與NAND型的密集度難以提高。 【發明解決課題】 有鑑於斯，本發明之目的係提供一種減少單位快閃記 憶體大小的永久性記憶體元件之儲存單元製造方法。 【解決課題手段】 緣是’為達上述本發明之目的，遂提供一種永久性記 憶體元件之儲存單元製造方法，係包含有在半導體基板上 依序裝設浮置閘絕緣膜及浮置閘極用導電膜的步驟；依序 對該膜和半導體基板的特定厚度施行部分蝕刻處理，而 成溝渠的步驟·，在其上面形成絕緣膜，而將該溝渠全部 入的步驟；對，該絕緣膜施行回蝕處理，直到該浮置閘極用 導電膜裸露出，而形成和該浮置閘極用導電膜具相同高度 之元件分離膜的步驟；在該浮置閘極用導電膜及元件分 膜上依序形成控制閘絕緣膜和控制閘極用導電膜的步^ 對該控制閘極用導電膜、控制閘絕緣膜、浮置閘極用導 膜及浮置閘絕緣膜施行蝕刻處理，而形成具疊層構造的 形 埋 離 電 浮 (請先閱讀背面之注意事項再填寫本頁) 裝 l·---訂---------線 本紙張尺度適財關家標準（CNS)A4規格⑽χ 297公€ -5 - 五、發明說明（4) 置閘極和控制閘極者。 、々：有陰：達上述本發明的另一目的’遂提供-種製造 水久性记憶體元件之儲存單元的方法，係包含有在半導體 基板上形成姓刻防止膜的步驟；依序對該姓刻防止膜和半 導體基板的.特定厚度施行部分餘刻處理，而形成溝渠的步 驟，在其上面形成絕緣膜，而將該溝渠全部埋入的步驟； 對該絕緣膜施行回姓處理，直到該钱刻防止膜裸露出，而 形成該㈣防止膜具相同高度之元件分離膜的步驟；去除 該触刻防止㈣㈣；在裸露出的半導體基板上形成浮置 閘絕緣膜’在该_置閘、絕緣膜上形成浮置閘極用導電膜， 而將該元件分離膜間的領域全部埋人的步驟；對該浮置間 極用導電膜施行回敍處理，直到該元件分離膜裸露出的步 驟；在經回姓處理的浮置間極用導電膜和元件分離膜上， 依序形成控制閘絕緣膜和控—制極用I電膜的步驟；'對該 控制閉極用導電膜、控制閘Μ緣膜、浮置閘極用導電膜及 浮置閘絕緣膜施行蝕刻處理，而形具疊層構造的浮置閘極 和控制閘極者。 【圖式簡單說明】 第1圖係典型的EEPROM或快閃記憶體的NOR型儲存單元 的等效回路示意圖。 第2圖係典型的EEPr〇m或快閃記憶體的nAN]d型儲存單 元的等效回路示意圖。 · 第3Α圖係依照習知技術在n〇r型和NAND型儲存單元的制 造時，使用的元件分離罩幕和浮置閘極罩幕的平面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 565931 A7 五、發明說明（ 示意圖。 第3B圖係依照習知技術在NOR型和NAND型儲存單元的制 造時，使用的浮置閘極罩幕和控制閘極罩幕的平面 示意圖。 第4A圖係本發明在NOR型和NAND型儲存單元的製造時， 使用的元件分離罩幕和浮置閘極罩幕的平面示音 圖。 第4B圖係依照習知技術在NOR型和NAND型儲存單元的制 造時’使用的浮置閘極罩幕和控制閘極罩幕的平面 示意圖。 第5 A〜F圖係依照本發明的實施例，為說明儲存單元的警迭 方法，沿第4A圖的X—X，線及γ—γ,線切剖的剖 面示意圖。 第6A〜F圖係依照本發明的另一實施例，為說明儲存單元的 製造方法，沿第4A圖的X — X，線及γ—γ，線切剖 的剖面示意圖。 【圖示符號說明】 κ ί-ΊΙΙ-τ— ^-----r ---^---------^ I (請先閱讀背面之注音？事項再填寫本頁w 經濟部智慧財產局員工消費合作社印製 402 元件分離罩幕 406控制閘極罩幕 503絕緣膜 505a浮置閘極 508元件分離膜 5 12控制閘極用導電膜 514源極 403浮置閘極罩幕 500半導體基板 505浮置閘極用導電膜 507絕緣膜 i 510絕緣膜 512a控制閘極 516汲極I 565931 A7 V. Description of the Invention (The small volume printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is the size of the component isolation film 〇 · 18 // m and the size of the floating gate 0 · 18 // m 'total 〇 · 3 6 // m. But if it is manufactured according to the conventional method, the actual October situation is that, considering the theoretical minimum volume of 0 _ 3 6 // m curtain misalignment and the change in critical size, about 0.06 / / m, which becomes 0.48 // ηι. As a result, in the case of manufacturing the storage unit by the conventional technology, the actual size will be 33% larger than the theoretical size. In the case of manufacturing the NOR type and the NAND type according to the conventional technology, In order to increase the size of the unit memory cell in the overlapping area between the element isolation film and the floating gate, as a result, it is difficult to increase the density of the NOR type and the NAND type. [Inventive Problem] In view of this, the object of the present invention is to provide a reduction Method for manufacturing a storage unit of a permanent memory element having a unit size of a flash memory. [Means for solving the problem] The reason is to provide a method for manufacturing a storage unit of a permanent memory element in order to achieve the above-mentioned object of the present invention. The method includes the steps of sequentially installing a floating gate insulating film and a conductive film for a floating gate on a semiconductor substrate, and sequentially performing a partial etching process on the film and a specific thickness of the semiconductor substrate to form a trench. A step of forming an insulating film on the trench and fully injecting the trench; on the insulating film, an etch-back process is performed until the floating gate electrode is exposed to form a conductive film for the floating gate electrode Steps for separating films of components of the same height; Steps of sequentially forming a control gate insulating film and a control gate conductive film on the floating gate conductive film and a component separation film ^ For the control gate conductive film, control The gate insulation film, the conductive film for the floating gate electrode, and the floating gate insulation film are etched to form a shape-buried ion float with a laminated structure (please read the precautions on the back before filling this page). Installation l ·- --Order --------- Line paper size Standards for Financial Services (CNS) A4 Specification ⑽χ 297 € -5-V. Description of the invention (4) Those who place and control the gate. 々: There is yin: to achieve the above-mentioned another object of the present invention, and then provide a kind of manufacturing A method for storing a water-resilient memory element includes a step of forming a surname prevention film on a semiconductor substrate; sequentially performing a part of the remaining thickness treatment on the surname prevention film and the semiconductor substrate in order, and The step of forming a trench, the step of forming an insulating film on top of it, and burying the trench in its entirety; performing a return-to-lasting treatment on the insulating film until the money-cut prevents the film from being exposed, and forming the anti-film with the same height The step of separating the film of the element; removing the contact engraving to prevent ㈣㈣; forming a floating gate insulating film on the exposed semiconductor substrate; and forming the conductive film for the floating gate on the insulating gate and the insulating film to separate the element The steps of burying people in the field between the membranes; the step of performing a retrospective process on the floating interelectrode with a conductive film until the element separation film is exposed; separating the conductive interlayer and the element with the floating interelectrode after the surname treatment Steps of sequentially forming a control gate insulating film and a control-electrode I electric film on the film; 'the conductive film for the control closed electrode, the edge film of the control gate, the conductive film for the floating gate, and the floating gate insulation Film application An etching process is performed, and a floating gate and a control gate having a stacked structure are formed. [Schematic description] Figure 1 is a schematic diagram of an equivalent circuit of a typical EEPROM or NOR-type memory cell of a flash memory. Figure 2 is a schematic diagram of the equivalent circuit of a typical EEProm or flash memory nAN] d type storage unit. · Figure 3A is the plane of the element separation cover and floating gate cover used in the manufacturing of nor and NAND storage cells according to the conventional technology. The paper standards are applicable to the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) 565931 A7 V. Description of the invention (Schematic diagram. Figure 3B shows the floating gate shield and control gate shield used in the manufacture of NOR and NAND memory cells in accordance with conventional technologies. FIG. 4A is a plan view of a component separation cover and a floating gate cover used in the manufacture of NOR-type and NAND-type storage cells according to the present invention. Planar schematic diagrams of the floating gate cover and the control gate cover used in the manufacture of NOR-type and NAND-type storage units. Figures 5A to F are diagrams illustrating the warning of the storage unit according to the embodiment of the present invention. The method is a schematic cross-sectional view taken along line X-X, line and γ-γ, line in Fig. 4A. Figs. 6A to F are diagrams according to another embodiment of the present invention. Figure X-X, line and γ-γ, line cross-section [Illustration of Symbols] κ ί-ΊΙΙ-τ— ^ ----- r --- ^ --------- ^ I (Please read the note on the back? Matters before filling out this page w Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative, 402 Component separation cover 406 Control gate cover 503 Insulation film 505a Floating gate 508 Element separation film 5 12 Conductive film for controlling gate 514 Source 403 Floating gate Screen 500 semiconductor substrate 505 floating gate conductive film 507 insulating film i 510 insulating film 512a control gate 516 drain
565931 五、發明說明（ 智 慧 局 員 工 消 費 製 600基板 603浮置閘絕緣膜 605a浮置閘極 608元件分離膜 612控制閘極用導電膜 614源極 T 溝渠 【發明實施較佳態樣】 本盔明的目的和優點，請參閱以下的詳細說明及附圖 表示。 第4A圖所示係本發明的元件分離罩幕和浮置閘極罩幕 的平面表不圖。如第4A圖冷表示的，本發明的元件分離罩 幕402與浮置閘極罩幕綱，和第从圖所示的習知技術不 同，邊緣的區域沒有重疊。這是浮置問極使用元件分離膜 以自對準方式形成的原因。 緣是，前記元件分離膜及浮置閘極因省略重疊領域， 理論上最小體積是可能形成的，結果是儲存單元大小得以 減少。 請參考第4B圖，第4B圖所示係本發明的浮置閘極罩幕 404和控制閘極罩幕406的平面表示圖。 以下，請參閱附圖所示，針對本發明較佳實施態樣的 儲存單元製造方法進行說明。 ' 第5A圖到第5F圖係依照本發明的實施例，為說明儲存 早元的衣造方法’沿弟4 A圖的X ~ X ’線及γ 一 γ，線士 601蝕刻防止膜 605浮置閘極用導電膜 607絕緣膜 610控制閘絕緣膜 612a控制閘極 616 >及極 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复） 565931 五、發明說明（ 的剖面示意圖。 第5A圖所示係在半導體基板5〇〇上形成以浮置間絕緣 膜503作的氧化膜或氧化氮膜，在該浮置閘絕緣膜5〇3上形 成以矽膜作的浮置閘極用導電膜5〇5。該膜5〇5、5〇3和半導 體基板500在第4A圖所示的元件分離罩幕4〇2依序蝕刻處 理，如此，在半導體基板500的特定區域形成溝渠丁。 第5B圖所不係在該完成品上形成絕緣膜5〇7，俾將溝渠 T全部埋入。前記絕緣膜5〇7最好是氧化膜。 第5C圖所示係前，採用_氣體或用化學機械研磨法 (CMP)，對絕緣膜施行回蝕處理，直到浮置閘極用導電膜 裸露出為止，俾形成和該浮置閘極用導電膜5〇5有同樣高度 的元件分離膜508。 ▲ 第5D圖所不係在浮置閘極用導電膜5〇5及元件分離膜 508上，以氧化膜或氧化氮膜形成控制閘絕緣膜51〇，在該 控制閘絕緣膜510上，以矽膜形成控制閘極用導電膜512， 即矽膜和金屬膜的疊層膜。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 第5E圖所不係控制閘極用導電膜、控制閘絕緣膜、浮 置閘極用導電膜及浮置閘絕緣膜在第化圖所示的控制閘極 罩幕406依序蝕刻處理，如此形成有疊層構造的浮置閘極 505a及控制閘極512a。此時，閘極間的半導體基板區域， 也就是形成源極和汲極的半導體基板區域是裸露出的狀 態。 第5F圖所不係在裸露出的半導體基板區域，從硼、磷 或砷中選擇一種雜質施行離子植入及熱擴散處理，而形成 x 297公釐） 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 •9- 565931 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 源極和沒極5 14、5 16。 之後，雖無圖示，但為符合NOR型或NAND型儲存單 元的結構，依習知方法，形成在汲極5 16連結的位元線和在 源極514連結的源極線，至此，NOR型或NAND型儲存單元 已完成。 在則述的實施例中’為使浮置閘極5 0 5 a在元件分離膜 508上以自對準方式形成，該浮置閘極5〇5a和元件分離膜 5 〇 8不需要重疊。如此，浮置閘極5 〇 5 a和元件分離膜5 〇 8在 理論上最小體積是可能形成的，儲存單元大小得以減少， 結果是，NOR型或NAND型儲存單元得以呈現高密集化。 第6 A圖到第6F圖係依照本發明的另一實施例，為說明 儲存單元的製造方法，沿第4A圖的Χ—χ，線及γ_γ，線 切剖的剖面示意圖。 — 第6A圖所示係蝕刻防止膜6〇1在半導體基板6〇〇上形 成。該蝕刻防止膜601由氧化膜和氧化氮膜的疊層構造或 氧化膜和矽膜的疊層構造中形成較為理想。再者，該蝕刻 防止膜601必須比在後續工程中形成的浮置閘極還厚。盆原 因為，餘刻防止膜的厚度必須和在後續工程中形成的浮置 閘絕緣膜及浮置閘極合計的厚度相#。該㈣防止膜6〇ι和 半導體基板600的特定深度卜厚度） 又v序度）在苐4 A圖所示的元件 分離罩幕4〇2依序蝕刻處理，如卜， 处主如此，在το件分離膜上形成溝 渠T 〇 第6B圖所示係在該完成品 上$成纟巴緣膜607以埋入溝 渠T。該絕緣膜607最好是氧化膜565931 V. Description of the Invention (Consumer-made 600 substrates made by employees of the Wisdom Bureau 603 Floating gate insulation film 605a Floating gate 608 Element separation film 612 Conductive film for controlling the gate 614 Source T trench [Practice of the invention] The helmet For the purpose and advantages of the invention, please refer to the following detailed description and the accompanying drawings. Figure 4A is a plan view of the component separation cover and floating gate cover of the present invention. As shown in Figure 4A The element separation cover 402 of the present invention is different from the floating gate cover outline, unlike the conventional technique shown in the figure, there is no overlap in the edge area. This is the use of a component separation film for self-alignment of the floating question electrode. The reason is that the reason for this is that, due to the omission of overlapping areas of the separation membrane and floating gate of the previous element, theoretically the smallest volume is possible, and as a result, the size of the storage unit is reduced. Please refer to FIG. 4B and FIG. 4B It is a plan view of the floating gate shield 404 and the control gate shield 406 of the present invention. Hereinafter, referring to the drawings, a method for manufacturing a storage unit according to a preferred embodiment of the present invention will be described. Figures 5A to 5F are according to an embodiment of the present invention. In order to explain the clothes manufacturing method of storing the early yuan, the lines X ~ X 'and γ-γ of Figure 4A, the lineman 601 etching prevention film 605 floating gate Conductive film for electrode 607 Insulation film 610 Control gate Insulation film 612a Control gate 616 > and polar wire This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 public copy) 565931 5. Description of the invention As shown in FIG. 5A, an oxide film or a nitrogen oxide film made of a floating interlayer insulating film 503 is formed on a semiconductor substrate 500, and a floating silicon film is formed on the floating gate insulating film 503. The conductive film 505 for the gate is sequentially etched with the element separation mask 400 shown in FIG. 4A and the semiconductor substrate 500 on the semiconductor substrate 500. Thus, in a specific area of the semiconductor substrate 500 Formation of trenches. Figure 5B does not involve forming an insulating film 507 on the finished product, so that all trenches T are buried. The previous insulating film 507 is preferably an oxide film. As shown in Figure 5C, Use _ gas or chemical mechanical polishing (CMP) to etch back the insulating film until the floating gate Until exposed by the conductive film, the element separation film 508 having the same height as the conductive film for floating gate 505 is formed. ▲ The conductive film for floating gate 505 and the device are not shown in FIG. 5D. On the separation film 508, a control gate insulating film 51 is formed with an oxide film or a nitrogen oxide film. On the control gate insulating film 510, a conductive film for control gate 512 is formed with a silicon film, that is, a stack of a silicon film and a metal film. Printed in Figure 5E by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the conductive gate control film, control gate insulation film, floating gate conductive film and floating gate insulation film are not shown in the first figure. The control gate mask 406 is sequentially etched, so that the floating gate 505a and the control gate 512a of the stacked structure are formed. At this time, the semiconductor substrate region between the gates, that is, the semiconductor substrate region where the source and drain electrodes are formed is exposed. Figure 5F does not apply to the bare semiconductor substrate area. Select an impurity from boron, phosphorus, or arsenic to perform ion implantation and thermal diffusion treatment to form x 297 mm.) This paper size applies Chinese National Standards (CNS) A4 specifications (21〇 • 565565 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention () Source and non-polar 5 14, 5 16. After that, although not shown, it is NOR type The structure of the NAND-type memory cell is formed by bit lines connected at the drain electrode 5 16 and the source line connected at the source electrode 514 according to the conventional method. So far, the NOR-type or NAND-type memory cell has been completed. In the embodiment of the invention, in order to form the floating gate electrode 5 05 a on the element separation film 508 in a self-aligned manner, the floating gate electrode 505a and the element separation film 508 do not need to overlap. The gate electrode 5 0 5 a and the element separation film 5 0 8 are theoretically possible to form a minimum volume, and the size of the memory cell can be reduced. As a result, the NOR or NAND type memory cell can be highly dense. Figure 6 A FIG. 6F is another embodiment according to the present invention. In order to explain the manufacturing method of the memory cell, a schematic cross-sectional view taken along the line XX, γ and γ_γ in FIG. 4A is shown. — The etching prevention film 601 shown in FIG. 6A is formed on the semiconductor substrate 600. The etching prevention film 601 is preferably formed from a laminated structure of an oxide film and a nitrogen oxide film, or a laminated structure of an oxide film and a silicon film. Furthermore, the etching prevention film 601 must be more than a floating gate formed in a subsequent process. The reason is that the thickness of the remaining prevention film must be equal to the total thickness of the floating gate insulation film and the floating gate electrode formed in the subsequent process. The thickness of the prevention film 6 and the semiconductor substrate 600 Specific depth (thickness) and v-sequence degree) The element separation mask 402 shown in Figure 4A is sequentially etched. As shown by the owner, a trench T is formed on the το separation film. Figure 6B The figure shows that the finished film is formed into a rim film 607 to bury the trench T. The insulating film 607 is preferably an oxide film
本紙張尺度適财關家標準（CNS)A4規格 J -----r---^---------M r (請先閱讀背面之注意事項再填寫本頁) -10- 565931 A7The paper size is suitable for financial and family care standards (CNS) A4 specifications J ----- r --- ^ --------- M r (Please read the precautions on the back before filling this page) -10 -565931 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（9 ) 第6C圖所示係在蝕刻防止膜601裸露出前，絕緣膜用蝕 刻氣體或用化學機械研磨法（CMP)，依回蝕處理形成和該姓 刻防止膜601有同樣高度的元件分離膜6〇8。 其次’第6D圖所示係除去姓刻防止膜，如此，在半導 體基板600的特定區域’也就是浮置閘極所形成的區域會裸 路出。在裸露出的半導體基板區域上形成浮置閘絕緣膜 603，之後，在該完成品上形成浮置閘極用導電膜6〇5以埋 入元件分離膜608間的區域。此處，浮置閘絕緣膜6〇3以氧 化膜或氧化氮膜，及浮置閘極用導電膜6〇5以矽膜形成較理 想。該浮置閘絕緣膜603在元件分離膜6〇8的側面和上面形 成。 第6E圖所示係在元件分離膜608裸露出前，採用蝕刻氣 體或以化學機械研磨法（CMP)，對浮置閘極用導電膜盡施行 回蝕處理，而在浮置閘極用導電膜6〇5和元件分離膜6〇8上 形成控制閘絕緣膜610及控制閘極用導電膜612。此處，控 制閘絕緣膜610以氧化膜或氧化氮膜，及控制閘極用導電膜 612以矽膜形成較理想。 如第6F圖所示般，對控制閘極用導電膜、控制閘絕緣 膜、浮置閘極用導電膜及浮置閘絕緣膜，採用如第4B圖所 示的控制閘極罩幕406，依序施行蝕刻處理，俾形成具疊層 構造的浮置閘極605a及控制閘極612a。此時，閘極間的半 導體基板區域，也就是形成源極及沒極的半導體基板區域 是裸露出的狀態。在裸露出的半導體基板區域，從硼、磷 或珅中選擇一種雜質做離子植入及熱擴散處理形成源極及 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---^ K----- U----Γ--^ * I I--t----I----線 r (請先閱讀背面之注意事項再填寫本頁) -11- 565931 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 10 汲極 614、616。 之後，雖無圖示，但為符合NOR型或NAND型儲存單 元的結構，依習知方法，形成在沒極616連結的位元線和在 源極614連結的源極線，至此，NOR型或NAND型儲存單元 已完成。 在此實施例中，因為浮置閘極605a和之前的實施例一 樣，在元件分離膜608上以自對準方式形成，不要和元件分 離膜508重疊，如此，在理論上最小體積是可能形成的，儲 存單元大小得以減少，結果是，NOR型或NAND型儲存單元 得以呈現高密集化。 雖由以上實施例說明本發明，但在不脫離其要旨的範 圍内，能夠實施多樣化的變更。 【發明功效】 ， 綜上所述，本發明係使浮置閘極在元件分離膜上以自 對準方式形成，該浮置閘極和元件分離膜能夠形成最小體 積。因而，NOR型或NAND型的儲存單元大小得以減少，如 此，能夠實現符合家電用品的小型化及高機能化的永久性 記憶體元件的高密集度。 ‘ (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (9) Figure 6C shows that before the etching prevention film 601 is exposed, the insulating film is etched with an etching gas or chemical mechanical polishing (CMP), and is etched back. An element separation film 608 having the same height as the engraved prevention film 601 was formed. Next, as shown in FIG. 6D, the anti-engraving prevention film is removed. In this way, a specific region of the semiconductor substrate 600, that is, a region formed by a floating gate, is exposed. A floating gate insulating film 603 is formed on the exposed semiconductor substrate region, and then a conductive film for floating gate 605 is formed on the finished product to bury the region between the element separation films 608. Here, the floating gate insulating film 603 is preferably formed of an oxide film or a nitrogen oxide film, and the floating gate conductive film 605 is formed of a silicon film. The floating gate insulating film 603 is formed on the side and upper surfaces of the element separation film 608. As shown in FIG. 6E, before the element separation film 608 is exposed, the conductive film for the floating gate is etched back by etching gas or chemical mechanical polishing (CMP), and the conductive film is used for the floating gate. A control gate insulating film 610 and a control gate conductive film 612 are formed on 605 and the element separation film 608. Here, it is preferable that the control gate insulating film 610 is formed of an oxide film or a nitrogen oxide film, and the control gate conductive film 612 is formed of a silicon film. As shown in FIG. 6F, the control gate shield film 406 shown in FIG. 4B is used for the control gate conductive film, the control gate insulation film, the floating gate conductive film, and the floating gate insulation film. The etching process is sequentially performed to form a floating gate electrode 605a and a control gate electrode 612a having a stacked structure. At this time, the semiconductor substrate region between the gates, that is, the semiconductor substrate region where the source and non-electrodes are formed is exposed. In the exposed semiconductor substrate area, select an impurity from boron, phosphorus, or thorium for ion implantation and thermal diffusion treatment to form the source and the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- -^ K ----- U ---- Γ-^ * I I--t ---- I ---- line r (Please read the precautions on the back before filling this page) -11 -565931 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy V. Invention Description (10) Dip 614, 616. Thereafter, although not shown, in order to conform to the structure of a NOR-type or NAND-type memory cell, a bit line connected at the non-pole 616 and a source line connected at the source 614 are formed according to a conventional method. So far, the NOR-type Or the NAND-type memory cell has been completed. In this embodiment, since the floating gate electrode 605a is formed on the element separation film 608 in a self-aligned manner as in the previous embodiment, do not overlap with the element separation film 508. Thus, in theory, the smallest volume is possible to be formed As a result, the memory cell size is reduced, and as a result, NOR-type or NAND-type memory cells are highly dense. Although the present invention has been described by the above embodiments, various changes can be made without departing from the scope of the present invention. [Effect of the invention] In summary, the present invention is to make the floating gate electrode self-aligned on the element separation film, and the floating gate electrode and the element separation film can form a minimum volume. Therefore, the size of the NOR-type or NAND-type memory cells can be reduced. In this way, it is possible to achieve a high density of permanent memory devices that are compatible with miniaturization and high performance of home appliances. ‘(Please read the notes on the back before filling this page)
、1T -•t__ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29<7公釐） -12-、 1T-• t__ This paper size is applicable to China National Standard (CNS) A4 specification (210X29 < 7mm) -12-