3 7 7 9 t v\ ' f. d o c / Ο Ο 6 3 7 7 9 t v\ ' f. d o c / Ο Ο 6 經濟部中央標準局負工消f合作社印製 ___H~ 五、發明説明（/ ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種動態隨機存取記憶體電容器下電極的製造方 法。 在半導體積集度越來越大的趨勢下，使得半導體業界 不停地在發展新方法來製造出尺寸更小的元件，以應付次 微米技術的需求。以往，若要增加積體電路元件的密度， 必須設法減少每一結構的尺寸。就動態隨機存取記億體 (Dynamic Random Access Memory, DRAM)而言，爲了縮小 DRAM電容器所佔據的面積’必須縮小電容器電極的尺寸， 但同時也減少了電容器的儲存電荷量。 —般來說，在記憶體電容器上的儲存電荷量不可太 少，以達到記憶體資料可被正確讀寫的要求。所以若進一 步減少DRAM記億體電容器的尺寸時，電容器所儲存的電 荷量也跟著降低。而且爲了補充因電容器漏電而損耗掉的 電荷量，對電容器所做之週期性充電的頻率也會跟著增 加。這些都會降低DRAM的資料處理速度，所以在減少 DRAM電容器在半導體基底上所需面積的同時，如何至少 保持甚至增加DRAM儲存電容器的電容量成爲一個亟待解 決的問題。 在砂材表面生長半球型砂晶粒（hemispherical grain silicon, HSG-Si)即爲解決此問題的方法之一。利用此方法， 在電容器下電極的表面生長HSG-Si，在電容器電極和介電 層的材質以及兩電極之間距等條件不變之下，可增加電容 器的電容，使其約爲原先電容的兩倍大小。 3 本紙張尺度適用中國國家標皁（CNS ) A4说格（210X297公处） (誚先閱誚背而之注意事項再填寫本頁) .裝.3 7 7 9 tv \ 'f. Doc / Ο Ο 6 3 7 7 9 tv \' f. Doc / Ο Ο 6 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by a cooperative ___ H ~ V. Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a lower electrode of a dynamic random access memory capacitor. With the increasing trend of semiconductor accumulation, the semiconductor industry is constantly developing new methods to manufacture smaller components to meet the needs of sub-micron technology. In the past, to increase the density of integrated circuit components, efforts must be made to reduce the size of each structure. As far as Dynamic Random Access Memory (DRAM) is concerned, in order to reduce the area occupied by a DRAM capacitor, the size of the capacitor electrode must be reduced, but at the same time the amount of stored charge of the capacitor is also reduced. -In general, the amount of stored charge on the memory capacitor must not be too small to meet the requirement that the memory data can be read and written correctly. Therefore, if the size of the DRAM memory capacitor is further reduced, the amount of charge stored in the capacitor will also decrease. And in order to supplement the amount of charge lost due to capacitor leakage, the frequency of periodic charging of the capacitor will also increase. All of these will reduce the data processing speed of DRAM, so how to maintain or even increase the capacitance of DRAM storage capacitors while reducing the required area of DRAM capacitors on the semiconductor substrate has become an urgent problem to be solved. One way to solve this problem is to grow hemispherical grain silicon (HSG-Si) on the surface of the sand material. With this method, HSG-Si is grown on the surface of the lower electrode of the capacitor. Under the conditions that the material of the capacitor electrode and the dielectric layer and the distance between the two electrodes are not changed, the capacitance of the capacitor can be increased to about two times the original capacitance. Times the size. 3 This paper size applies to China National Standard Soap (CNS) A4 scale (210X297) (please read the precautions before filling this page).
*1T 3 779twf.doc/006 3 779twf.doc/006 經濟部中央標準扃貝工消费合作社印裝 - 圓 , II 圓 - » - -·.··私 ·_ —· A — —. . — 五、發明説明（）） 第1A〜1C圖是習知之DRAM電容器下電極的製造流 程剖面圖。請參照第1A圖，在基底11〇中形成源極/汲極 120，然後在基底110之上沈積一層介電層130。再利用微 影倉虫刻製程在介電層130中形成自卩點接觸窗（node contact) 開口 140，在節點接觸窗開口 140內，以低壓化學氣相沈 積法（Low Pressure Chemical Vapor Deposition, LPCVD)，在 約520 °C下，以矽甲烷（SiH4)爲氣源來沈積摻雜非晶矽 (amorphous silicon, oc-Si)層 150a 〇 —般來說，以LPCVD來沈積多晶砂（polysilicon)和非 晶矽的條件差不多。最大的差別爲沈積多晶矽所需的溫度 較高，約600 ~ 650 °C ;而沈積非晶矽所需的溫度較低， 約500〜550 °C左右。此乃因爲若沈積溫度較高，則分子 動能較大，在晶片表面將具有較大的移動性(mobility)，所 以較容易聚集結晶成較大的晶粒。* 1T 3 779twf.doc / 006 3 779twf.doc / 006 Printed by the Central Standard of the Ministry of Economic Affairs of the Bayer Consumer Cooperative-Round, II Round-»--·. · 私 · _ — · A — —.. — Five 2. Description of the Invention ()) FIGS. 1A to 1C are cross-sectional views of a manufacturing process of a conventional lower electrode of a DRAM capacitor. Referring to FIG. 1A, a source / drain 120 is formed in a substrate 110, and then a dielectric layer 130 is deposited on the substrate 110. A lithographic process is used to form a node contact opening 140 in the dielectric layer 130. In the node contact window opening 140, a Low Pressure Chemical Vapor Deposition (LPCVD) method is used. ), At about 520 ° C, using silicon methane (SiH4) as a gas source to deposit a doped amorphous silicon (oc-Si) layer 150a—in general, LPCVD is used to deposit polysilicon (polysilicon The conditions are similar to that of amorphous silicon. The biggest difference is that the temperature required to deposit polycrystalline silicon is higher, about 600 to 650 ° C; while the temperature required to deposit amorphous silicon is lower, about 500 to 550 ° C. This is because if the deposition temperature is higher, the molecular kinetic energy is larger, and the mobility on the wafer surface will be larger, so it is easier to aggregate and crystallize into larger crystal grains.
但是，爲了形成非晶矽來降低沈積溫度，卻使得沈積 速率大爲降低。例如在600 °C時，沈積速率有1〇〇 A/min 左右。但是在550 °C時，沈積速率降爲25 A/min左右。 若在520 °C時，沈積速率只剩下8 A/mm左右。而現今爲 了因應0.25 μπι以下製程的要求，元件的尺寸一再縮小， 使得DRAM電容器所能佔據的面積也一直降低。爲了增加 電容器的保面積，電容器只好往垂直方向發展，例如堆疊 (stack)電容器。在0.25 μιη以下的製程，電容器的節點高 度（node height)，如第1Α圖所所標示的ΝΗ，將會大於6000 人以上，使得沈積非晶矽層需要花費很長的時間。以520 °C 4 尺度適用中國國家標率（CNS ) Λ4規格（210X297公焓) ~ ~ I I私衣 訂 絲 (請先閱讀背面之注意事項再填寫本頁) 5779twr.d〇c/〇〇6 5779twr.d〇c/〇〇6 經濟部中央標芈局貝工消费合作社印製 ------- η1________________________________ 五、發明説明（彡） 下8 A/mm左右的沈積速率來沈積8000 Α厚的非晶矽來估 算’至少需要花費16小時的時間，產量實在太低了。而 如此長的沈積時間，使得先沈積的非晶矽有機會進行晶格 重排，重新結晶出第1A圖所標示的多晶矽160，將會影響 後續HSG-Si的生長。若想要完全避免多晶矽160的生長， 則可能沈積溫度得降到510。(：以下，將會使得沈積速率更 '丨曼 '產量更低，造成很大的困擾。 爲了要提高非晶矽層的導電度，因此另外一個伴隨著 沈積非晶矽的問題是離子摻雜的問題。離子摻雜的方式一 般有三種，第一是離子植入法，第二是利用熱擴散將摻質 趨入(drive)法，第三是和沈積反應同時進行(in situ)法。若 選擇第三種方法，則只有利用B2H6爲摻源的情況下，B2H6 的濃度越高，非晶矽的沈積速率才會越快。若選擇ph3或 AsH3爲摻源，則濃度越高，非晶矽的沈積速率越慢，所需 的沈積時間也就更長，產量也就會更低。其原因是b2h6 在晶片表面會分解形成不穩定的BH3自由基(free radical)， 加速Sm4的分解反應，以利沈積反應的進行。而PH3* AsH3 則是強烈地吸附在晶片表面，抑止SiH4的分解反應，使得 沈積反應速率更慢。 請參照第1B圖，定義非晶矽層150a，形成下電極 150b ’其部份表面積165被多晶矽160所覆蓋。接著請參 照第丨C圖，進行播晶種(seeding)以及在55〇〜570 °C下之 高真空回火（annealing)的步驟，使下電極150b的表面選擇 性的生長出HSG-Si 170，形成表面積更大的下電極150c。 5 (請先閲讀背面之注意事項再填寫本頁) .裝- 訂 絲 \紙張尺度適則(CNS) Λ4· ( 2iqx297公發) 3779t\vt'.doc/006 3779t\vt'.doc/006 經濟部中央標準局貝工消费合作社印聚 ΗΊ 五、發明説明（士） 但是多晶矽160的表面165卻無法長出HSG-Si，此乃因爲 HSG-Si是非晶矽中的矽原子藉由晶種以及回火的高溫以進 行晶格重排使其整體能量降低的結果。而多晶矽本身已經 具有一定的結晶度，能量態本來就較穩定，所以不會有非 晶矽的晶格重排現象，也就不會有HSG-Si的產生了。如 此一來，下電極150c所增加的表面積將會比預計的還要 小許多，使得電容器可儲存的電荷量也跟著減少了。而且 回火步驟的溫度（550〜570 °C)比沈積時的溫度(500 ~ 550。〇 還高，因此在回火時，非晶矽可以繼續進行再結晶來形成 多晶矽，則可生長出HSG-Si的α-Si表面積又會更少了。 因此本發明的目的就是在提供一種DRAM電容器下電 極的製造方法，以改善上述習知的缺點。 根據本發明之上述目的，提出一種DRAM電容器下電 極的製造方法。此方法以多晶矽來取代非晶矽爲下電極的 材質，因爲多晶矽的沈積溫度較高，所以可以提高沈積速 率，縮短沈積時間。再利用離子植入的方式使下電極的表 層多晶矽結構被破壞，以形成非晶矽來生長半球型矽晶 粒，完成下電極的製作。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A〜1C圖是習知之DRAM電容器下電極的製造流 程剖面圖；以及 6 (請先閲讀背而之注意事項再填«?本頁) .裝- 、-β 線 本紙張尺度適用中國國家標準（CNS ) A4現格"("210X297公垃) 37 7 9lwr<lt)c/0()6However, in order to reduce the deposition temperature in order to form amorphous silicon, the deposition rate is greatly reduced. For example, at 600 ° C, the deposition rate is about 100 A / min. But at 550 ° C, the deposition rate drops to about 25 A / min. At 520 ° C, the deposition rate is only about 8 A / mm. Now, in order to meet the requirements of processes below 0.25 μm, the size of components has been repeatedly reduced, so that the area occupied by DRAM capacitors has also been reduced. In order to increase the area of the capacitor, the capacitor has to be developed in a vertical direction, such as a stack capacitor. In the process below 0.25 μm, the node height of the capacitor, as shown in Figure 1A, will be greater than 6000 people, making it necessary to deposit an amorphous silicon layer for a long time. Applicable to China National Standards (CNS) Λ4 specification (210X297 enthalpy) at 520 ° C 4 scale ~ ~ II private stapler (please read the precautions on the back before filling this page) 5779twr.d〇c / 〇〇6 5779twr.d〇c / 〇〇6 Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ------------ η1 ________________________________ V. Description of the invention (彡) Deposition rate of about 8 A / mm to deposit 8000 A thick It takes at least 16 hours to estimate the amorphous silicon, and the yield is really too low. Such a long deposition time allows the previously deposited amorphous silicon to have the opportunity to undergo lattice rearrangement and recrystallize the polycrystalline silicon 160 as shown in Figure 1A, which will affect the subsequent growth of HSG-Si. If the growth of polycrystalline silicon 160 is to be completely avoided, the deposition temperature may be reduced to 510. (: The following will make the deposition rate more 'man' and lower the yield, causing a lot of trouble. In order to improve the conductivity of the amorphous silicon layer, another problem accompanying the deposition of amorphous silicon is ion doping There are generally three types of ion doping methods. The first is the ion implantation method, the second is the dopant drive method using thermal diffusion, and the third is the in situ method at the same time as the deposition reaction. If the third method is selected, only when B2H6 is used as the doping source, the higher the concentration of B2H6, the faster the deposition rate of the amorphous silicon. If ph3 or AsH3 is used as the doping source, the higher the concentration, the The slower the deposition rate of crystalline silicon, the longer the deposition time and the lower the yield. The reason is that b2h6 will decompose on the wafer surface to form unstable BH3 free radicals, which will accelerate the decomposition of Sm4. The reaction is to facilitate the deposition reaction. PH3 * AsH3 is strongly adsorbed on the wafer surface, which suppresses the decomposition reaction of SiH4, making the deposition reaction rate slower. Please refer to Figure 1B, define the amorphous silicon layer 150a, and form the following Electrode 150b 'its part The area 165 is covered by polycrystalline silicon 160. Next, referring to Figure 丨 C, the steps of seeding and high vacuum annealing at 55 ~ 570 ° C are performed to select the surface of the lower electrode 150b. HSG-Si 170 grows by nature, forming a lower electrode 150c with a larger surface area. 5 (Please read the precautions on the back before filling out this page). Binding-Staples \ Paper Size Appropriate (CNS) Λ4 · (2iqx297 (Issued) 3779t \ vt'.doc / 006 3779t \ vt'.doc / 006 Printed by Jumei Group, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of Invention (Justice) However, the surface 165 of polycrystalline silicon 160 cannot grow HSG-Si This is because HSG-Si is the result of reducing the overall energy of the silicon atoms in the amorphous silicon by seeding and tempering at high temperatures to conduct lattice rearrangement. Polycrystalline silicon itself already has a certain degree of crystallinity, and the energy state was originally It is more stable, so there will be no lattice rearrangement of amorphous silicon and no HSG-Si. In this way, the increased surface area of the lower electrode 150c will be much smaller than expected , So that the amount of charge that can be stored in the capacitor also decreases. Moreover, the temperature of the tempering step (550 ~ 570 ° C) is higher than the temperature during deposition (500 ~ 550 °). Therefore, during tempering, amorphous silicon can continue to recrystallize to form polycrystalline silicon, and HSG can grow. The α-Si surface area of -Si will be smaller again. Therefore, the object of the present invention is to provide a method for manufacturing a lower electrode of a DRAM capacitor, so as to improve the conventional shortcomings. According to the above object of the present invention, a DRAM capacitor is proposed. Method for manufacturing electrodes. This method uses polycrystalline silicon instead of amorphous silicon as the material of the lower electrode. Because polycrystalline silicon has a higher deposition temperature, it can increase the deposition rate and shorten the deposition time. Then, the surface polycrystalline silicon structure of the lower electrode is destroyed by ion implantation to form amorphous silicon to grow hemispherical silicon grains, and the fabrication of the lower electrode is completed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Section 1A ~ Figure 1C is a cross-sectional view of the manufacturing process of the lower electrode of a conventional DRAM capacitor; and 6 (Please read the precautions on the back before filling in the «? Page). The dimensions of the paper are applicable to Chinese national standards (CNS) A4 is now " (" 210X297 public garbage) 37 7 9lwr < lt) c / 0 () 6
經濟部中央標準局貝工消费合作社印繁 五、發明説明（< ) 第2A〜2D圖是依據本發明之一較佳實施例的一種 DRAM電容器下電極的製造流程剖面圖。 圖式之標記說明： 110、210 :基底 120、220 :源極/汲極 130、230 :介電層 140、240 :節點接觸窗開口 150a、252a、252b :非晶矽層 150b、150c、250b、280a、280b :下電極 160 :多晶石夕 165 :多晶敢的表面 170、290 :半球型矽晶粒 250a、250c :多晶矽層 260 :導電插塞 270 :摻雜離子 實施例 請參照第2A〜2D圖，其繪示依照本發明一較佳實施 例的一種DRAM電容器下電極的製造流程剖面圖。 請參照第2A圖，在基底210中，例如以離子植入法 形成源極/汲極220。然後在基底210之上形成一層介電層 230，其材質例如可爲二氧化矽，其形成的方法，例如使 用以31(0(：出5)4爲氣源的LPCVD來沈積之。再利用微影蝕 刻製程在介電層230中形成節點接觸窗開口 240。在節點 接觸窗開口 240內和介電層230之上，例如以LPCVD來 7 本紙张尺度適Λ中國國家標準（CNS ) A4规梏（210X 297公处) (請先閱讀背而之注意事項再填寫本頁) 、τYin Fan, Shelley Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the Invention (2) ~ 2D are cross-sectional views of the manufacturing process of a lower electrode of a DRAM capacitor according to a preferred embodiment of the present invention. Symbols of the drawings: 110, 210: substrate 120, 220: source / drain 130, 230: dielectric layer 140, 240: node contact window openings 150a, 252a, 252b: amorphous silicon layers 150b, 150c, 250b 280a, 280b: lower electrode 160: polycrystalline stone 165: polycrystalline surface 170, 290: hemispherical silicon grain 250a, 250c: polycrystalline silicon layer 260: conductive plug 270: doped ion 2A to 2D are cross-sectional views illustrating a manufacturing process of a lower electrode of a DRAM capacitor according to a preferred embodiment of the present invention. Referring to FIG. 2A, a source / drain 220 is formed in the substrate 210 by, for example, an ion implantation method. Then, a dielectric layer 230 is formed on the substrate 210. The material may be, for example, silicon dioxide, and the formation method is, for example, LPCVD using 31 (0 (: out 5) 4 as a gas source to deposit it. Reuse The lithographic etching process forms a node contact window opening 240 in the dielectric layer 230. Within the node contact window opening 240 and above the dielectric layer 230, for example, LPCVD is used. 7 Paper standards are compliant with Chinese National Standard (CNS) A4 regulations.梏 （210X 297 office） (Please read the precautions before filling in this page), τ
經濟部中央標隼局員工消費合作社印製 3 779iwl'.d〇c/U〇0 Λ7 ^____— — W ____ 五、發明说明（6) 沈積形成導電插塞260和摻雜多晶矽層250a ’其主要沈積 氣源例如爲SlH4。 此時因爲要沈積的是多晶砂而不是非晶砂，若沈積是 在600 的溫度下’沈積速率有100 A/min時’以同樣要 沈積8000 A厚的多晶矽來估算，只需1.33小時就可完成 此步驟。和原先沈積同樣厚度的非晶矽所需之至少16小 時比起來，產量實在提昇不少。 另外用摻雜多晶矽取代摻雜非晶矽所附加的好處是， 摻雜多晶矽的導電度較摻雜非晶矽的爲高。一般在元件尺 寸越做越小的情況下’若元件的材質不變，通常元件的電 阻也會隨著電性通路的截面積的減少而增加，則元件的操 作速率也就隨著變慢。在此以摻雜多晶矽取代摻雜非晶 矽，提昇導電插塞260的導電度，如此才不會因爲元件的 尺寸減少，而使得元件的操作速率一下子慢得不可接受。 請參照第2B圖，定義多晶矽層250a，形成下電極 250b。請參照第2C圖，進行離子植入的步驟，使由摻雜 多晶矽所構成之下電極250b之表面部位因受到摻雜離子 270之植入而破壞多晶矽的結構，形成非晶矽層252a。則 下電極280a變成由內部的多晶砂250c和表層的非晶矽252a 所組成。其可用的摻雜離子270以及其植入條件，例如包 括氬(Ar) ’其植入能量爲150〜200 KeV，植入濃度約爲3 xio14 atom/cm2 ;或磷(P)，其植入能量爲 250 〜300 KeV， 植入濃度約爲5X1014 atom/cm2 ;或砷(As)，其植入能量爲 180〜230 KeV，植入濃度約爲1014 atom/cm2 ;還有氮(N)、 8 (請先間讀背面之注意事項再填寫本頁) -裝. --° 本紙張尺度適用中國國家標準（CNS ) Λ4規格（21(ΚΚ297ϋ " M19[w\'\ I /002 項87丨丨67X3號說明雷修ί]-: Α7 Β7 修正曰期 修正 二κ女 經濟部智慧財產局員工消费合作社印製 五、發明說明（"） 銻（Sb)也可以。若植入的離子爲磷、砷和銻，還可減少下 電極表層的電阻，又加上下電極的表層材質已經轉成非晶 矽，所以可增加電荷分佈的均勻性，減少放電的機率，並 進一步增加元件的操作速率。 因爲摻雜離子270在植入之時具有高動能，當和晶格 原子相撞時，可藉其所具有之動能來破壞摻雜多晶矽表面 部位之晶格排列，而使得受到離子所影響之表面部位會由 原有具結晶性之多晶矽250b轉換爲非晶矽252a，而其餘 未受離子所影響之部位則仍爲摻雜多晶矽250c。 請參照第2D圖，進行播晶種以及在550〜570 °C下之 高真空回火的步驟，使下電極280a之表層非晶矽252a的 表面選擇性地生長出HSG-Si 280,變成表面積約爲原來兩 倍大的下電極280b。此時下電極280b由內部的多晶矽250c 和表面長出HSG-Si 290的表層非晶矽252b所組成。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 第一、因爲下電極的材質用多晶矽來取代非晶矽，所 以下電極的製作時間可大爲縮短，使得產量可以大幅提 昇。 第二、因爲下電極的材質用多晶矽來取代非晶矽，所 .以導電插塞的電阻較低，可增加元件的操作速度。 第三、利用離子植入的方式使下電極表層整個轉成非 晶矽，因此在播晶種和高真空回火時，矽原子可以更有效 地在下電極的表面移動，使得HSG-Si的生長更有效率也 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —— — — — — — — — — — I. - I I I (請先閱讀背面之注意事項再填寫本頁) 訂---------f. 3 7 79twf.docΛ)06 Λ? ΪΓ 五、發明説明（》） 更均勻。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ---------- ------丁------ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 I 0 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公位）Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 3 779iwl'.d〇c / U〇0 Λ7 ^ ____ — — W ____ V. Description of the invention (6) The conductive plug 260 is deposited and a doped polycrystalline silicon layer 250a is formed. The main deposition gas source is, for example, SlH4. At this time, because polycrystalline sand is to be deposited instead of amorphous sand, if the deposition is at a temperature of 600 'at a deposition rate of 100 A / min', it is estimated that 8000 A thick polycrystalline silicon is also deposited, which only takes 1.33 hours. This step can be completed. Compared with the original deposition of amorphous silicon at the same thickness of at least 16 hours, the yield is really improved. In addition, the advantage of replacing doped amorphous silicon with doped polycrystalline silicon is that the conductivity of doped polycrystalline silicon is higher than that of doped amorphous silicon. Generally, when the component size is getting smaller, if the material of the component is unchanged, the resistance of the component will generally increase with the reduction of the cross-sectional area of the electrical path, and the operation speed of the component will also slow down. Here, doped polycrystalline silicon is used instead of doped amorphous silicon to increase the conductivity of the conductive plug 260 so that the operation speed of the device is unacceptably slow because the size of the device is reduced. Referring to FIG. 2B, a polycrystalline silicon layer 250a is defined to form a lower electrode 250b. Referring to FIG. 2C, an ion implantation step is performed, so that the surface portion of the lower electrode 250b composed of doped polycrystalline silicon is implanted with doped ions 270 to destroy the structure of the polycrystalline silicon to form an amorphous silicon layer 252a. Then, the lower electrode 280a is composed of the polycrystalline sand 250c inside and the amorphous silicon 252a on the surface layer. Its available doped ion 270 and its implantation conditions include, for example, argon (Ar), its implantation energy is 150 ~ 200 KeV, and its implantation concentration is about 3 xio14 atom / cm2; or its phosphorus (P), its implantation The energy is 250 ~ 300 KeV, and the implantation concentration is about 5X1014 atom / cm2; or arsenic (As), the implantation energy is 180 ~ 230 KeV, and the implantation concentration is about 1014 atom / cm2; and nitrogen (N), 8 (Please read the precautions on the back before filling out this page) -Install.-° This paper size applies Chinese National Standard (CNS) Λ4 specification (21 (ΚΚ297ϋ " M19 [w \ '\ I / 002 item 87)丨 丨 67X3 Explanation Lei Xiu]-: Α7 Β7 Amendment Date Amendment II κ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People's Republic of China 5. Inventory (") Antimony (Sb) can also be used. If implanted ions For phosphorus, arsenic and antimony, the resistance of the lower electrode surface layer can also be reduced, and the surface material of the lower electrode has been converted to amorphous silicon, so it can increase the uniformity of charge distribution, reduce the probability of discharge, and further increase the operation of the component Because doped ion 270 has high kinetic energy at the time of implantation, Its kinetic energy destroys the lattice arrangement of the surface area of the doped polycrystalline silicon, so that the surface area affected by the ions will be converted from the original crystalline polycrystalline silicon 250b to the amorphous silicon 252a, and the rest is not affected by the ions. The part is still doped with polycrystalline silicon 250c. Please refer to Figure 2D to perform seeding and high vacuum tempering at 550 ~ 570 ° C to make the surface of the lower layer 280a amorphous silicon 252a selective. HSG-Si 280 grows on the ground, and becomes a lower electrode 280b with a surface area about twice as large as the original surface. At this time, the lower electrode 280b is composed of polycrystalline silicon 250c inside and HSG-Si 290 surface amorphous silicon 252b growing on the surface. It can be known from the preferred embodiments of the present invention that the application of the present invention has the following advantages. First, because the material of the lower electrode is replaced by polycrystalline silicon instead of amorphous silicon, the manufacturing time of the following electrode can be greatly shortened, so that the yield can be greatly improved. Because the material of the lower electrode is polycrystalline silicon instead of amorphous silicon, the resistance of the conductive plug is low, which can increase the operating speed of the component. Third, the ion implantation method is used. The surface layer of the electrode is completely transformed into amorphous silicon, so when seeding and high vacuum tempering, silicon atoms can move more effectively on the surface of the lower electrode, making the growth of HSG-Si more efficient. Standard (CNS) A4 specification (210 X 297 mm) —— — — — — — — — — — — I.-III (Please read the notes on the back before filling this page) Order -------- -f. 3 7 79twf.docΛ) 06 Λ? ΪΓ 5. Description of the invention (") More uniform. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---------- ------ Ding ------ (Please read the notes on the back before filling out this page) Printed by I 0 copies Paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm)