3 739twf.doc/006 3 739twf.doc/006 經濟部中央榡準局負工消费合作社印裝 j、發明説明（/) 本發明是有關於一種半導體元件的製造方法，且特別 裊有關於一種動態隨機存取記憶體電容器下電極的製造方 法。 在半導體積集度越來越大的趨勢下，使得半導體業界 不停地在發展新方法來製造出尺寸更小的元件，以應付次 微米技術的需求。以往，若要增加積體電路元件的密度， 必須設法減少每一結構的尺寸。就動態隨機存取記億體 (Dynamic Random Access Memory, DRAM)而言，爲了縮小 D R A Μ電谷器所佔據的面積，必須縮小電容器電極的尺寸， 但同時也減少了電谷器的儲存電荷量。 一般來說’在記憶體電容器上的儲存電荷量不可太 少，以達到記憶體資料可被正確讀寫的要求。所以若進一 歩減少DRAM記憶體電容器的尺寸時，電容器所儲存的電 荷量也跟著降低。而且爲了補充因電容器漏電而損耗掉的 電荷量，對電容器所做之週期性充電的頻率也會跟著增 加。這些都會降低DRAM的資料處理速度，所以在減少 DRAM電容器在半導體基底上所需面積的同時，如何至少 保持甚至增加DRAM儲存電容器的電容量成爲一個亟待解 決的問題。 在砂材表面生長半球型砂晶粒（hemispherical grain sUicon, HSG-Si)即爲解決此問題的方法之一。利用此方法， 在電容器下電極的表面生長HSG-Si，在電容器電極和介電 層的材質以及兩電極之間距等條件不變之下，可增加電容 器的電容，使其約爲原先電容的兩倍大小。 3 ^氏张尺ϋ用中國國家標準(CNS ) 格（2I〇x297公猪) ' (請先閱讀背而之注意事項再填寫本頁) -裝- 、-° 線 3 739twf.doc/006 3 739twf.doc/006 經濟部中央標準局員工消费合作社印製 ____ ir 五、發明説明（之） 第1A〜1C圖是習知之DRAM電容器下電極的製造流 程剖面圖。請參照第1A圖’在基底10中形成源極/汲極2〇， 然後在基底10之上沈積一層二氧化矽層3〇。再利用微影 蝕刻製程在二氧化矽層30中形成節點接觸窗(node conta⑴ 開口 40，在節點接觸窗開口 40內，以低壓化學氣相沈積 法（Low Pressure Chemical Vapor Deposition, LPCVD)沈積摻 雜多晶矽’形成節點接觸窗50。接著，再利用LPCVD， 在約530 °C下，以矽甲烷(SiH4)爲氣源來沈積摻雜非晶矽 (amorphous silicon, α-Si)層 60a。 一般來說’以LPCVD來沈積多晶矽(p〇lysiilcon#D非 晶矽的條件差不多。最大的差別爲沈積多晶矽所需的溫度 較高’約600〜650 °C ;而沈積非晶矽所需的溫度較低， 約500〜550 °C左右。此乃因爲若沈積溫度較高，則分子 動能較大，在晶片表面將具有較大的移動性(moMUty)，所 以較容易聚集結晶成較大的晶粒。 但是，爲了形成非晶矽來降低沈積溫度，卻使得沈積 速率大爲降低。例如在600 °C時，沈積速率有100 A/min 左右。但是在550 °C時，沈積速率降爲25 A/min左右。 若在530 °C時，沈積速率只剩下1〇 A/min左右。而現今 爲了因應〇·25 μπι以下製程的要求，元件的尺寸一再縮小， 使得DRAM電容器所能佔據的面積也一直降低。爲了增加 電容器的保面積，電容器只好往垂直方向發展，例如堆疊 (stack)電容器。在0.25 μιη以下的製程，電容器的節點高 度（node height)，如第1Α圖所所標示的ΝΗ，將會大於6000 4 本紙張尺度中國國家標^ ( CNS > Λ4規^ ( - (請先閱讀背而之注意事項再填寫本頁) 裝· 線 3739twf.doc/0063 739twf.doc / 006 3 739twf.doc / 006 Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs j. Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a development Method for manufacturing lower electrode of random access memory capacitor. With the increasing trend of semiconductor accumulation, the semiconductor industry is constantly developing new methods to manufacture smaller components to meet the needs of sub-micron technology. In the past, to increase the density of integrated circuit components, efforts must be made to reduce the size of each structure. In terms of dynamic random access memory (DRAM), in order to reduce the area occupied by the DRA M valley device, the size of the capacitor electrode must be reduced, but at the same time the amount of stored charge of the valley device is also reduced. . Generally, the amount of stored charge on the memory capacitor should not be too small to meet the requirement that the memory data can be read and written correctly. Therefore, if the size of the DRAM memory capacitor is further reduced, the amount of charge stored in the capacitor also decreases. And in order to supplement the amount of charge lost due to capacitor leakage, the frequency of periodic charging of the capacitor will also increase. All of these will reduce the data processing speed of DRAM, so how to maintain or even increase the capacitance of DRAM storage capacitors while reducing the required area of DRAM capacitors on the semiconductor substrate has become an urgent problem to be solved. One way to solve this problem is to grow hemispherical grain sUicon (HSG-Si) on the surface of the sand material. With this method, HSG-Si is grown on the surface of the lower electrode of the capacitor. Under the conditions that the material of the capacitor electrode and the dielectric layer and the distance between the two electrodes are not changed, the capacitance of the capacitor can be increased to about two times the original capacitance. Times the size. 3 ^ Zhang Zhangye uses the Chinese National Standard (CNS) grid (2I〇x297 boar) '' (Please read the precautions before filling this page) -install- 、-° line 3 739twf.doc / 006 3 739twf.doc / 006 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs ____ ir 5. Description of the Invention (Part 1) Figures 1A to 1C are cross-sectional views of the conventional manufacturing process of the lower electrode of a DRAM capacitor. Referring to FIG. 1A, a source / drain 20 is formed in the substrate 10, and then a silicon dioxide layer 30 is deposited on the substrate 10. Then, a lithography etching process is used to form a node contact window (node conta 开口 opening 40) in the silicon dioxide layer 30. In the node contact window opening 40, doping is deposited by Low Pressure Chemical Vapor Deposition (LPCVD). Polycrystalline silicon 'forms a node contact window 50. Next, LPCVD is used to deposit a doped amorphous silicon (α-Si) layer 60a at about 530 ° C using silicon methane (SiH4) as a gas source. Say 'The conditions for the deposition of polycrystalline silicon (LP0) by LPCVD are similar. The biggest difference is that the temperature required to deposit polycrystalline silicon is higher', about 600 ~ 650 ° C; and the temperature required to deposit amorphous silicon is higher than Low, about 500 ~ 550 ° C. This is because if the deposition temperature is high, the molecular kinetic energy is large, and there will be a large mobility (moMUty) on the wafer surface, so it is easier to aggregate and crystallize into larger grains. However, in order to reduce the deposition temperature in order to form amorphous silicon, the deposition rate is greatly reduced. For example, at 600 ° C, the deposition rate is about 100 A / min. However, at 550 ° C, the deposition rate is reduced to 25 A / min. At 530 ° C, the deposition rate is only about 10 A / min. However, in order to meet the requirements of the process below 0.25 μm, the size of components has been shrinking again and again, so that the area that DRAM capacitors can occupy has also been reduced. To increase the capacitor's guaranteed area, the capacitor has to develop in a vertical direction, such as a stack capacitor. For processes below 0.25 μιη, the node height of the capacitor, as shown in Figure 1A, will be greater than 6000. 4 This paper is a Chinese national standard ^ (CNS > Λ4 Regulations ^ (-(Please read the precautions on the back before filling out this page)) Thread · 3739twf.doc / 006
經濟部中央搮準爲員工消费合作社印裝 五、發明説明（3 ) A以上，使得沈積非晶矽層需要花費很長的時間。以530 T 下10 A/min左右的沈積速率來估算，至少需要花費10小 時的時間，產量實在太低了。而如此長的沈積時間，使得 先沈積的非晶砂有機會進行晶格重排，重新結晶出第1A 圖所標示的多晶矽70，將會影響後續HSG-Si的生長。 爲了要提高非晶矽層的導電度，因此另外一個伴隨著 沈積非晶矽的問題是離子摻雜的問題。離子摻雜的方式一 般有三種，第一是離子植入法，第二是利用熱擴散將摻質 趨入(drive)法，第三是和沈積反應同時進行(in situ)法。若 選擇第三種方法，則只有利用b2h6爲摻源的情況下，b2h6 的濃度越高，非晶矽的沈積速率才會越快。若選擇ph3或 AsH3爲摻源，則濃度越高，非晶矽的沈積速率越慢，所需 的沈積時間也就更長，產量也就會更低。其原因是b2h6 在晶片表面會分解形成不穩定的BH3自由基(free radical)， 加速SiH4的分解反應，以利沈積反應的進行。而PH3或AsH3 則是強烈地吸附在晶片表面，抑止SiH4的分解反應，使得 沈積反應速率更慢。 請參照第1B圖，定義非晶矽層60a，形成下電極60b， 其部份表面積75被多晶矽70所覆蓋。接著請參照第1C 圖，進行播晶種(seeding)以及在550〜570 °C下之高真空 回火（annealing)的步驟，使下電極60b的表面選擇性的生 長出HSG-Si 80，形成表面積更大的下電極60c。但是多晶 矽70的表面75卻無法長出HSG-Si，此乃因爲HSG-Si是 非晶砂中的砍原子錯由晶種以及回火的闻溫以進彳了晶格重 (請先閱讀背面之注意事項再填寫本I) 裝· ,11 線 本紙张尺度適用中國國家標隼（CNS ) A4規格（210X 297公你） 3 739t\vf.doc/006 3 739t\vf.doc/006 經濟部中央標準局Μ工消费合作社印製 五、發明説明（芋） 排使其整體能量降低的結果。而多晶矽本身已經具有一定 的結晶度，能量態本來就較穩定，所以不會有非晶矽的晶 格重排現象，也就不會有HSG-Sl的產生了。如此一來， 下電極60c所增加的表面積將會比預計的還要小許多，使 得電容器可儲存的電荷量也跟著減少了。而且回火步驟的 溫度(550〜570 °C)比沈積時的溫度(500 ~ 550。〇還高，因 此在回火時，非晶矽可以繼續進行再結晶來形成多晶矽， 則可生長出HSG-Si的〇t-Si表面積又會更少了。 因此本發明的目的就是在提供一種DRAM電容器下電 極的製造方法，以改善上述習知的缺點，使沈積非晶矽所 需的時間縮短，以避免部份非晶矽再結晶出多晶矽。 根據本發明之上述目的，提出一種DRAM電容器下電 極的製造方法。此方法利用電漿化學氣相沈積法（Plasma Enhanced Chemical Vapor Deposition，PECVD)來沈積非晶 矽，以提高非晶矽的沈積速率和摻雜效率。使得沈積DRAM 電容器下電極之非晶矽層所需的時間被大幅縮短，以避免 非晶矽再結晶出多晶矽。如此可使整個下電極表面皆長出 HSG-Si，以增加下電極的表面積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A〜1C圖是習知之DRAM電容器下電極的製造流 程剖面圖；以及 6 (諳先閱讀背面之注意事項再填寫本頁) •裝. 、-° 線 本紙張尺度通用中國國家標準（CNS )如规格（210X2^7公及） 3739twf.doc/006 經濟部中央標準局只工消费合作社印製 ΑΊ Η - 五、發明説明（f) 桌2A〜；2C圖是依據本發明之一較佳實施例的一種 DRAM電容器下電極的製造流程剖面圖。 圖式之標記說明： 10、110 :基底 20、120 :源極/汲極 30、130 •二氧化矽層 40、140 :節點接觸窗開口 50、150 :節點接觸窗 60a、160a :非晶石夕層 60b、60c、i6〇b、160c :下電極 70:多晶矽 7 5 :多晶砂的表面 80、180 :半球型矽晶粒 實施例 請參照第2A〜2C圖，其繪示依照本發明一較佳實施 例的一種DRAM電容器下電極的製造流程剖面圖。 請參照第2A圖，在基底11〇中，例如以離子植入法 形成源極/汲極120。然後在基底U0之上形成一層二氧化 矽層130 ’其形成的方法，例如使用以Si(〇C2H5)4爲氣源 的LPCVD來沈積之。再利用微影蝕刻製程在二氧化矽層130 中形成節點接觸窗開口 140,在節點接觸窗開口 140內， 例如以LPCVD沈積摻雜多晶矽來塡滿節點接觸窗開口 M0，以形成節點接觸窗150。 接著，利用PECVD的方式來沈積摻雜非晶矽層i6〇a。 7 本紙張尺度適用中國國家標隼（CNS ) Λ4坭格（210X297公兑） (請先閱讀背而之注意事項與试寫本頁) .裝. 線 3739twf.doc/006 Η"___ ___ 五、發明説明（6) 在此PECVD所用的主要氣源爲矽烷類(sUane，SixHy)化合 物，其攜帶氣體（carder gas)可爲氫氣（H2)、氦氣（He)或氬 氣(Αι.)。PECVD之沈積反應所需的溫物只要在400 °C以下 即可，其沈積速率又在約1000 A/min以上，而且非晶砍所 需的摻質可以在沈積反應過程中同時摻入，沒有在LPCVD 中所碰到的沈積速率降低之問.題。在表一中整理出用 LPCVD和PECVD沈積非晶矽層的參數以及性質的比較。 --:--:·-----^-- (請先間讀背面之注意事項再填ΪΪΤ本頁) 線 表一 LPCVD PECVD 沈積溫度 500 ~ 550 °C 400。(：以下 沈積速率 〜10 A/min (〜530 oC) ^ 1000 A/min 主要氣源 矽甲烷(SiH4) 矽烷類(SixHv) 同時進行摻 雜的接受力 低 闻 摻雜效率 低 經濟部中央標準局員工消费合作社印製 LPCVD係利用晶片所傳遞的高溫，在晶片表面分解作 爲沈積氣源的氣體分子並同時進行沈積反應’所以所需的 溫度較高。但在沈積非晶矽時’又怕溫度太高會形成多晶 矽，造成氣體分子的分解效率不好’所以沈積速率十分慢° 而PECVD係先在電漿中將作爲沈積氣源的氣體分子先分 解掉，然後被分解掉的氣體分子再撞擊到晶片表面而在晶 片表面沈積。所以PECVD分解分子的效率較好’沈積速 率較快，又加上沈積所需溫度較低’可避免非晶砂再結晶 8 i紙张财關㉞準(CNS ) Λ4規格（210X297'»^ )The Central Ministry of Economic Affairs of the People's Republic of China has printed for the consumer consumer cooperatives. 5. Description of the invention (3) Above A, it takes a long time to deposit the amorphous silicon layer. Estimated at a deposition rate of about 10 A / min at 530 T, it takes at least 10 hours and the yield is too low. With such a long deposition time, the previously deposited amorphous sand has the opportunity to undergo lattice rearrangement and recrystallize the polycrystalline silicon 70 indicated in Figure 1A, which will affect the subsequent growth of HSG-Si. In order to improve the conductivity of the amorphous silicon layer, another problem accompanying the deposition of amorphous silicon is the problem of ion doping. There are generally three types of ion doping. The first is the ion implantation method, the second is the dopant drive method using thermal diffusion, and the third is the in situ method with the deposition reaction. If the third method is selected, only when b2h6 is used as the doping source, the higher the concentration of b2h6, the faster the deposition rate of amorphous silicon will be. If ph3 or AsH3 is selected as the doping source, the higher the concentration, the slower the deposition rate of amorphous silicon, the longer the deposition time, and the lower the yield. The reason is that b2h6 will decompose on the wafer surface to form unstable BH3 radicals (free radicals), which will accelerate the decomposition reaction of SiH4 to facilitate the deposition reaction. However, PH3 or AsH3 is strongly adsorbed on the wafer surface, inhibiting the decomposition reaction of SiH4, and making the deposition reaction rate slower. Referring to FIG. 1B, the amorphous silicon layer 60a is defined to form a lower electrode 60b, and a part of the surface area 75 is covered by the polycrystalline silicon 70. Next, referring to Figure 1C, seeding and high vacuum annealing at 550 to 570 ° C are performed to selectively grow HSG-Si 80 on the surface of the lower electrode 60b to form The lower electrode 60c has a larger surface area. However, HSG-Si cannot be grown on the surface 75 of the polycrystalline silicon 70. This is because HSG-Si is an atomic cut in amorphous sand. The seed weight and tempering temperature have entered the lattice weight (please read the back Note: Please fill in this item again. I) The size of the 11-line paper is applicable to China National Standard (CNS) A4 (210X 297). 3 739t \ vf.doc / 006 3 739t \ vf.doc / 006 Central Ministry of Economic Affairs Printed by the Bureau of Standards and Industry and Consumer Cooperatives V. Invention Description (Taro) The result of reducing its overall energy. Polycrystalline silicon itself already has a certain degree of crystallinity, and the energy state is relatively stable, so there will be no lattice rearrangement of amorphous silicon, and no HSG-Sl will be generated. As a result, the increased surface area of the lower electrode 60c will be much smaller than expected, so that the amount of charge that can be stored in the capacitor also decreases. In addition, the temperature of the tempering step (550 ~ 570 ° C) is higher than the temperature during deposition (500 ~ 550 °). Therefore, during tempering, amorphous silicon can continue to recrystallize to form polycrystalline silicon, and HSG can grow. 〇t-Si surface area of -Si will be smaller again. Therefore, the object of the present invention is to provide a method for manufacturing a lower electrode of a DRAM capacitor, in order to improve the conventional shortcomings described above, and shorten the time required to deposit amorphous silicon. To avoid recrystallizing a part of amorphous silicon, polycrystalline silicon is proposed. According to the above object of the present invention, a method for manufacturing a lower electrode of a DRAM capacitor is proposed. This method uses Plasma Enhanced Chemical Vapor Deposition (PECVD) to deposit Amorphous silicon to increase the deposition rate and doping efficiency of amorphous silicon. The time required to deposit the amorphous silicon layer of the lower electrode of a DRAM capacitor is greatly reduced to avoid the recrystallization of amorphous silicon from polycrystalline silicon. HSG-Si is grown on the surface of the lower electrode to increase the surface area of the lower electrode. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following specific examples are provided. The preferred embodiment and the accompanying drawings are described in detail as follows: Brief description of the drawings: Figures 1A to 1C are cross-sectional views of the manufacturing process of the conventional lower electrode of a DRAM capacitor; and 6 (谙 Read the note on the back first Please fill in this page again for matters) • Packing.,-° Threaded paper sizes are common Chinese National Standards (CNS) such as specifications (210X2 ^ 7) and 3739twf.doc / 006 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, only printed by consumer cooperatives Ί Η Η -V. Description of the invention (f) Tables 2A to 2C are cross-sectional views of the manufacturing process of a lower electrode of a DRAM capacitor according to a preferred embodiment of the present invention. Marking description of the drawings: 10, 110: substrate 20, 120 : Source / drain 30, 130 • silicon dioxide layer 40, 140: node contact window openings 50, 150: node contact window 60a, 160a: amorphous stone layer 60b, 60c, i60b, 160c: lower electrode 70: polycrystalline silicon 7 5: polycrystalline sand surface 80, 180: hemispherical silicon grains Example Please refer to FIGS. 2A to 2C, which illustrate a manufacturing process of a lower electrode of a DRAM capacitor according to a preferred embodiment of the present invention Sectional view. Please refer to Figure 2A, in the base 11 For example, the source / drain 120 is formed by an ion implantation method. Then, a silicon dioxide layer 130 ′ is formed on the substrate U0, and the formation method is, for example, LPCVD using Si (〇C2H5) 4 as a gas source for deposition The lithographic etching process is used to form the node contact window opening 140 in the silicon dioxide layer 130. Inside the node contact window opening 140, for example, doped polycrystalline silicon is deposited by LPCVD to fill the node contact window opening M0 to form the node contact window. 150. Next, a doped amorphous silicon layer i60a is deposited by PECVD. 7 This paper size applies to the Chinese National Standard (CNS) Λ4 grid (210X297) (please read the precautions and test page first). Packing. Line 3739twf.doc / 006 Η " ___ ___ 5. Description of the invention (6) The main gas source used in this PECVD is a silane (SUane, SixHy) compound, and its carrier gas can be hydrogen (H2), helium (He), or argon (Alm). The warming material required for the PECVD deposition reaction is only required to be below 400 ° C, and the deposition rate is more than about 1000 A / min, and the dopants required for the amorphous chopping can be simultaneously incorporated during the deposition reaction. The problem of reduced deposition rate encountered in LPCVD. The comparison of the parameters and properties of the amorphous silicon layer deposited by LPCVD and PECVD is summarized in Table 1. -:-: · ----- ^-(Please read the precautions on the back before filling this page) Line Table 1 LPCVD PECVD deposition temperature 500 ~ 550 ° C 400. (: The following deposition rate ~ 10 A / min (~ 530 oC) ^ 1000 A / min Main gas source Silane (SiH4) Silane (SixHv) Simultaneous acceptance of doping Low smell Doping efficiency Low central standard of the Ministry of Economic Affairs Bureau ’s consumer cooperative prints LPCVD based on the high temperature transmitted by the wafer, decomposing gas molecules on the wafer surface as a deposition gas source and performing the deposition reaction at the same time, so the required temperature is higher. But when depositing amorphous silicon, it ’s afraid If the temperature is too high, polycrystalline silicon will be formed, resulting in poor decomposition efficiency of the gas molecules. Therefore, the deposition rate is very slow. Impacted on the wafer surface and deposited on the wafer surface. Therefore, the efficiency of PECVD decomposition molecules is better 'faster deposition rate, coupled with a lower temperature required for deposition' can avoid the recrystallization of amorphous sand CNS) Λ4 specifications (210X297 '»^)
IV 3 739twf.d〇c/006 IV 3 739twf.d〇c/006 經濟部中央標準局員工消f合作社印製 五、發明説明（7) 出多晶矽’影響後續HSG-Si的生成。另外摻質氣體和非 曰曰石夕的沈積氣源’可以问時在電装中進彳了分解反應，再沈 積至晶片表面’所以同時(in situ)摻雜的接受力（capacibility) 以及摻雜效率會比LPCVD要好很多。 .目前可用的PECVD依其產生電漿的方法，大致有無 線電頻率-電隳化學氣相沈積法（Radio Frequency-PECVD, RF-PECVD) '電子迴旋共振-電漿化學氣相沈積法（Electron Cyclotron Resonance-PECVD，ECR-PECVD)和高密度電漿-電 漿化學氣相沈積法（High Density Plasma-PECVD, HDP-PECVD)等三種方法。而且使用PECVD還有一個附加的好 處，即在沈積非晶矽之前可利用H2、He/H2或Ar/H2電漿 來淸理晶片表面的污染物，以免污染物造成不可預期的影 響。 ’ 請參照第2B圖，定義非晶矽層160a ’形成下電極 160b。接著請參照第2C圖，進行播晶種以及在550〜570 °C 下之高真空回火的步驟，使下電極160b的表面選擇性的 生長出HSG-Si 180，變成表面積約爲原來兩倍大的下電極 6〇c。因爲在此係利用PECVD來沈積非晶矽層160a ’所以 不會有多晶矽摻雜於其中，整個下電極160c的表面皆可 長出 HSG-Si 180。 由上述本發明較佳實施例可知，應用本發明具有下列 優點。 第一、可避免非晶矽在沈積過程中再結晶出多晶砂’ 因此可讓由非晶矽所構成的下電極整個暴露出的表面，在 9 (請先閱讀背面之注意事項再填寫本頁) 裝 線 393774 3 739t、vf.d〇c/〇〇6 一 一**^*^·^*—- 立、發明说明（公） 播晶種和闻真空回火的步驟處理下長出半球型砂晶粒。 第二、因爲PECVD的沈積速率較快，所以可以使得 產能提昇。 第三、因爲PECVD在沈積之同時進行摻雜的能力較 胃，所以可以提昇下電極的導電能力。 第四、因爲可利用PECVD的攜帶氣體先淸理晶片表 面，所以可以防止斷線及提高產品良率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者’在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾’因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填.??本頁) 装. 線 經濟部中央標準局貝工消费合作社印製 本纸張尺度適用中國國家標準（CNS ) Λ4規格（2Ι〇Χ25>7,公及）IV 3 739twf.d0c / 006 IV 3 739twf.doc / 006 Printed by the staff of the Central Standards Bureau of the Ministry of Economic Affairs and printed by a cooperative Fifth, the description of the invention (7) Polycrystalline silicon ’affects the subsequent generation of HSG-Si. In addition, dopant gas and non-Shixi deposition gas source 'can be decomposed in the electrical equipment, and then deposited on the surface of the wafer', so the acceptability and doping of in-situ doping Efficiency will be much better than LPCVD. The currently available PECVD is based on the method of generating plasma. There are roughly Radio Frequency-PECVD (RF-PECVD) 'electron cyclotron resonance-plasma chemical vapor deposition (Electron Cyclotron) Resonance-PECVD, ECR-PECVD) and high-density plasma-plasma chemical vapor deposition (High Density Plasma-PECVD, HDP-PECVD). And there is an additional advantage of using PECVD, that is, H2, He / H2, or Ar / H2 plasma can be used to treat the contaminants on the wafer surface before depositing amorphous silicon, so as to prevent the contaminants from causing unexpected effects. ′ Please refer to FIG. 2B to define an amorphous silicon layer 160a ′ to form a lower electrode 160b. Next, referring to Figure 2C, the steps of seeding and high vacuum tempering at 550 ~ 570 ° C are performed to selectively grow HSG-Si 180 on the surface of the lower electrode 160b, so that the surface area is approximately twice the original. Large lower electrode 60c. Since the amorphous silicon layer 160a 'is deposited by PECVD here, no polycrystalline silicon is doped therein, and HSG-Si 180 can be grown on the entire surface of the lower electrode 160c. As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the following advantages. First, it can avoid the recrystallization of polycrystalline sand during the deposition of amorphous silicon. Therefore, the entire exposed surface of the lower electrode composed of amorphous silicon can be avoided. (Please read the precautions on the back before filling this Page) Installation line 393774 3 739t, vf.d〇c / 〇〇6 one by one ** ^ * ^ · ^ * —- standing, description of the invention (public) seeding seeds and vacuum tempering steps grow out Hemispherical sand grains. Second, because the deposition rate of PECVD is fast, it can increase the productivity. Third, because PECVD has a higher ability to dopant while depositing, it can improve the conductivity of the lower electrode. Fourth, because the carrier surface of PECVD can be used to pre-treat the wafer surface, disconnection can be prevented and product yield can be improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention to "any person skilled in the art" without departing from the spirit and scope of the present invention, and can make various modifications and retouches. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page.) Packing. The paper printed by the Central Standards Bureau of the Ministry of Online Economy, Shellfish Consumer Cooperatives, is printed on this paper, which applies the Chinese National Standard (CNS) Λ4 specification (2Ι〇χ25 > 7, Public)