TW396605B - Manufacturing method of metal capacitor constrcuture - Google Patents

Abstract

This is a metal capacitor structure suitable for the semiconductor chip with dynamic random access memory (DRAM) and logic device. The metal capacitor structure process includes a transistor on the semiconductor substrate. The first plug, which is in contact with the respective source/drain regions, is formed in the store structure region and the bit line region. The first interconnect wire contacting the first plug is formed in the store structure region and the bit line region. Then, the multiple layer plug and interconnect wire processes are performed in the store structure region. The interlayer connective wire and the plug in each layer serves as the store nodes for the metal capacitor structure. Finally, the capacitor isolation layer and metal plates manufacturing finishes the metal capacitor structure.

Description

V. Description of the invention (1) '----- 1 ~ 2 is related to the manufacturing process of a semiconductor device, especially to a dynamic random access memory (MAC) metal capacitor structure and a manufacturing method of some logic devices . Fan, ί ί '' Semiconductor chip system integrates logic device and memory at the same time ... ίί-device is used to process information or data, memory device is used to: i two storage 'These two devices are currently widely used in computers The system, however, the m device and the 'memory device' are generally packaged on their own specific chips, so the data signal between the two will be delayed. Round, its production f is much larger than those who integrate logic devices and memory devices on the same chip, because of the cost and performance considerations, semiconductor manufacturers must manufacture a semiconductor chip that integrates logic devices and memory devices. In addition, prior technology In the United States, Patent No. 5,6 27,095 refers to a kind of valley structure, but the complex capacitor structure used by it does not meet the logic device manufacturing process. In view of this, one of the inventions The idea is to propose a capacitor structure suitable for the DRA M single cell, its 1 ^] line structure is formed at the same time, so that the logic device and the memory device can be integrated on the same semiconductor chip at the same time. It increases performance and reduces manufacturing cost. The present invention is characterized in that when the storage structure is heated, it becomes _ D- this dung, and is used for short installation. The low-resistance metal material used for capacitor storage nodes can also be used at the same time. Connection of logic devices.

C: \ ProgramFiles \ Patent \ 0503-3574-E.ptd page 4 5. Description of the invention (2) Japanese + manufacturing method, a you-is to provide a system of capacitor structure of 011 and 8 ^ The second one uses some-the same m to manufacture MOSFETs and logic devices on the same semiconductor wafer. The second purpose of the avoidance structure is to manufacture a genus that uses metal plugs and interconnecting wire element structures:: f structure ', which is formed at the position D R Α Μ and metal plugs and interconnecting wire structures. Structural Ϊ—The purpose is to form metal plugs and interconnects at the lower layer and add metal plugs and interconnects. … For -ί = ΐ; :: ίΐ :: method according to the first embodiment of the present invention, the electrode structure of the present invention and the position of the upper and lower body are formed-transistor, including a gap wall In order to cover the thunder leg, the first insulation layer is formed, and at the same time, a contact window located in the storage: two-conductor substrate is formed in the bit line area, and its contact window and- In order to form contact with the corresponding source " and the polar region, respectively, the first contact between the knife and the storage node region and the bit line region is formed; the second insulating layer is formed with frost # 筮, Η A plug structure is formed on the surface of the plug; a plug is formed in the second insulation layer to make contact with the first interconnect structure in the storage node area, and a second interconnect structure is formed on the surface of the second insulation layer. Its and Chu

C: \ Program Files \ Patent \ 0503-3574-E.ptd page 5 of the storage node area _ covering the second insulating plug to form contact; forming the H-third golden eyebrow: layer and second interconnecting structure; The second insulation layer is contacted; except i, a metal plug is formed in the S-second insulation layer of the storage node area, and the g Γ 'insulation layer * part / minute of the first connection structure is formed as the storage node: 2 Wire structure, and the second metal recovery plug f: the top of the third zone-the meat ^ top, and the second metal plug above the plug, to be stored in the exposed: ΪΓ the first plug is used as the surface of the wrong point margin layer Forming-forming a capacitor insulation layer; and in the second embodiment of the invention, the present invention provides another-a plug, which is based on the foregoing system, and the third insulation is a capacitor structure system: ί ;: The surface of the second insulating layer forms the surface area of the third gold spot. In addition, according to the third embodiment, another manufacturing method of the ^ κ structure of the present invention is used for a semiconductor A metal capacitor junction at the end, and a transistor is formed at a predetermined position to cover the conductor. Base area; an upper surface is formed on the open electrode structure: and an insulating gap wall is formed on the electrode wall. Guard # $ @, at the gate electrode, the side of the semiconductor structure is beautiful. The first insulating layer covers the transistor. The self-aligned contact of the contact area;] edge: the two are the same: formed-located at the storage node office. The self-aligned contact that touched the position line area: exposed the corresponding source / impulse area; A polycrystalline silicon contact plug is simultaneously formed in the self-aligned contact window of the bit region to make contact with the corresponding source / drain region; a second insulation is formed.

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C: \ Program Files \ Patent \ 0503-3574-E.ptd page 6 V. Description of the invention (4) Storage node S 及: and = silicon contact plug 'In the second insulation layer, between the storage port and the storage port: The first metal test plug, which respectively touches; a contact surface is formed on the upper surface of the first-stop contact plug :::;! Dot area and bit line area shape; -Metal ... surface formation ;: area = line, where the line area in the third insulation sound-the first interconnecting structure; storage node area formation-the second metal plug to Insect, the first name of the amp & an internal connection structure is formed in the storage node area-the second internal connection cover, the second metal plug in the surface area of the second insulation layer to form contact two; absolutely: and storage The node j insulation layer and the second interconnect structure layer are formed to cover the first region-the third metal plug, so as to make contact with the storage node in the layer except the fourth insulation layer and a part of the f, e structure;

窠, 坌. Le-insulation layer, exposed Sheng-A :: two internal connection structure, and the second metal to the top of the second metal inspection, and below *, the temple line structure as a storage point, the first Metal plugs and polycrystalline silicon plugs I: the first and the third part of the dot area; a storage node is formed on the top of the exposed storage node and an upper metal plate is formed on the surface of the capacitor insulation layer. Electric valley insulation layer; Among them, the upper surface of the gate structure Xi, Fen # a < Ni η material to form a 'first' insulating layer gap wall "scene: and selective etching process can etch silicon oxide materials [One such The self-aligned contact window and the first insulating layer forming the exposed source / drain region can be illustrated in the following, and the embodiment of the present invention is illustrated below. C: \ Program F i1es \ Patent \ 0503-3574-E. Ptd Fifth, the description of the invention (5) Brief description of the drawings Figures 1 to 8 show the capacitor storage section of the too-surface area: one of the f. In one embodiment, the process steps formed on the -surface area include the -point structure Sectional view 'where the • ~, this 5 4 Ran metal line, and a second formed on a' where the first metal to fill the surface area includes a stack. The upper part of the metal plug. Figure 9-n of the metal plug Shows the capacitance storage inscription of the second real surface area of the present invention. The surface area includes a cross-sectional view of the first process step of the structure ^ < Chu-Α Η »-metal connection structure 'a plug and a second The upper part of the metal plug 9 The 12th to 14th genera shows that it is too complex The contact plugs were shot from ^ 3 to fill the structure to the source region. I aligned the contact window to connect the DRAM metal electric junction [Symbol Explanation] Seven field oxide layer of the semiconductor substrate ~ 2; Opening gate ~ 4; Insulation screen ~ 5; Interpretation margin layer J, day-to-day silicon ~ 7. P 卩 p right edge ". Β 仏 craft pole, ·, α structure ~ 6; light-changing heterogeneous / non-polar area ~ 7, gap wall ~ 8 'Densely doped source / drain region ~ 夂 18, 25; metal plugs ~ u, 12, 16, 19; ^ ::: element wire metal structure ~ 13; metal interconnect structure] 4, 17, 2 . Two H54; Capacitor insulation layer ~ 20; Mouth: layer, polycrystalline silicon plug ~ 31. Opening ~ 30, Example A manufacturing process for manufacturing a DRAM capacitor structure 'including a structure' where a metal storage node structure can be used Lang dotted line structure, and at the same time forming a metal oxide semiconductor (MOS transistor)

V. Description of the invention (6 ^ —---- Electricity is described in detail below. Among them, the transmission gate of the DRAM device used in the present invention is-N channel or NFET device, but it can also be & pFET transmission The gate is shown in Figure 1. Figure 1 shows an NFET transmission using a MDRAM device—P-type generation visit—A r, Section J 丨 甲 J Electric sun and sun limbs are 3 lithographic silicon substrates 1 is a [1 〇]] direction, the formed field oxidation area 2 is used for the ^ stone 5 separation, of which the field oxidation area 2 by depositing a nitride stone layer on the oxide layer and using traditional lithography process and non- The isotropic RIE process comes / forms an oxide mask (〇xidati〇n S, k) composed of silicon nitride-silicon oxide, and then removes the photoresist by the plasma oxygen ashing process. Wet engraved and oxidized at a temperature of about 850 to 1050. 匚 ^ oxidized in an oxygen-containing environment to form an area not covered by the oxidation mask, field oxide layer 2, thickness is about 300 0 Up to 5000 angstroms. The siliconized silicon layer as an oxidation mask can be removed by etching with a hot phosphoric acid solution, and then the silicon oxide layer underlying it is removed. The isolation region can also be a shallow trench isolation structure, which is firstly formed into a shallow trench in a semiconductor substrate by a conventional lithography process and an anisotropic RIE process, and then by low pressure chemical vapor deposition (LPCVD) or The plasma vapor deposition (PECVD) process deposits an insulating layer, such as a silicon oxide layer, and then removes the unnecessary insulating layer by selective etching or chemical mechanical polishing (CMP) to form a shallow trench isolation filled with insulating material. (Not shown). Secondly, a gate insulating layer 3 'is composed of a silicon oxide layer, which is formed by thermal oxidation under an oxygen vapor environment. The temperature is about 700 to 1050. (:, the thickness is about 3 〇 to 100 angstroms. Then LPCVD can be deposited to form a polycrystalline dream. The temperature is about 50 0 to 65 0 ° C. The thickness is about 1 500 to 4000 angstroms. Or polycrystalline spar / layer

C: \ ProgramFiles \ Patent \ 0503-3574 ~ E.ptd page 9

V. Description of the invention (7) 4 The arsenic or phosphorus can be added in the silicic methane environment to be doped with the deposition reaction (in_situ). The polycrystalline silicon layer 4 can also be deposited first, and then phosphorus or Arsenic ion doping. In addition, if there is a need for a low word line resistance, the polycrystalline silicon layer 4 can be replaced with a polycrystalline silicon silicide layer, for example, by depositing a metal lithium oxide layer such as a stone xihua crane on a composite shixi layer And formed. Finally, the insulating layer 5 is deposited using a LPCVD or PECVD process, which includes silicon oxide or silicon nitride, and has a thickness of about 500 to 15 Angstroms. In addition, traditional lithography and RIE etching processes are used, for example, carbon tetrafluoride (c &) is used as the etching gas for silicon nitride layer 5 (trifluoromethane CHF3 can be used as the etching gas for silicon oxide layer 4), and Etching is performed on the etching gas of the polycrystalline silicon layer or the polycrystalline silicon metal layer 4 to define a gate structure 6 having an insulating upper surface 5 as shown in FIG. 1. Secondly, after removing the photoresist used to define the polycrystalline silicon gate structure 4 by oxygen plasma deashing and wet cleaning, the lightly doped source / drain region 7 is implanted into the semiconductor by phosphorus or arsenic ions The area in the substrate 丨 that is not covered by the polycrystalline silicon gate structure 6 is formed with an implantation energy of about 25 to 50 KeV and a dose of about 1 £ 13 to 5E14 at 0 ms / cm2. Then, one is used as a subsequent gap wall The insulation layer of 8, including silicon nitride material, is again deposited by a "1) or 1) £: (^ 1) process to form a thickness of about 1000 to 3000 angstroms. The spacer 8 The insulating layer used can also be made of silicon material and obtained by LPCVD or pECVDt process deposition, through an anisotropic β IE etching process, such as the etched body of the fossil evening layer with trifluoromethane A 'technology gas T condition (Or use three random methane as the etching gas for the silicon oxide layer), and form an insulating spacer 8 on the side wall of the crystalline silicon gate structure 6. Finally, as shown in the figure, the heavily doped source / drain region 9 is formed by Phosphorus or arsenic ions implanted into semiconductors

C: \ ProgramFiles \ Patent \ 0503-3574-E.ptd page 10 V. Description of the invention (8) In the substrate 1, the implantation energy is about 20 to 80 K e V, and the dose is about 1 E 1 5 to 5E15 atoms / cm2 〇 Please refer to FIG. 2. An insulating layer 10, including a silicon oxide layer, is formed by a LPCVD or PECVD process and has a thickness of about loooo to 20,000 angstroms. The chemical mechanical polishing process is used to planarize the insulating layer, forming a smooth upper surface. The lithography and anisotropic rie with trifluoromethane as the etching gas are used to place the bit in the insulating layer 10. A wire contact window 51 is opened in the wire area, and a storage node contact window 52 is opened in the storage node area, which exposes the upper surface of the source / drain region 9 and is removed by ash removal and wet cleaning with an oxygen plasma. After defining the photoresist of the contact windows 51 and 52, a plug n, 12 is formed, wherein the plug 11, 12 can be a polycrystalline silicon layer formed by LPCVD process, and the degree of f is about 3000 to loooo, which It is used to completely fill the bit line contact window 51 and the storage node contact window 52. Alternatively, the polycrystalline silicon layer can be doped with in-situ by adding arsenic or phosphorus in a siloxane environment. In addition, the polycrystalline silicon layer can be replaced with a metal material, such as a metal tungsten layer deposited by LPCVD or reduced bond. Then, the unnecessary polycrystalline silicon or metal tungsten layer is removed from the surface of the insulating layer 10 by a CMP process or selective engraving, and a bit line contact plug 1 is formed in the bit line contact window ^, and a storage node is formed. A storage node contact plug 12 is formed in the contact window 52. In addition, when a metal tungsten layer is formed, a barrier layer, such as a titanium nitride layer, may be formed on its surface to improve the adhesion of crane metal. Please refer to FIG. 3, which shows bit lines formed in the bit line area and the storage node area at the same time. The metal structure 13 and the DRAM metal interconnect structure 14 are deposited with a metal material such as tungsten metal by LPCVD or RF sputtering process

V. Description of the invention (9) f = about 1000 to 5000 Angstroms. The lithography process and process can be used to simultaneously form a bit line metal structure 13 in contact with the bit line plug 11 and a DRAM metal interconnect structure η in contact with the storage node plug 12. Please refer to Figure 4. After the photoresist used to define the photoresist is removed by oxygen plasma deashing and wet cleaning, an insulating layer, such as a silicon oxide layer, is formed by LPCVD or PECVD process deposition, and the thickness is about The thickness is 10,000 to 29,000 angstroms, and then planarized by a CMP process. The lithography process and the anisotropic RIE process with trifluoromethane as the source of engraving are used to open the history-intermediate window 53 in the insulation layer 5 and expose the upper surface of the DRAM metal interconnect structure 14 After removing the photoresist used to define the interlayer window 53 by oxygen ash removal and wet cleaning, a metal layer, such as a metal tungsten layer, is formed by LPCVI) or RF sputtering process to form a thickness of about It is 2000 to 5000 Angstroms, which completely fills the interlayer window 53. Next, a selective RIE process or a CMP process can be used to remove the metal material 'unnecessary on the surface 15 of the insulating layer to form a dram metal plug 16 in the interlayer window 53. Then 'see Fig. 5. Another metal layer, such as a metal tungsten layer, is formed by LPCVD or RF sputtering with a thickness of about 1,000 to 50,000 angstroms', and then by lithography and non-equivalent. The directional RIE process is performed to form a DRAM metal interconnect structure 17 on the surface of the DRAM metal plug 16 in contact therewith. When the via window 53 and the DRAM metal interconnect structure 17 are formed, the via window and the metal interconnect structure used in the MOSFET logic device are also formed at the same time. The MOSFET logic device system and the DRAM memory device are arranged in the same It is not shown on the semiconductor wafer.

C: \ Program Files \ Patent \ 0503-3574-E.ptd Page 12 V. Description of the invention (10) ---- Please refer to Figure 6 and remove again by oxygen plasma deashing and wet cleaning. After defining the photoresist of these metal interconnect structures, an insulating layer, including 8 ', including a silicon oxide layer, is deposited by LPCVD or PECVD process to form a thick sound with a thickness of about 100 to 2000 Angstroms. The CMP process is used for planarization. The " process and the anisotropic RIE process are used to open a via window 54 which is located in the insulating layer 18 and exposes the upper surface of the dram metal interconnect structure 17. — A metal layer, such as a metal tungsten layer, is again formed by "port 1" or radio frequency sputtering with a thickness of about 200 to 5000 angstroms, which is completely filled in * 54, using a selective RIE process and a pp process. The unnecessary metal material in the insulating layer 18 ^ can be removed to form a DRAM metal plug Η in the via window 54. The formation of the via window 54 and the DRAM metal plug 19 is the last metal layer formed by the MOSFET logic device. In the latter additional step, when considering the number and order of layers regarding metal plugs and interconnect structures, deep mediator windows with high aspect ratios and difficult to fill in the characteristics of metal materials are excluded. Please refer to Figure 7, The metal plug and metal internal structure of the exposed part are used as storage nodes of the fine AM capacitor structure. The insulating layer ^ and the upper part of the insulating layer 15 are removed approximately 1000 to 150,000 angstroms to expose the gold plug. 19. The upper part of the DRAM metal interconnect structure 17, and the DRAM metal plug "is about 0 to 1000 angstroms. Removal of these insulating layers can be engraved using a selective rie surname ^ it can be trifluoromethane fired as an etching source, or it can be removed by using a buffer solution. These metal plugs and interconnects The exposed surface will be used as the storage node surface of the DRAM capacitor structure, and the storage node can be made stronger by breaking through the insulation layer, the W metal plug, and the interconnect structure.

The five 'invention description (11) is connected to a semiconductor substrate. Refer to Figure 8 for the servant 5t. A capacitor insulation layer 20, such as tantalum oxide, barium titanium oxide, etc., can be formed by MOCVD (meta organic CVD), coating, " coating process deposition. , The thickness is about 4 to 50 angstroms, a metal metal crane layer, deposited by LPCVD or radio frequency sputtering process to 100 ° to 100,000 angstroms, finally, using the lithography process and non-.1 clothing process to form a The upper metal plate 21 is deoxidized and wet with oxygen plasma. It is used to define the photoresistance of the upper metal plate 21 to complete the DRAM gold ~ 5 order structure, which includes the upper metal plate 21 and the capacitor insulation layer. And storage = point structure, the storage node structure is composed of DRAM metal plug 19, metal interconnect structure 17, and the upper part of DRAM metal plug 16 in order. 2. The second embodiment of the present invention is shown in FIGS. 9 to 11, which is a method for increasing the surface area of the DRA ^ I metal capacitor structure. It is based on the embodiment of FIG. 6 'stacking embedded in the insulation layer. Add another DRAM metal interconnect structure to the metal plug and interconnect structure. ^ — Please refer to Figure 6 and refer to Figure 9. A metal layer, such as a metal tungsten layer, is deposited by LPCVD or RF sputtering process and has a thickness of about 2000 to 5000 Angstroms. A lithography process and an anisotropic RIE process are used to form a DRAM metal interconnect structure 22 'which is located on the surface of the DRAM metal plug 9 and is in contact with it' finally 'by oxygen plasma deashing and wet cleaning to remove The photoresist of the DRAM metal interconnect structure 22 is defined. Please refer to Section 10 (b). The same process as in the previous first embodiment, removing the insulating layer 18 and the upper part of the insulating layer 15 from about 2000 to 15 Angstroms, and removing these insulating layers can use the selective R IE The etching process is completed.

C: \ ProgramFiles \ Patent \ 0503-3574-E. Ptd page 14

Etching source. And to expose the storage node structure of FIG. 10, the DRAM metal interconnect structure 22, the hard metal plug ⑺, and the upper part of the DRAM metal plug 16. Stacked on two = connected additional DRAM metal interconnect structure 22 is used to increase the J point and therefore can increase capacitance and performance. Area, Figure 11 shows a complete ⑽ "capacitor structure, due to the metal interconnect structure 22, which increases the surface area, in which the electric c, 20 :: on the metal plate 21, the same as the first of the previous Figure 8 Reality: use the same process and materials. "Please refer to Figure / 12. The third embodiment uses self-aligned contact windows (), ',; | between the gate structures and fill in the complex Crystal silicon plug, contact with the source / drain region, and tungsten plug or traditional narrower contact ratio. The use of polycrystalline silicon plug in the self-aligned contact window can improve the leakage current m2. Flattening] Covered gate structure 6. Please refer to Fig. 13 for the 25th increase. The ΓΓα window Γ located in the storage node area and the bit line area is covered by the nitrided layer 5 of the interfacial structure 6 and the interstitial soil 8 of the argonized group. The lithography and selective etching process etch the first insulating layer 25 made of silicon oxide to form a self-contact window 30 that exposes the source / drain region 9. For example, the SAC opening 30 can be formed by a lithography process and a selective RIE process using a trifluoromethyl engraving source. Among them, a nitride nitride gap and a silicon nitride layer 5 are used as a mask, and trifluoromethane is used as an etching source. In the selective RIE process, a sac opening can be formed by etching in the insulating layer 25 between the gate structures, and the width is larger than the interval between the gate structures. Deposition followed-polycrystalline silicon layer

C: \ ProgramFiles \ Patent \ 0503-3574-E.ptd page 15 V. Description of the invention (13) 31 'If silazane is used as a gas source and deposited by the LPCVD process, the thickness is about 3 0 0 0 to 7 0 0 0 Angstroms, in order to completely fill the S AC openings 30, the polycrystalline silicon layer 31 can be added with arsenic or phosphorus in a silicon methane environment to be doped with the deposition reaction (in-si tu) or the polycrystalline silicon layer 31 It can also be deposited first, and then filled or doped with erbium ions by ion implantation. In addition, selective selective E process or CMP process can be used to remove the polycrystalline silicon material unnecessary on the surface of the insulating layer 25 to form a doped polycrystalline silicon plug 31 in the SAC opening 30, and the source / drain region 9 contact. = Refer to Figure 14 'as described previously' which includes the same elements, such as a same metal plug and interconnect structure formed in a stack storage node by filling the SAC opening with doped 4 ·· '/ The plug is connected to the source / inverted region, so it can be changed to connect &, b ”Riri Shi Xishuan Although the present invention has been exposed in a preferred embodiment as an issue of current. To limit the present invention, Anyone who is familiar with this skill can use the scope of God and the scope, but can make some changes and embellish it without departing from the scope of the present invention. The righteous shall prevail.

Claims (1)

6. Scope of Patent Application 1. A method for manufacturing a metal capacitor structure suitable for a semiconductor substrate, comprising: forming a transistor at a predetermined position on the semiconductor substrate, including a gate structure and a source / drain region, wherein the gate A sidewall of the pole structure and an insulating gap; forming a first insulating layer to cover the transistor and the semiconductor substrate; in the first insulating layer, a contact window in the storage node area and a bit line area are formed at the same time A contact window, which exposes the corresponding source / drain region, and simultaneously forms a first plug in the contact window between the storage node region and the bit line region to make contact with the corresponding source / drain region respectively; A first interconnect structure is formed on the surface of the first insulating layer at the same time in the storage node area and the bit line area, which are in contact with the upper surface of the first plug of the storage node area and the bit line area, respectively; forming a A second insulation layer covers the first insulation layer and the first interconnect structure of the storage node area and the bit line area; a second metal plug is formed in the second insulation layer to communicate with the storage node A first interconnect structure in the region forms a contact; a second interconnect structure is formed on the surface of the second insulating layer, which is in contact with a second metal plug of the storage node region; a third insulating layer is formed to cover the A second insulating layer and a second interconnect structure; forming a third metal plug in the third insulating layer to make contact with the second interconnect structure of the storage node area; C: \ ProgramFiles \ Patent \ 0503-3574-E. Ptd page 17 VI. Patent application scope Remove the third insulation layer and part of the second insulation layer, exposing the third metal plug and the second interconnect structure And the upper part of the second metal plug as the top of the storage node, and the lower part of the second metal plug, the first interconnecting structure of the storage node area and the first plug as the bottom of the storage node; A capacitor / column edge layer is formed on the top of the exposed storage node; and an upper metal plate is formed on the surface of the capacitor insulation layer. 2. The method according to item 1 of the scope of patent application, wherein the first insulating layer is made of silicon oxide material. 3. The method according to item 1 of the scope of patent application, wherein the first plug is made of metal tungsten. 4. The method according to item 1 of the scope of patent application, wherein the first plug is made of polycrystalline silicon. 5. The method according to item 1 of the scope of patent application, wherein the first interconnect structure is made of metal tungsten. 6. The method according to item 1 of the scope of patent application, wherein the second insulating layer is made of silicon oxide material. 7. The method according to item 1 of the scope of patent application, wherein the second metal plug is made of metal tungsten. 8. The method according to item 1 of the scope of patent application, wherein the third insulating layer is made of silicon oxide material. 9. The method according to item 1 of the scope of patent application, wherein the step of removing the third insulating layer and part of the second insulating layer is completed by a selective R IE etching process, which uses trifluoromethane as an etching source . C: \ ProgramFiles \ Patent \ 0503-3574-E. Ptd page 18 6. The patent application scope touches the plug; in the second insulating layer, a first metal plug is formed at the time, and the polycrystalline silicon contact plug on the surface is formed on the surface, and a first interconnect structure is formed on the surface of the second insulating layer. A third insulating layer is formed on the upper surface of the first metal plug in the region, and a first interconnecting structure of the first interconnecting line of the bit line region in the middle node region of the second insulating layer is on the surface of the third insulating layer. The second Jinli formation of the storage node area-the fourth insulation 2 structure; in this, the second interconnection structure of the middle node area in the fourth insulation layer removes the fourth insulation layer and the three metal plugs, and the second interconnection The first internal silicon plug that serves as the storage node and the storage point area is used as the storage node at the exposed storage node on the surface of the valley insulation layer 2: storage. The point area is the same as the bit line area /, The knife is in contact with the storage node area and the bit line surface; the line is in contact with the storage node area and the bit line area at the same time, and the storage node area and the bit line are in contact with each other; f covers the second insulation Layer and storage node area structure; A second metal plug to make contact with the storage; forming a second interconnection structure that makes contact with the plug; covering the third insulating layer and the second interconnection to form a third metal plug for contact The storage I forms a contact; a portion of the third insulating layer 'exposes the top of the first structure and the second metal plug, and the wiring structure under the second metal plug, the bottom of the first plug and the compound ; A capacitor insulating layer is formed on the top; and an upper metal plate is formed. C: \ ProgramFiles \ Patent \ 0503-3574-E.ptd page 20 VI. Patent application scope pole company 2. As described in the application patent scope No. 14 method, the shielding layer on the upper surface is one Silicon nitride layer. The method for the extreme surname is as described in item 15 of the scope of patent application. A method as described in item 16 of the scope of patent application, the insulation layer is made of stone oxide material. ',, the method described in item 22 is the method described in item 17 of the scope of the patent application, and 4: 自我: the self-aligned contact window of the dot area and the self-positioned 碉 ® located in the bit line area are based on The silicon nitride masking layer and the silicon nitride gap = my pair: the silicon oxide material is etched by lithography and selective etching processes; 2 act, 'layers' form self-aligned contact windows that expose the source / drain regions . — Absolute—1 9 · The method according to item 14 of the scope of patent application, wherein the first plug, the second metal plug, and the third metal plug include depositing metal tungsten by a low pressure chemical vapor deposition method or a radio frequency sputtering process. Material steps. 20. The method according to item 14 of the scope of the patent application, wherein the first interconnect structure and the second interconnect structure include a metal tungsten material deposited by a low pressure chemical vapor deposition method or a radio frequency sputtering process. step. 2 1. The method according to item 4 of the scope of the patent application, wherein the 忒 multicrystalline silicon plug is formed by low pressure chemical vapor deposition. In JL, this complex 22. The method described in item 21 of the scope of the patent application, and the accumulation of anti-crystalline silicon embolism system includes adding tritium in the siloxane environment or filling it with "in-situ" doping The steps. Among them, the method described in item 14 of the scope of the patent application, "'Then, the deposition by the low-pressure chemical vapor deposition method by the crystalline silicon plug system'," C, \ ProgramFiles \ Patent \ 0503-3574-E.ptd page 21 VI 'patent application sub-implantation method for phosphorus or arsenic ion doping. ΙΙΙΙΙΙΙ C: \ ProgramFiles \ Patent \ 0503-3574-E. Ptd page 22