3542twf.doc/005 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（丨） 本發明是有關於一種混合元件(Mixed-mode)的製造方 法，且特別是有關於一種可控制閘氧化層之形成厚度’以 改善閘氧化層品質的方法。 隨著積體電路之半導體元件的積集度日益增加，因此 製程的準確度就顯得格外，重要。因爲一旦在製程中發生細 微錯誤(error)，即可能就會造成製程的失敗’導致晶片的 毀損或報廢，因而耗費大量成本。 第1A〜1C圖繪示的是習知一種混合元件的製造方法。 首先請參照第1A圖，提供一半導體基底10，在半導 體基底10上依序形成一閘氧化層I2、一多晶矽層14與一 閘氧化層16覆蓋整個基底結構，其中形成閘氧化層16之 厚度將決定後續製程之電性。 接著請參照第1B圖，上光阻覆蓋欲形成元件的地方， 然後進行微影鈾刻製程至暴露出半導體基底10表面，以 形成閘極結構18與20，其中閘極結構1S與20分別係由 閘氧化層12a、多晶矽層14a與閘氧化層16a所組成，並假 設閘氧化層16a之厚度爲A。之後，例如使用硫酸(H2S04) 剝除上述光阻。然後，上光阻22覆蓋閘極結構18.。 再來請參照第1C圖，回蝕刻暴露出之閘極結構20之 閘氧化層16a，直到其厚度由山變爲d2爲止，如圖中所繪 示，以形成閛氧化層16b，其中因閘氧化層16b與閘氧化 層16a的厚度不同，將使得兩元件具有不同之電容値。在 此同時，將因上述回蝕刻製程，而容易造成閘極結構20 之閛氧化層16a遭受到傷害(damage)，並且形成閘氧化層 本紙張又度適用中國國家檩準（CNS ) A4規格（210X297公釐） / ^ -8 (請先閱讀背面之注意事項再填寫本頁)3542twf.doc / 005 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (丨) The present invention relates to a method for manufacturing a mixed-mode, and in particular, to a controllable brake Method for forming the thickness of the oxide layer to improve the quality of the gate oxide layer. With the increasing accumulation of semiconductor components in integrated circuits, the accuracy of the manufacturing process becomes particularly important. Because if a slight error occurs in the process, it may cause the process to fail ', which may cause the wafer to be damaged or scrapped, thus consuming a lot of costs. Figures 1A to 1C show a conventional method for manufacturing a hybrid device. First, referring to FIG. 1A, a semiconductor substrate 10 is provided. A gate oxide layer I2, a polycrystalline silicon layer 14 and a gate oxide layer 16 are sequentially formed on the semiconductor substrate 10 to cover the entire base structure. The thickness of the gate oxide layer 16 is formed therein. Will determine the electrical properties of subsequent processes. Next, please refer to FIG. 1B, a photoresist is used to cover the parts to be formed, and then a lithography lithography process is performed to expose the surface of the semiconductor substrate 10 to form gate structures 18 and 20, where the gate structures 1S and 20 are respectively It is composed of the gate oxide layer 12a, the polycrystalline silicon layer 14a, and the gate oxide layer 16a, and it is assumed that the thickness of the gate oxide layer 16a is A. After that, the photoresist is removed using, for example, sulfuric acid (H2S04). Then, the upper photoresistor 22 covers the gate structure 18. Referring again to FIG. 1C, the gate oxide layer 16a of the exposed gate structure 20 is etched back until its thickness changes from mountain to d2, as shown in the figure, to form a hafnium oxide layer 16b. The thicknesses of the oxide layer 16b and the gate oxide layer 16a are different, so that the two elements have different capacitances. At the same time, due to the etch-back process described above, damage to the oxide layer 16a of the gate structure 20 is likely to occur, and the gate oxide layer is formed. This paper is also applicable to the Chinese National Standard (CNS) A4 specification ( 210X297 mm) / ^ -8 (Please read the notes on the back before filling this page)
3542twf.doc/005 3542twf.doc/005 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（> ) 16a之厚度亦不易掌控。隨後去除光阻22。 接著，例如使用低壓化學氣相沉積法(LPCVD)，在閘 氧化層16a與16b上形成一層多晶砂層24,以完成兩個不 同電容値之元件。 之後進行後續的半導體製程，由於此非關本發明，在 此不多做贅言。 有鑒於此，本發明的目的就是在提供一種混合元件的 製造方法，以解決習知回蝕刻閘氧化層，導致閘氧化層遭 受損害的問題。 本發明的另一目的，提出一種混合元件的製造方法， 係利用簡易非晶矽成長技術，配合閘氧化層成長，以易於 控制閘氧化層之形成厚度。 爲達成本發明之上述和其他目的，一種混合元件的製 造方法，包括下列步驟：首先於半導體基底上依序形成第 一閘氧化層、第一多晶矽層與非晶矽層。接著依序定義非 晶矽層、第一多晶矽層與第一閘氧化層，直到暴露出半導 體基底表面爲止，以形成第一閘極結構與第二閘極結構。 之後去除第二閘極結構之非晶矽層，以暴露出第二閘極結 構之多晶矽層表面。再來形成第二閘氧化層與第三閘氧化 層，分別覆蓋第一閘極結構與第二閘極結構表面。最後形 成第二多晶矽層覆蓋第二閘氧化層與第三閘氧化層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I---------裝-- (請先閱讀背面之注意事項再填寫本頁) 訂 i- 3542twf.doc/005 A7 B7 五、發明説明（）） 圖式之簡單說明： 第1A〜1C圖繪示的是習知一種混合元J生的製麗方法； _--------- 以及 ： 第2A〜2E圖繪示的是依照本發朋一較隹寞施现的二種 混合元件的製造方贫。 圖式之標號說明： 10、30 :半導體基底 12、12a、16、16a、16b、32、32a、44、46 :闊氧化 層 14、14a、24、34、34a、48 :多晶砂層 18、20、38、40、40a :閘極結構 22、42 :光阻 36、3 6a :非晶Ϊ夕層 實施例 請參照第2A〜2E圖，其繪示的是依照本發明一較佳實 施例的一種混合元件的製造方法。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 首先請參照第2A圖，提供一半導體基底30，在半導 體基底30上依序形成一閘氧化層32、一多晶矽層34與一 非晶矽層36覆蓋整個基底結構，其中形成非晶矽層36之 厚度將決定後續之電性。 接著請參照第2B圖，上光阻覆蓋欲形成元件的地方， 然後進行微影蝕刻製程至暴露出半導體基底30表面，以 形成閘極結構38與40，其中閘極結構38與40分別係由 閘氧化層32a、多晶矽層34a與非晶矽層36a所組成。隨後 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3542twf.doc/005 3542twf.doc/005 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（·/) 去除上述光阻。然後，上光阻42覆蓋閘極結構％。 再來請參照第2C圖，然後使用乾蝕刻法例如反應性離 子蝕刻法(Reactive Ion Etch ; RIE) ’蝕刻去除未被光阻42 覆蓋之閘極結構40之非晶矽層36a，以暴露出閘極結構4〇 之多晶矽層34a表面’分別形成兩種不同的閘極結構38 與40a。隨後，去除光阻42。 之後請參照第2D圖，利用非晶砂（氧化速率快)與多晶 矽（氧化速率慢）之氧化速率的不同，例如使用熱氧化法於 兩蘭極結構38與40a之多晶砂層34a上，分別形成一層鬧 氧化層44與46，其中閘氧化層44與46的材質例如是二 氧化砍。此外，因非晶砂與多晶砂氧化速率之不同，故會 產生不同厚度之閘氧化層44與46 ’如第2D圖所繪示，藉 以使我們可以有效地控制閘氧化層44與46之厚度。換言 之’本發明係利用閘氧化層之成長取代習知利用回蝕刻閘 氧化層的方法，如此不僅可避免閘氧化層遭受傷害，並且 更可有效地掌控閘氧化層之厚度。 接著請參照第2E圖’例如使用低壓化學氣相沉積法， 在閘氧化層44與46上形成一層多晶矽層48，以完成兩個 不同電容値之元件。 之後進行後續的半導體製程’由於此非關本發明，在 此不多做贅言。 綜上所述，本發明的特徵，係利用簡易的非晶矽成長 技術，配合閘氧化層成長，達到易於控制閘氧化層之形成 厚度之目的。 ---------f',裝— (請先閲讀背面之注意事項再填寫本頁)3542twf.doc / 005 3542twf.doc / 005 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs B7 V. Description of the Invention (>) The thickness of 16a is not easy to control. The photoresist 22 is subsequently removed. Next, for example, a low-pressure chemical vapor deposition (LPCVD) method is used to form a polycrystalline sand layer 24 on the gate oxide layers 16a and 16b to complete two elements with different capacitances. Subsequent semiconductor processes will be performed thereafter. Since this is not related to the present invention, I will not go into details here. In view of this, an object of the present invention is to provide a method for manufacturing a hybrid device, so as to solve the problem that the conventional gate oxide layer is etched back and the gate oxide layer is damaged. Another object of the present invention is to provide a method for manufacturing a hybrid device, which uses a simple amorphous silicon growth technology in conjunction with the growth of a gate oxide layer to easily control the thickness of the gate oxide layer. In order to achieve the above and other objects of the present invention, a method for manufacturing a hybrid device includes the following steps: First, a first gate oxide layer, a first polycrystalline silicon layer, and an amorphous silicon layer are sequentially formed on a semiconductor substrate. Then, the amorphous silicon layer, the first polycrystalline silicon layer, and the first gate oxide layer are sequentially defined until the semiconductor substrate surface is exposed to form a first gate structure and a second gate structure. Thereafter, the amorphous silicon layer of the second gate structure is removed to expose the surface of the polycrystalline silicon layer of the second gate structure. Then, a second gate oxide layer and a third gate oxide layer are formed to cover the surfaces of the first gate structure and the second gate structure, respectively. Finally, a second polycrystalline silicon layer is formed to cover the second gate oxide layer and the third gate oxide layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: This paper size applies to the Chinese National Standard (CNS ) A4 specification (210X297mm) I --------- install-(Please read the precautions on the back before filling this page) Order i- 3542twf.doc / 005 A7 B7 V. Description of the invention () ) Brief description of the drawings: Figures 1A ~ 1C show the method of making a beauty of a hybrid element J; _--------- and: Figures 2A ~ 2E show Ben Fapeng is poorer than the manufacturer of the two hybrid components. Description of the symbols of the drawings: 10, 30: semiconductor substrates 12, 12a, 16, 16a, 16b, 32, 32a, 44, 46: broad oxide layers 14, 14a, 24, 34, 34a, 48: polycrystalline sand layer 18, 20, 38, 40, 40a: Gate structure 22, 42: Photoresistor 36, 36a: Example of amorphous silicon layer Please refer to FIGS. 2A to 2E, which shows a preferred embodiment according to the present invention A method for manufacturing a hybrid element. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) First, please refer to Figure 2A, provide a semiconductor substrate 30, and sequentially form a gate oxide layer 32 on the semiconductor substrate 30, A polycrystalline silicon layer 34 and an amorphous silicon layer 36 cover the entire base structure. The thickness of the amorphous silicon layer 36 will determine subsequent electrical properties. Referring to FIG. 2B, a photoresist is used to cover the parts to be formed, and then a lithographic etching process is performed to expose the surface of the semiconductor substrate 30 to form gate structures 38 and 40. The gate structures 38 and 40 are respectively formed by The gate oxide layer 32a, the polycrystalline silicon layer 34a, and the amorphous silicon layer 36a are composed. Subsequently, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 3542twf.doc / 005 3542twf.doc / 005 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (· /) Remove the above Photoresist. Then, the upper photoresistor 42 covers the gate structure%. Please refer to FIG. 2C again, and then use a dry etching method such as a reactive ion etching method (Reactive Ion Etch; RIE) to etch and remove the amorphous silicon layer 36a of the gate structure 40 not covered by the photoresist 42 to expose Two different gate structures 38 and 40a are formed on the surface of the polycrystalline silicon layer 34a of the gate structure 40, respectively. Subsequently, the photoresist 42 is removed. Please refer to Figure 2D afterwards. Use the difference between the oxidation rate of amorphous sand (fast oxidation rate) and polycrystalline silicon (slow oxidation rate). For example, use thermal oxidation method on the polycrystalline sand layer 34a of the two blue pole structures 38 and 40a. A layer of oxide layers 44 and 46 is formed, and the material of the gate oxide layers 44 and 46 is, for example, dicing oxide. In addition, due to the different oxidation rates of amorphous sand and polycrystalline sand, gate oxide layers 44 and 46 of different thicknesses will be generated as shown in Figure 2D, so that we can effectively control the gate oxide layers 44 and 46. thickness. In other words, the present invention replaces the conventional method of etching back the gate oxide layer by using the growth of the gate oxide layer, so that not only the gate oxide layer can be prevented from being damaged, but also the thickness of the gate oxide layer can be effectively controlled. Then referring to FIG. 2E, for example, a low-pressure chemical vapor deposition method is used to form a polycrystalline silicon layer 48 on the gate oxide layers 44 and 46 to complete two elements with different capacitances. Since the subsequent semiconductor process is performed later, since it is not related to the present invention, I will not repeat it here. In summary, the feature of the present invention is to use simple amorphous silicon growth technology in conjunction with the growth of the gate oxide layer to achieve the purpose of easily controlling the formation thickness of the gate oxide layer. --------- f ', equipment — (Please read the notes on the back before filling this page)
、tT 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X 297公釐） 3542twf.doc/005 A7 B7 五、發明説明（7) 雖然本發明已以較佳實施例揭露如上’然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾’因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）, TT This paper size is applicable to China National Standards (CNS) A4 specifications (210X 297 mm) 3542twf.doc / 005 A7 B7 V. Description of the invention (7) Although the present invention has been disclosed as above with preferred embodiments, it is not To limit the invention, anyone skilled in the art can make various modifications and retouches without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the appended patents as follows: quasi. (Please read the precautions on the back before filling out this page) Binding and printing Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X 297 mm)