TW389983B - Improvement of isolation spacing between a self-aligned contacts and gate - Google Patents

Abstract

This invention provides an improved method of isolation spacing between a self-aligned contact (SAC) and a gate. A silicon-oxy-nitride (SiON) substitutes conventional silicon nitride layer to serve as a hard mask when a polycide layer is subject to Cl2/HBr plasma etching. Hydrogen is released when the SiON layer is etched and reacts with polymer on the sidewall of the polyside from etching the photoresist such that the etching rate of the sidewall of the polycide is increased and the width of the gate is less than that of the SiON layer. Accordingly, the hard mask has the same width as prior art but the gap between the gates is larger. Thereafter, the bottom of the insulating spacer on the sidewall of the SiON layer and the polycide is thicker, thereby increasing the isolation spacing between the SAC and the gate.

Description

The manufacture of circuits, especially when a metal engraved silicon compound is used to enhance self-aligned contact windows, and the present invention relates to a semiconductor building block and a polycide stack using an Ion Oxide (SiON) layer. Hard cover, improved isolation process of gate. The manufacturing of semiconductor integrated circuits (1C) is located in the county. The purpose of the extremely complicated crossing is to reduce the size of various electronic components and circuits required for specific circuits on a small-scale substrate. : Each component in the film must be guided by appropriate inline ^ ^ ^ ^ ^ ^ ^ ^ ^ In general, the so-called metallization process of integrated circuits, in addition to making various layers of wire patterns, and using contact windows (contact / via) structure, is used as the contact between the component contact area and the wires or the multilayer wires. In the channel, when manufacturing high-density integrated circuit components such as dynamic random access memory (DRAM), the so-called self-aligned contact window (SAC) process is often used to improve the precision of the wire. At present, the production line usually uses a silicon nitride layer as a hard cover when etching the closed electrode structure and as a top protective layer when the contact window is etched later. As for the side wall portion of the gate, an insulation gap is used. Wall (spacer) to provide protection. However, as the size of integrated circuit components continues to shrink, the insulation gap used to isolate the contact window from the gate also becomes thinner, which not only tends to cause the problem of poor isolation, but also makes the etching of the contact window. The conditions are rigorous and are not conducive to production. In order to further explore the problem, the following describes the manufacturing process of the conventional technology with reference to the figures ^ to 丨!). First, as shown in the figure, a semi-conductor substrate 10 'is provided, such as a silicon wafer. A gate is sequentially formed on the substrate 10

C: \ ProgramFiles \ Patent \ 0503-3784-E.ptd Page 4 V. Description of the invention (2) Electrode dielectric layer 11 and a gate conductive layer 12 'For example, first, a thermal oxidation process or a chemical vapor deposition process A gate oxide layer U is formed to cover the surface of the substrate 10 ', and then a metal polycrystalide stack 12 is formed on the closed oxide layer 11, which sequentially deposits a polycrystalline dream layer and A dream formed by the town layer. Then, a silicon nitride layer 13 is deposited on the surface of the metal polycrystalline silicide stack 12 and a photoresist 19 is used as a mask to perform an etching process to form the structure shown in the figure. ' It covers the portion where the transistor gate is to be formed. Secondly, please refer to FIG. 1B, using the silicon nitride layer 13 as a hard mask to perform a plasma etching process, for example, using Cl2 / HBr as an etching gas to remove the metal polycrystalline silicide stack 12 The portion covered by the silicon nitride layer 13 forms a polycide gate 12a. During the engraving process, the photoresist pattern 19 is etched due to poor anti-etching ability, and a part of the reaction forms a polymer protective layer and covers the sidewall of the polyc ide gate 12a, which can suppress excessive horizontal surnames. Therefore, after the #etching process, the sidewalls of the nitrided layer 13 and the polyc ide gate 12a become approximately a vertical shape, that is, the size of the nitrided layer 13 is accurately transferred to the poiycide gate 12a. . Next, as shown in FIG. 1C, another etching process is performed to remove the exposed portion of the gate oxide layer 11 to complete the fabrication of a gate structure. Then, an insulating layer is first deposited on the surface of the nitride nitride layer 13, the polycide gate electrode 12a, the gate oxide layer 11, and the substrate 10, and then an anisotropic (an i so tr op) is applied to the insulating layer. ic) back to the engraving process, such as a reactive ion etching (RIE) process, leaving the silicon nitride layer 13 and the polycide gate

C: \ Program Files \ Patent \ 0503-3784-E.ptd page 5 5. Description of the invention (3) Insulation spacer 14 on the side wall of 12a. Forming a frank insulating layer 15 covers the surface of each of the above layers, a glass (BPSG) layer. On the surface of each layer, for example, after depositing a broken glass, another photoresist layer 16 is coated on the surface of the flattened insulating layer 15 and lithography is performed, which is formed like a program—open σ17, and expose the contact window 4 to be formed. 'See Figure 1D, using photoresist layer 16 as a cover, and etching and flattening the insulating layer to form a contact window 18' which is equivalent to opening 17 and the lower half is due to s servants ’thinking, ' The protective effect of a large width, the alignment is aligned: = II and the insulating spacer 14 are flattened to the surface of the semiconductor substrate 1 0 between the gate structures. η 5 shows that the side wall of the closed-pole structure is isolated from the Ξ wall of the contact window 18 :: Γ / wall / 4, and the distance is the thickness of the insulating wall 14 in the past. In this process, 1 degree can provide sufficient isolation effect. However, with the continuous development of integrated circuit elements, the thickness of the insulation wall 14 must be reduced with i, especially when the characteristic of the insulation wall 14 is not only reduced. Difficulties increase, and easy to produce = good problems. In addition, the insulating spacer 14 having a reduced thickness also reduces the gate capability, which makes the operating conditions of the etching contact window more favorable and facilitates the production. Therefore, in order to continuously apply self-contact technology, it is necessary to seek ways to improve the above problems. In view of the card contact window technology, the purpose of the present invention is to provide an improved process for the window (SAC), which can increase the separation distance between the contact window and the gate electrode under the same size and weight. Self-aligned etch

C: \ ProgramFiles \ Patent \ 0503-3784-E.ptd page 6 5 'Explanation of the invention (4) Execution conditions of the program. The above-mentioned object of the invention is to improve the self-aligned connection (sHi electrode isolation pitch) by using an improved process, which uses a gas oxide stone evening + exhibition #S instead of the conventional silicon nitride layer as C12 / HBr The hard mask used in plasma etching of bright silicide stacks. Because the nitrogen layer: the layer will release oxygen during the etching process, and a polymer protective layer formed by photoresisting with the side wall of the metal compound 4 layer The reaction evaporates, which makes the side etch rate of the & silicide stack faster, so the horizontal size of the ^ generated will be smaller than that of the silicon oxynitride layer, and the gate electrode is added in the case of using the same size hard mask. After that, the insulating spacers formed on the sidewalls of the oxynitride layer and the metal polycrystalline silicide stack have a lower part, which can improve the isolation distance between the contact window and the gate. See s' The present invention provides an improved process for improving the separation distance between a self-aligned contact window (SAC) and a gate electrode, including the following steps: sequentially forming a gate oxide layer and a metal polycide stack on a semiconductor substrate surface Floor And a silicon oxynitride (SiON) layer; the pattern of the silicon oxynitride layer is defined by using a first photoresist layer as a hard mask; a metal complex is engraved with a C h / HBr electrode The part of the dream material worry layer that is not covered by the gas oxide fragment layer to form a gate with a horizontal size smaller than that of the silicon oxynitride layer, thereby becoming a T-shaped structure; etching the exposed part of the oxide layer of the gate; Forming an insulating spacer on the sidewall of the silicon oxynitride layer and the metal polycrystalline silicide stack; the thickness of the lower half is greater than that of the upper half; a planarizing insulating layer is formed on the surface of each layer; A second photoresist layer is coated on the surface of the insulating layer and an opening is formed by a lithography imaging procedure; using this light

C: \ ProgramFiles \ Patent \ 0503-3784-E.ptd page 7 V. Description of the invention (5) The limiting layer is used as a mask to etch and flatten the insulating layer to form a contact window, which is guided by the insulating gap wall. This leads to self-alignment on the surface of the semiconducting ship between tau-type structures. According to a preferred embodiment of the present invention, the above-mentioned metal polycrystalline silicide stack is formed by sequentially depositing a polycrystalline silicon layer and a tungsten silicide (ws) layer, and then forming the nitrogen by a chemical vapor deposition (CVD) process. Silicon oxide layer. Among them, the silicon oxynitride layer will release oxygen during the etch process of Ch / HBr, and it will react with the polymer protective layer formed by the etching photoresist layer on the side wall of the metal polycrystalline debris stack to volatilize. The side engraving rate of the metal polycrystalline silicide stack is accelerated to form the T-shaped structure described above. In addition, the planarization insulating layer is a borophosphosilicate glass (BPSG) layer. In order to make the above and other objects, features, and advantages of the present invention more obvious and easy, only a preferred embodiment is exemplified below, and it is described in detail with the accompanying drawings as follows: Brief Description of the Drawings Section 1A The cross-sectional view to Figure 1D is used to show a conventional self-aligned contact window manufacturing process using nitrided stone Xiguang as a hard cover; and the cross-sectional views of Figures 2A to 2D are used to show The manufacturing process of a preferred embodiment of the improved method of the invention. Embodiment A preferred embodiment of the improved method according to the present invention will be described below with reference to Figs. 2A to 2D. First, as shown in FIG. 2A, a semiconductor substrate 20, such as a silicon wafer, is provided. A gate dielectric layer 21 and a gate conductive layer 22 are sequentially formed on the substrate 20, for example, by a thermal oxidation process or a chemical gas first.

V. Description of the invention (6) The phase deposition process 'forms a gate oxide layer 21 with a thickness of 50 to 2000 1 on the surface of the substrate 20' and then covers a metal polycide stack 22 on the gate On the oxide layer 21, it is formed by sequentially depositing a polycrystalline layer and a tungsten silicide (WSix) layer. Next, a silicon oxynitride (si ON) layer 23 is deposited on the surface of the metal polycrystalline silicide stack 22, and a photoresist pattern 29 is used as a mask, and an etching process is performed to form the structure shown in the figure. ' It covers the portion where the transistor gate is to be formed. Secondly, referring to FIG. 2B, the above silicon oxynitride layer 23 is used as a hard mask to form a portion of the metal polycrystalline silicide stack 22 not covered by the silicon oxynitride layer 23 with a C "/ HBr plasma. -22a. For example, under the pressure of 4 mTorr, a flow of 90 ^^, and 2 seeming He-〇2 are used to generate a plasma to etch the tungsten silicide layer portion, and then the pressure is increased to 20 mTorr, and A flow rate of 80 Sccm (: 12, 12 Seem HBr, and 50 seem He was used to generate a plasma to etch the polycrystalline silicon layer portion. In the above-mentioned etching process, the photoresist pattern 29 is also not etched due to the anti-etching ability. It is etched away, and there is a partial reaction to form a polymer protective layer (not shown). In addition, unlike the conventional technology, the silicon oxynitride layer 23 also releases oxygen during the etching process, and attaches to the original element. The polymer protective layer on the side wall of the metal polycrystalline silicide stack 22 reacts to cause its volatilization and volatilization to evaporate, so that the side etching rate of the metal polycrystalline silicide stack 22 is accelerated, so the generated Policide gate The horizontal dimension of the electrode 22a will be smaller than that of the silicon oxynitride layer 23. That is, a T-like structure is formed. In other words, the method of the present invention can produce a smaller-sized

The gates increase their spacing. Wi: Come to the one shown in the figure 'and perform another etching process to remove the exposed part of the oxide layer 21' to complete the fabrication of a gate structure. Then, an insulating layer is deposited on the surfaces of the silicon oxynitride layer 23, the gate gate 22a, the gate oxide layer 21, and the substrate 20, and then an anisotropic etch-back process is performed on the insulating layer. For example, it is a reactive ion etching (RIE) process, leaving an insulating spacer 24 on the side wall of the silicon oxynitride layer and the heart gate 22 &. The exposed surface is approximately a vertical shape. The portion connected to the gate electrode 22a and the silicon oxynitride layer 23 follows a T-shaped structure and becomes a stepped shape. Then, a planarization insulating layer 25 is formed on the surface of each layer, for example, a borophosphosilicate glass is deposited. (BPSG) layer. Then, another photoresist layer 26 is coated on the surface of the planarized insulating layer 25, and an lithography process is performed to form an opening 27 'to expose the portion where the contact window is to be formed. Figure 'Using the photoresist layer 26 as a cover, etching and planarizing the insulating layer to form a contact window 28' The width of the upper half is approximately the same as the opening 27, and the lower half is due to the nitrided layer 23 and the insulation gap The protective effect of wall 2 4 To the surface of the semiconductor substrate 20 between the gate structures. Obviously, the thickness of the connecting portion of the insulating spacer 24 and the silicon nitride layer 23 in the 2D circle is approximately the same as that of the insulating spacer 1 in the 1D diagram. It is equivalent, but the part connected to? 〇1 丫 (^ (16gate 223, 1) because the size of the 16 gate 223 shrinks and the thickness increases to L, so it can effectively improve the self-alignment. The isolation distance between the quasi-contact window 28 and the side wall of the gate structure can not only ensure a good isolation effect, but also provide sufficient protection capabilities to facilitate the erosion of the contact window.

C: \ Program Files \ Patent \ 0503-3784-E.ptd page 10 5. Description of the invention (8) Engraved program. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

C: \ Program Fiies \ Patent \ 0503-3784-E.ptd page 11

Claims (1)

6. Patent application group 1. An improved process for improving self-aligned contact windows, including the following steps: Ac) and a closed electrode with a separation distance of a polycrystalline silicon silicide (pol ycide) stack on a semiconductor substrate surface, # Gate oxide layer, a metal utilization-the first-photoresist layer: the layer; as a hard mask; the pattern of the oxynitride layer is used for nitrogen: ^ 2: The 4 layers of the metal complex crystal compound are not formed by the ΪΪίΪί to form a gate having a horizontal dimension smaller than that of the oxynitride layer, thereby becoming a τ-type structure; etched the exposed portion of the gate oxide layer; An insulating spacer is on the side wall of the silicon oxynitride layer and the metal polycrystalline silicide stack. The thickness of the lower half is greater than the upper half to form a planarized insulating layer on the surface of each layer; A second photoresist layer is coated on the surface of the planarized insulating layer, and an opening is formed by a lithography imaging procedure; using the photoresist layer as a mask, the planarized insulating layer is etched to form a contact window. Guided by the insulating barrier Self-aligned to the upper surface of the semiconductor substrate between the T-shaped configuration. 2. An improved system for improving the isolation distance between the self-aligned contact window and the gate electrode as described in item 1 of the scope of the patent application, wherein the thickness of the gate oxide layer is between 50 and 200 1. 3. An improved system for improving the separation distance between self-aligned contact windows and gates as described in item 1 of the scope of patent application, wherein a polycrystalline silicon is sequentially deposited C: \ Program Files \ Patent \ 0503-3784-E.ptd 12th true, patent application layer and-WSix layer to form the metal polycrystalline silicide stack. 4. An improved process for improving the separation distance between self-aligned contact windows and gate electrodes as described in item 1 of the scope of patent application, wherein the silicon oxynitride layer is formed by a chemical vapor deposition (CVD) process. 5. As described in item 1 of the scope of the patent application, an improved process for improving the separation distance between self-aligned contact windows and gate electrodes, wherein during the cl2 / HBr plasma etching process, the silicon oxynitride layer will release oxygen elements, It reacts with the polymer protective layer generated by the etching photoresist layer on the side wall of the metal polycrystalline sulphide substrate and volatilizes, so that the side etching rate of the metal polycrystalline silicide stack is accelerated to form the T-shaped structure. 》 6. An improved process for improving the self-aligned contact window and gate electrode isolation distance as described in item 1 of the scope of the patent application, wherein the step of forming the insulating spacer comprises: depositing an insulating layer over the silicon oxynitride layer And the metal polycrystalline silicide stack on the surface; and anisotropically etching back the insulating layer 'to leave the silicon oxynitride layer and the metal polycrystalline silicide stack The part on the side wall of the layer forms an insulating spacer. 7. An improved process for improving the separation distance between self-aligned contact windows and gate electrodes as described in item 1 of the scope of the patent application, wherein the planarized insulating layer is a borosilicate glass (BPS G) layer. C: \ ProgramFiles \ Patent \ 0503-3784-E.ptd page 13