經濟部中央樣準局貝工消费合作社印製 A7 ---—__ 五、發明説明（1 ) 技街麄iq 本發明疋範圍為矽積體電路加工處理，特別是以化學方 式剝除薄膜。 背景 美國專利5,282,925揭示一種剝除氧化物之方法，其係利用 HF與氧化物在真空環境中反應，以形成siF4，然後使別匕與 NH]反應以形成六氟矽酸銨，其中六氟矽酸銨係 留在被蚀刻之表面上’因此反應係自動受限，並在相同速 率下（於最初期間後）蝕刻熱氧化物與TE〇s (四乙氧基矽烷） 氧化物。此參考資料尚未被應用至具有裂缝及/或接縫之 結構。 工業標準實務係使用HF或HF與NH3之水溶液，其具有大 為擴大裂縫及其他缺陷之已知缺點。若將厚度r之氧化層 剝除’則最初寬度只有一埃左右之裂縫，其最後寬度將為 2R ’因為此反應為同向性。利用經經氧化物充填之之之壕 溝所致之元件隔離’會產生具有中央接縫之壕溝，乃非所 要之幾何形狀。此種幾何形狀不能使用，因為在氧化物剥 除期間，接缝將大為擴大。在形成閘極之多晶矽 (polysilicon，原文簡稱poly)層蝕刻過程中，標準過度 蚀刻無法清除深裂縫或凹槽，而在底部留下多晶矽，其可 能會造成短路。漫長之過度蝕刻並不可行，因為會有傷害 閘極氧化物之風險。 標準方法有此項限制’因而不可能形成具有平滑表面之 經氧化物充填之壕溝。此表面之粗糙度導致在稍後步驟中 本紙張尺度適财家鮮（CMS > (請先閱讀背面之注意事項再填寫本頁) ci.Printed by the Central Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative A7 -----__ V. Description of the invention (1) Technical Street (iq) The scope of the present invention is the processing of silicon integrated circuits, especially chemically stripping films. BACKGROUND U.S. Patent 5,282,925 discloses a method for stripping oxides, which uses HF and oxides to react in a vacuum environment to form siF4, and then reacts with NH] to form ammonium hexafluorosilicate, of which hexafluorosilicon The ammonium acid is left on the etched surface, so the reaction system is automatically limited, and the thermal oxide and TEOs (tetraethoxysilane) oxide are etched at the same rate (after the initial period). This reference has not been applied to structures with cracks and / or seams. The industry standard practice is to use HF or an aqueous solution of HF and NH3, which has the known disadvantage of greatly expanding cracks and other defects. If the oxide layer of thickness r is peeled off ', the initial width is only about one angstrom, and the final width will be 2R' because the reaction is isotropic. Isolation of components by using trenches filled with oxides' will create trenches with a central seam, which is not the desired geometry. This geometry cannot be used because the seams will be greatly enlarged during oxide stripping. During the etching of the polysilicon (poly) layer that forms the gate electrode, standard over-etching cannot remove deep cracks or grooves, while leaving polysilicon at the bottom, which may cause a short circuit. Long overetching is not feasible because there is a risk of damaging the gate oxide. The standard method has this limitation 'so that it is impossible to form oxide-filled trenches with smooth surfaces. The roughness of this surface will cause the paper size to be suitable in a later step (CMS > (Please read the precautions on the back before filling this page) ci.
，1T 經濟部中央樣準局負工消費合作社印製 A7 ___B7______ 五、發明説明（2 ) 沈積之材料仍將殘留；意即，多晶矽可能會充填被加大之 凹槽並形成短路。而且，被加大凹槽或裂縫之存在，會產 生一個步階，當導線運行於壕溝上時，其可能會形成斷 路。 於該項技藝中，長久以來一直在尋求具有小尺寸之介電 隔離，且因此已嘗試使用具有垂直壁與高縱橫比之隔離構 件。 發明摘述 本發明係關於剝除氧化物層或其他薄膜之氣態方法，其 係採用一種化學反應，藉由增加裂缝之寬度以消除淺裂 縫、降低深裂縫之深度及使尖銳邊角圓化，而增加表面粗 糙度。 本發明使得能夠使用以前不能使用之壕溝幾何形狀，並 改良在以前已被使用之幾何形狀之良率。 國式簡輩說明 圖1A-1C顯示在剝除前及在使用不同剥除方法後，經充填 壕溝之比較β 圖2顯示先前技藝壕溝之SEM軌跡。 圖3顯示在根據本發明之方法後，相同尺寸之壕溝。 圖4A與4B顯示經阻塞凹槽之最初與最後尺寸。 圖5圖示使邊角圓化之方法。 圖6圖示圖5方法之結果。 圖7係以部份圈示、部份示意之方式，圖示一部份積體 電路。 -5- 本紙張尺度適用中國國家標準（CNS ) Α^5Τ2丨〇><297公釐）------ ---------Q! (請先W讀背面之注意事項再填寫本頁) 訂 經濟部中央樣準局負工消费合作社印褽 A7 ______B7 五、發明説明（3 ) 德隹具醴會施例乏拢明 在次微米積體電路加工處理中，具有垂直壁而供元件隔 離用之淺壕溝，與具有厚度限制及因氧化作用期間之擴散 所造成之侧向延伸之LOCOS (矽之局部氧化作用）隔離相 較’其幾何形狀之優點為此項技藝中所習知的。一旦壕溝 已形成並經經氧化物充填之時，不想要之經經經氧化物充 填之之係藉蝕刻及/或化學-機械研磨（CMP)移除，使用襯 替氮化物作為阻播層。在主動元件形成之前，必須剝除概 墊氮化物及襯墊氧化物（典型上為熱襯墊氧化物）。標準工 業實務係使用HF與NH3之水溶液剝除熱襯墊氧化物，其會 侵蚀壕溝填充物之外露氧化物表面。於CMP期間，已在壕 溝填充物中形成之裂缝將被大為擴大，在隨後加工處理期 間，其將成為多晶矽之貯放所。留在此種裂缝中之殘留多 晶矽，可能形成短路而降低晶片反率。 現在參考圖1，於圖1A中顯示隔離壕溝15之橫截面，其 具有呈公稱90〇之侧壁，在矽積體電路中被使用於隔離主動 元件。壕溝15已在矽基材1〇中藉習用乾蝕刻方法蝕刻，此 方法為熟諳此藝者所習知，譬如在”電漿蝕刻之新境界••國 際半導體，1996年7月，第152頁中所述者。熱氧化物25之薄 (20毫微米）層，已在壕溝丨5之内側上生長，以舒解應力及 使外露表面鈍化。綷後，壕溝係經經氧化物充填之，譬如 TE0S氧化物。TE0S及其他同覆性充填材料有形成孔味^傾 向，譬如高側壁角及大縱橫比之孔隙31。接縫35係標示於 壕溝之中央，其係由從侧面向外延伸之材料會合所造成。 -6- 本紙張尺度適用中國國家橾準（CNS ) Α4規格（210X297公釐） --- (請先閲讀背面之注意事項再填疼本頁), 1T Printed by the Central Procurement Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 ___B7______ V. Description of the Invention (2) The deposited material will remain; that is, polycrystalline silicon may fill the enlarged groove and form a short circuit. Moreover, the presence of enlarged grooves or cracks creates a step, and when the wire runs on the trench, it may form a break. In this technique, dielectric isolation with a small size has been sought for a long time, and therefore attempts have been made to use an isolation member having a vertical wall and a high aspect ratio. Summary of the Invention The present invention relates to a gaseous method for stripping oxide layers or other films. It uses a chemical reaction to increase the width of cracks to eliminate shallow cracks, reduce the depth of deep cracks, and round sharp edges. And increase the surface roughness. The present invention enables the use of trench geometries that were previously unusable and improves the yield of geometries that have been previously used. Brief description of the Chinese style Figure 1A-1C shows the comparison of the filled trench before stripping and after using different stripping methods. Figure 2 shows the SEM trajectory of the previous technique trench. Figure 3 shows trenches of the same size after the method according to the invention. Figures 4A and 4B show the initial and final dimensions of the blocked groove. FIG. 5 illustrates a method of rounding corners. FIG. 6 illustrates the results of the method of FIG. 5. Fig. 7 illustrates a part of the integrated circuit in a partially circled and partially schematic manner. -5- This paper size applies to Chinese National Standard (CNS) Α ^ 5Τ2 丨 〇 < 297 mm) -------- --------- Q! (Please read the Please fill in this page for the matters needing attention) Order A7 ______B7 from the Central Procurement Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. V. Description of the invention (3) The examples of the German Society for Mechanical and Electrical Equipment are not clear in the processing of sub-micron integrated circuits. Shallow trenches with vertical walls for component isolation, compared to LOCOS (localized oxidation of silicon) isolation with thickness limitation and lateral extension due to diffusion during oxidation, the advantage of its geometry is this technique Known in. Once the trench has been formed and filled with oxide, the unwanted filled oxide is removed by etching and / or chemical-mechanical polishing (CMP), using a replacement nitride as a barrier layer. Before the active element is formed, the pad nitride and pad oxide (typically a hot pad oxide) must be stripped. Standard industrial practice is the use of aqueous solutions of HF and NH3 to strip hot pad oxides, which can erode oxide surfaces outside trench fills. During the CMP, the cracks that have been formed in the trench filling will be greatly enlarged, and it will become a storage place for polycrystalline silicon during subsequent processing. Residual polysilicon left in such cracks may form a short circuit and reduce the reflectivity of the wafer. Referring now to FIG. 1, a cross-section of an isolation trench 15 is shown in FIG. 1A, which has a side wall of nominally 90 ° and is used to isolate active components in a silicon integrated circuit. The trench 15 has been etched by dry etching in the silicon substrate 10. This method is known to those skilled in the art, such as in the "new realm of plasma etching." • International Semiconductor, July 1996, page 152 The thin (20 nm) layer of thermal oxide 25 has been grown on the inside of the trench 5 to relieve stress and passivate the exposed surface. After that, the trench is filled with oxide. For example, TE0S oxide. TE0S and other cohesive filling materials have a tendency to form pores, such as pores 31 with high sidewall angles and large aspect ratios. The seam 35 is marked in the center of the trench, and it extends outward from the side. -6- This paper size applies to China National Standard (CNS) A4 (210X297 mm) --- (Please read the precautions on the back before filling this page)
經濟部中央樣準局貝工消费合作社印«. A7 B7 五、發明説明（4 ) 與別處之氧化物比較，在此種接縫處之氧化物係受壓迫， 且在水溶液方法中更易被蝕刻。接縫35可在兩側面未完全 會合之處可具有開孔，其數量級為0丨毫微米。”缺陷，，一詞 將用以一般性地表示裂縫、孔隙、界面、接縫或受壓迫之 氧化物區域。 在壕溝外侧之殘留經經氧化物充填之之30已以習用方法 移除’留下頂部表面33。有些方法，譬如CMP ("CMP :供應 商整合，應用擴展"，國際半導體，丨995年n月第74頁）會有刮 傷表面之傾向。襯墊氧化物20係接著被剝除，以製備供閘 極氧化物生長之活性區域。若表面33為平滑，則本發明所 著重之問題為保存其平滑性’而若表面33具有裂縫或刮 痕’則為降低其粗糙度。 在填充氧化物被移除且襯塾氮化物被剝除後，.係根據美 國專利5,282,925中所述之方法剥除概整氧化物，其中 Si02 + 4HF -> SiF4 + 2Η2 Ο 與 SiF4 + 2NH3 + 2HF -> (NH4 )2 SiF6 此反應係發生在Si〇2單次曝露至氨與册之周園氣體下。氧 與HF可個別在約2-3毫托與4-6毫托之分壓下，及在基材溫 度為23°C下通入反應室中。反應產物六氟矽酸銨（(NH4)2SiFd 會黏附至表面，並形成一個會妨礙反應之層。HF必須擴散 穿過六氟矽酸銨，以與氧化物反應，因此反應速率係受到 HF之擴散速率所限制，而剝除係為自動受限性。典型上， 可在合理加工處理時間30分鐘内，移除12毫微米之氧化 物。係藉由將六氟矽酸銨反應產物溶解在溶液（例如水）中 -7- 本紙張尺度適用中國國家樣準（CNS ) A4規格（210Χ297公着） (錆先(^讀背而之注*^項鼻填寫本Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative «. A7 B7 V. Description of the Invention (4) Compared with oxides elsewhere, oxides at such joints are oppressed and are more easily etched in the aqueous solution method . The seam 35 may have openings where the two sides do not fully meet, and their order of magnitude is 0 nm. "Defect," the term will be used to refer generally to cracks, pores, interfaces, joints, or areas of compressed oxides. Residues on the outside of trenches, which have been filled with oxide, have been removed by conventional methods. Lower top surface 33. Some methods, such as CMP (" CMP: Vendor Integration, Application Expansion ", International Semiconductor, n-995, p. 74) tend to scratch the surface. Liner oxide 20 series Then it is stripped to prepare an active area for the growth of the gate oxide. If the surface 33 is smooth, the important problem of the present invention is to preserve its smoothness, and if the surface 33 has cracks or scratches, it is to reduce its Roughness. After the filling oxide is removed and the liner nitride is stripped, the rough oxide is stripped according to the method described in US Patent 5,282,925, where Si02 + 4HF-> SiF4 + 2Η2 〇 and SiF4 + 2NH3 + 2HF-> (NH4) 2 SiF6 This reaction occurs under a single exposure of Si02 to the ambient gas of ammonia and hydrogen. Oxygen and HF can be individually at about 2-3 mTorr and 4-6 Into the reaction chamber at a partial pressure of millitorr and at a substrate temperature of 23 ° C The reaction product ammonium hexafluorosilicate ((NH4) 2SiFd) will adhere to the surface and form a layer that hinders the reaction. HF must diffuse through the ammonium hexafluorosilicate to react with the oxides, so the reaction rate is subject to HF The diffusion rate is limited, and stripping is automatically limited. Typically, 12 nanometers of oxide can be removed within 30 minutes of reasonable processing time. It is by dissolving the reaction product of ammonium hexafluorosilicate In solution (such as water) -7- This paper size applies to China National Standard (CNS) A4 specification (210 × 297) (着 先 (^ read the back and note * ^ item)
經濟部中夬棣準局員工消費合作社印製 A7 ^>___B7 五、發明説明（5 ) 以將其移除，或將晶圓加熱至大於l〇〇°C之溫度以將其移 除。 圖1B顯示在使用HF水溶液之習用剝除方法後之相同橫截 面。熱氧化物已被剝除，且有較大量之TE〇s已被蝕刻，因 為TEOS比熱氧化物更容易蝕刻。被稱為表面缺陷之開孔 37 ’已在熱氧化物壕溝内襯25與壕溝填充物30之交點處之 裂縫26處形成。溶液係滲透進入界面處之小開孔中，並以 同向性方式蝕刻彼等，而在頂部處造成與其深度一樣寬或 更寬之表面缺陷。同樣地，溶液會沿著接縫35滲透至開孔 内’並使其擴大。當開孔擴大至孔隙3丨時，HF會侵蝕孔隙 之底部與侧面。 對照而言’圖1C係顯示根據本發明之剥除操作後之相同 壕溝。TEOS 30與内襯25已被蝕刻至與熱氧化物2〇相同之深 度’因為此方法會達到極限速率，其對TE〇s、拉緊之TE〇s 及熱氧化物而言皆相同。接縫35與界面26並未被侵蝕。在 此實例中，孔隙31並未外露且表面仍然平滑。 圖2為先前技藝壕溝之掃描式電子顯微鏡（SEM)顯微照片 之軌跡，此壕溝之尺寸為深0.4微米及寬〇5微米，其縱橫 比為0.8,此先前技藝因良率不佳而不實用。熱氧化物内襯 已在各側面上經蝕刻一個步階，且TE〇s中央接縫已被蝕刻 至超過其餘丁 EOS深度之兩倍。於中央之接縫已被侵蚀且形 成凹槽，其遠較i真充材料本體為⑨。熟諸此技藝者明瞭此 種步驟會減損良率。對照而言，圖3為根據本發明之經剝 除壕溝之對應SEM，其顯示内檷盥诚*札p t 門砚興填无物已被蝕刻至相同 -8- 本紙張^度適用中國國家標準（CNS ) A4規格（----- (請先閲讀背面之注意事項再填寫本頁) 訂 良 A7 B7 五、發明説明（6 ) 深度，且界面與接縫並未被侵蝕。 同樣地，HF溶液會侵蝕CMP步驟期間所形成氡化物中之 裂縫或斷裂處。此種斷裂處僅具數埃之寬度，但HF溶液將 以同向性方式蝕刻其侧面及底部。由於底部係在與表面才目 同之速率下經蝕刻，故裂缝之深度不會改變。但是，其寬 度會從一埃或2埃，擴大至從表面移除材料量之兩倍。 先前技藝壕溝具有之缺點為其縱橫比典型上低於〇 8，且 側面角度係低於75。，此係基於良率之考量。若切割較陡山肖 之壕溝，則在中央處之孔隙與接縫會導致良率太低，以致 無法為商業上所接受。於侧壁角度上之此項限制，需要嚴 密控制蝕刻程序參數方可達成，而導致比所需者為小之程 序限幅。再者，對於一些壕溝蚀刻方法而言，侧壁之角度 及對於低縱橫比之限制，迫使壕溝之寬度比起若沒有接縫 侵蝕問題時所能夠形成之最小寬度為寬。 經濟部中央樣準局員工消費合作社印製 (請先W讀背面之注項再填寫本頁) 於先前技藝中，HF襯墊氧化物剥除 '犧牲性氧化物剝除 及氮化物除釉之步驟，會在壕溝中移除約60毫微米之tE0S 氧化物，此係由於比起熱襯墊氧化物，在TEOS中有較大蝕 刻速率，及由於過度蝕刻以確保概整氧化物全部被移除所 致。使用本發明之方法，在表面下方大於30毫微米之缺 陷，將不會外露，因為本發明之方法在剝除相同之三層 時，僅移除約30毫微米之壕溝填充物。於先前技藝方法 中，此種缺陷會外露且被侵蝕。 於先前技藝中，通常係使經經氧化物充填之之樣溝退 火，以降低氧化物填料中之應力，及因此降低蝕刻速率。 -9- 本紙張尺度^用中國國家樣準（〇奶）六4規格（2丨0>：297公釐) 經濟部中央樣準局貝工消费合作社印装 A7 ___ B7 五、發明説明（7 ) 使用本發明’僅需要較少或甚至不需要退火。 現在參考圖4A，其係顯示一個淺凹槽，例如長度為毫 微米，根據本發明，其寬度將稍微地擴大，但深度會降 低。在填充氧化物30中之裂縫或凹槽6〇，具有由括弧η所 示之最初寬度％，及由括弧65所示之最初深度q。當氧化 物被蝕刻時，於壕溝侧面與底部上之氧化物，將被移除至 括孤62所示之深度。已發現在根據本發明之剝除方法期間 所形成之反應產物六氟矽酸銨層，其厚度為被移除氧化物 厚度之三倍（3x)。因此’圖示用以阻塞凹槽6〇所需要反應 產物厚度I括弧64，將各為括弧62長度之兩倍，且長度62 之量係為％/4。於是可立即明瞭，凹槽6〇之最終寬度％， 將接近WfOJWi，或l_5Wi。實際寬度將稍微大於此數值， 因為π氟矽酸銨並非具不透性，且在凹槽被阻塞後，HF將 持續與氧化物反應，但與在凹槽頂部相較，在凹槽之底部 係於緩慢得多之速率下進行。同樣地，裂縫之深度將不會 如先前技藝一樣保持恒定，而是將會降低。 在凹槽經阻塞後，於底部之蚀刻速率，將受擴散過凹 槽頂部之7V氟矽酸銨柱塞物之限制。最終深度化將稍微低 於：Df=Di+Wi/4-R，其中民為自表面移除之氧化物厚度。 當R大於或等於Wj/4時，凹槽之全長係皆被阻塞，且進一 步之蝕刻會減小凹槽之深度。凹槽之基底係在R = Wi/4之前 被阻基，因為從接近基底之側壁所延展之反應產物會在空 間上重疊，在充填至頂部之前充填基底。若R〉& +评丨/4， 則凹槽將被消除。 -10- 本紙張尺度適用中國國家標率（CNS > A4规格（210X297公着） (請先Μ讀背面之注f項再填寫本頁) α. 订 Α7 Β7 經濟部中央樣準局貝工消费合作社印製 五、發明说明（8 ) 現在參考圖4B，其係顯示藉由應用此方法至最初寬度為 約0.1毫微米之裂縫、接縫或狹窄凹槽，所造成之特性形 狀。當HF在表面上及在裂缝中向下蝕刻時，本發明方法會 留下一種特性形狀，其中缺陷之底部會極快速地閉合，且 在底部形成一個尖銳點（數十分之一毫微米），同時在缺陷 頂部之邊角係如下文所述被圓化（具有數量級為1〇毫微米 之曲率半徑），因此缺陷頂部遠較底部為寬。若裂縫並非 垂直’或若其比閘極RIE過度蝕刻為深，則此傾斜側壁具 有之另一項優點是，在用以界定電晶體閘極輪廓之異向性 蝕刻程序期間，多晶矽更容易自裂缝中消除，因此在剝除 襯墊氧化物後仍然留下之缺陷，於多晶矽蝕刻步驟後只 有較少之多晶矽留在其中。而且，在底部處較少產生蝕刻 作用’會降低底部導致其下方導體短路之機會。 在壕溝具有氮化物内襯之情況中，此内襯係在襯墊氮化 物經移除期間内，凹陷進氧化物表面下方。氧化物剝除方 法會使氮化物内襯外露，因此其會突出於氧化物表面上 方。於是其可在稍後之蝕刻步驟期間收集電荷，或在懸垂 之氮化物下方捕集多晶矽。本發明方法不會使氧化物凹陷 至低於氮化物表面處，因為氧化物蚀刻係終止於因氮化物 内襯凹陷所造成之裂隙底部。 現在參考圖5，其係顯示一個步階，譬如在壕溝中之 TEOS填充物邊緣處，表為實線74者。線條66、68及71係表 π反應產物之内部界限，而線條67、69及72係表示若反應 係垂直於最初表面進行時之反應產物外部表面。在此擊假 -11 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先《讀背面之注f項再填寫本頁) 訂 A7 B7 五、發明説明（9 ) 設情況中，邊角不會被圓化，而是保持尖銳。事實上，此 反應並不具方向性，且在外部邊角之區域75係被圓化，直 到於邊角上產生有限厚度之反應產物為止。在内部邊角之 區域73係經保護，因為來自兩個表面之反應產物會阻塞深 入邊角中之擴散作用。其結果係以圖6中之線條％顯示， 說明經圓化之邊角。 現在參考圖7，其係以部份示意、部份圖示形式顯示 藉助於本發明所形成積體電路之一部份。基材1〇具有兩個 經明確圖示電路之電晶體，而電路之其餘部份係概要地示 意^標識為"邏輯”之方塊85。為方便起見，被覆佈植襯 墊氧化物及襯墊氮化物之形成等標準預備步驟將簡要地 稱為製備基材。具有閘極62與側壁6〗之兩個電晶體，係 被根據本發明所建構之壕溝15隔離。左邊電晶體之汲極 63，係藉由局部導線72連接至右邊電晶體之源極64，該導 線係藉由氧化物74與第一步階金屬構件82隔離。氧化㈣ 具有根據本發明處理之頂部表面75，以使表面平滑五藉以 降低短路之危險。便起見，㈣導線與步階間電介質 經濟部中央標準局負工消费合作社印裝 (請先聞讀背面之注意事項再填寫本頁) 之沈積與構圖、形成接點等標準後段内襯步驟將被稱為 完成此電路。 根據本發明方法，在23t：下對於氧化物移除之極限厚度 為約20毫微米。若需要’可藉由在高於赋下加熱晶圓： 逐出一部份六氟矽酸銨，然後持續進行而增加此厚度。襯 墊氧化物所形成之厚度較佳係小於該量。 雖然本發明係以單一較佳具體實施例加以說明但熟諳 -12- 卜紙張尺纽財目@家標準（CNS ) A4%# ( 210X297公釐- A7 B7 五、發明説明（10 ) 此藝者將明瞭本發明並不受限於M〇s技術，而是可與雙極 電晶體一起使用。同樣地，其並不受限於經經氧化物充填 之之之隔離壕溝，而是可與含有裂縫之其他層一起實施， 該層之材料係於一方法中經移除，其可為會留下具有擴大 體積之反應產物之方法，或可為在隨文所附申請專利範圍 之精神與範圍内之其他具體實施例。例如，可藉Si〇2之形 成 '及Si〇2之隨後移除而移除矽。另外之實例為，可在金 屬沈積之前使用此方法，藉由減少或排除可能充填金屬並 造成短路之缺陷，以改善其良率。亦可使用其他方法，以 產生NH3與HF，譬如從已知先驅物，在電漿放電中形成 NHi 及 HF。 (請先W讀背面之注意事項再填寫本页) 11 經濟部中央標準局負工消費合作社印衮 本紙張尺度適用中國國家標準（CNS >A4規格（210X297公釐）Printed on A7 ^ > ___B7 by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs. 5. Description of Invention (5) to remove it, or heat the wafer to a temperature greater than 100 ° C to remove it. Figure 1B shows the same cross section after a conventional stripping method using an aqueous HF solution. Thermal oxide has been stripped and a larger amount of TE0s has been etched because TEOS is easier to etch than thermal oxide. Openings 37 'called surface defects have been formed at the cracks 26 at the intersections of the thermal oxide trench liner 25 and trench filler 30. The solution penetrates into small openings at the interface and etches them isotropically, causing surface defects at the top that are as wide or wider than their depth. Similarly, the solution penetrates into the openings ' along the joint 35 and enlarges it. When the opening expands to pore 3, HF will erode the bottom and sides of the pore. In contrast, Fig. 1C shows the same trench after the stripping operation according to the present invention. TEOS 30 and liner 25 have been etched to the same depth as thermal oxide 20, because this method will reach the limit rate, which is the same for TE0s, tensioned TE0s, and thermal oxides. The joint 35 and the interface 26 are not eroded. In this example, the pores 31 are not exposed and the surface is still smooth. Figure 2 shows the trajectory of a scanning electron microscope (SEM) photomicrograph of a trench of the previous technique. The trench is 0.4 micrometers in depth and 0.05 micrometers in width, and its aspect ratio is 0.8. This prior technique is not good because of poor yield. practical. The thermal oxide lining has been etched one step on each side, and the TE0s central seam has been etched to more than twice the depth of the rest of the EOS. The seam in the center has been eroded and formed a groove, which is far more concrete than the body of i-filling material. Those skilled in the art know that this step can detract from yield. In contrast, FIG. 3 is a corresponding SEM of the stripped trenches according to the present invention, which shows that the internal toilets have been etched to the same extent. The paper is compliant with Chinese national standards ( CNS) A4 specifications (----- (Please read the notes on the back before filling out this page) Order A7 B7 V. Description of the invention (6) Depth, and the interface and joints are not eroded. Similarly, HF The solution will erode cracks or breaks in the halide formed during the CMP step. Such breaks are only a few angstroms wide, but the HF solution will etch its sides and bottom in an isotropic manner. Since the bottom is attached to the surface After etching at the same rate, the depth of the crack will not change. However, its width will increase from one angstrom or two angstroms to twice the amount of material removed from the surface. The disadvantage of the prior art trench is its aspect ratio It is typically lower than 0, and the side angle is lower than 75. This is based on the yield consideration. If you cut a trench with steep hills, the pores and joints in the center will cause the yield to be too low, so that Unacceptable commercially. In terms of sidewall angle Restrictions can only be achieved by tightly controlling the parameters of the etching process, which results in a smaller program limit than required. Furthermore, for some trench etching methods, the angle of the sidewalls and restrictions on low aspect ratios force the trench The width is wider than the minimum width that can be formed if there is no problem of seam erosion. Printed by the Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs (please read the note on the back before filling out this page) In previous techniques, HF liner oxide stripping 'sacrificial oxide stripping and nitride deglazing steps will remove about 60 nanometers of tE0S oxide in the trench. There is a large etch rate, and due to over-etching to ensure that the rough oxide is completely removed. Using the method of the present invention, defects greater than 30 nm below the surface will not be exposed because of the method of the present invention When stripping the same three layers, only about 30 nanometers of trench filler is removed. In previous techniques, such defects would be exposed and eroded. In previous techniques, oxidation is usually performed The filled sample grooves are annealed to reduce the stress in the oxide filler, and therefore the etching rate. -9- This paper size ^ uses the Chinese national standard (〇 奶) 6 4 size (2 丨 0 >: 297 mm ) Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7 ___ B7 V. Description of the invention (7) Use of the invention 'requires little or no annealing. Now refer to FIG. 4A, which shows a shallow groove, For example, the length is nanometers. According to the present invention, the width will be slightly enlarged, but the depth will be reduced. The cracks or grooves 60 in the filled oxide 30 have an initial width% indicated by the bracket η, and by the bracket The initial depth q shown at 65. When the oxide is etched, the oxide on the sides and bottom of the trench will be removed to the depth shown in brackets 62. It has been found that the thickness of the reaction product ammonium hexafluorosilicate layer formed during the stripping method according to the present invention is three times (3x) the thickness of the removed oxide. Therefore, the "I" block thickness 64 of the reaction product required to block the groove 60 will be twice the length of the bracket 62, and the amount of the length 62 will be% / 4. It can be immediately understood that the final width% of the groove 60 will be close to WfOJWi, or 1_5Wi. The actual width will be slightly larger than this value, because π ammonium fluorosilicate is not impermeable, and after the groove is blocked, HF will continue to react with the oxide, but compared to the top of the groove, at the bottom of the groove At a much slower rate. Similarly, the depth of the cracks will not remain constant as in the previous art, but will decrease. After the groove is blocked, the etching rate at the bottom will be limited by the 7V ammonium fluorosilicate plunger that diffuses through the top of the groove. The final depth will be slightly lower than: Df = Di + Wi / 4-R, where the thickness of the oxide removed from the surface. When R is greater than or equal to Wj / 4, the entire length of the groove is blocked, and further etching will reduce the depth of the groove. The substrate of the groove is blocked before R = Wi / 4, because the reaction products extended from the side walls close to the substrate will overlap in space, filling the substrate before filling to the top. If R> & + comment 丨 / 4, the groove will be eliminated. -10- This paper size applies to China's national standard (CNS > A4 size (210X297)) (please read the note f on the back before filling in this page) α. Order Α7 Β7 Printed by the Consumer Cooperative 5. Description of the invention (8) Reference is now made to Figure 4B, which shows the characteristic shape created by applying this method to cracks, seams or narrow grooves with an initial width of about 0.1 nm. When HF When etching down on the surface and in cracks, the method of the present invention leaves a characteristic shape in which the bottom of the defect is closed very quickly and a sharp point (tenths of a nanometer) is formed at the bottom, at the same time The corners on the top of the defect are rounded as described below (with a radius of curvature of the order of 10 nanometers), so the top of the defect is much wider than the bottom. If the crack is not vertical 'or if it is over-etched than the gate RIE Another advantage of this sloping sidewall is that polycrystalline silicon is easier to remove from cracks during the anisotropic etching process used to define the transistor gate profile, so it remains after stripping of the pad oxide For the following defects, only a small amount of polycrystalline silicon remains in the polycrystalline silicon after the etching step. Moreover, the occurrence of less etching at the bottom will reduce the chance of the bottom causing the conductors below it to be short-circuited. In the case of a trench with a nitride lining This liner is recessed under the oxide surface during the nitride removal of the liner. The oxide stripping method will expose the nitride liner, so it will protrude above the oxide surface. Charges are collected during later etching steps, or polycrystalline silicon is trapped under the overhanging nitride. The method of the present invention does not dent the oxide below the nitride surface because the oxide etch is terminated by the depression of the nitride liner The bottom of the crack caused. Now refer to Figure 5, which shows a step, for example, at the edge of the TEOS filler in the trench, shown as a solid line 74. Lines 66, 68, and 71 are the internal boundaries of the π reaction product The lines 67, 69, and 72 indicate the external surface of the reaction product when the reaction proceeds perpendicular to the original surface. Here is a fake-11-This paper applies to China Home Standard (CNS) A4 specification (210X 297 mm) (please read "Note f on the back side before filling out this page) Order A7 B7 V. Description of the invention (9) In the case, the corners will not be rounded, Instead, it remains sharp. In fact, the reaction is not directional, and the area 75 in the outer corner is rounded until a reaction product of limited thickness is produced on the corner. The area 73 in the inner corner is warped. Protection, because the reaction products from the two surfaces can block the diffusion effect deep into the corners. The results are shown as the line% in Figure 6, illustrating the rounded corners. Now refer to Figure 7, which is shown in sections Schematic and partial diagrams show a part of the integrated circuit formed by means of the present invention. The substrate 10 has two transistors with clearly illustrated circuits, and the rest of the circuit is schematically indicated ^ For " Logic "box 85. For convenience, the standard preparative steps, such as the formation of blanket oxides and the formation of pad nitrides, will be briefly referred to as preparing substrates. The two transistors having the gate electrode 62 and the side wall 6 are isolated by the trench 15 constructed according to the present invention. The drain 63 of the left transistor is connected to the source 64 of the right transistor by a local wire 72, which is isolated from the first-step metal member 82 by an oxide 74. Hafnium oxide has a top surface 75 treated in accordance with the present invention to smooth the surface thereby reducing the risk of short circuits. For the sake of convenience, standard post-line lining steps such as deposition and patterning, formation of contacts, etc., printed by the Consumers Cooperatives of the Central Standards Bureau of the Ministry of Economics and Dielectrics between Steps and Dielectrics Will be called to complete this circuit. According to the method of the present invention, the limiting thickness for oxide removal at 23t: is about 20 nm. If necessary, the thickness can be increased by heating the wafer at a temperature above: expelling a portion of the ammonium hexafluorosilicate, and then continuing. The thickness of the pad oxide is preferably less than this amount. Although the present invention is described with a single preferred embodiment, it is familiar with -12- Pu paper rule New Account @ 家 标准 (CNS) A4% # (210X297 mm-A7 B7 V. Description of the invention (10) This artist It will be understood that the invention is not limited to Mos technology, but can be used with bipolar transistors. Similarly, it is not limited to isolation trenches filled with oxides, but can be used with The other layers of the crack are implemented together. The material of this layer is removed in a method, which can be a method that will leave a reaction product with an enlarged volume, or it can be in the spirit and scope of the scope of the attached patent application Other specific embodiments within. For example, silicon can be removed by the formation of Si02 and subsequent removal of Si02. Another example is that this method can be used before metal deposition by reducing or eliminating possible Fill metal and cause short-circuit defects to improve its yield. Other methods can also be used to generate NH3 and HF, such as forming NHi and HF in plasma discharge from known precursors. (Please read the back of the first (Notes to fill out this page) 11 Ministry of Economic Affairs Bureau of Standards negative consumer cooperative work printed in this paper Dagon scale applicable Chinese National Standard (CNS > A4 size (210X297 mm)