經濟部中央揉準局負工消費合作社印製 A7 B7 五、發明説明（丨） 發明背景 (1) 發明範圍 本發明係有關於一種雙極性接面電晶體之結構及其形成方法，此 ，結構的雙極性面電晶體具有峰子植續形成料質基極(extrfnsic base)，本質基極(intrinsic base)和基極連結(baselink)等，以及由 雜質擴散所形成的射極(emitter)及集極(c〇liector)。 (2) 相關技藝之描述 美國專利US 5,592,017(Johnson)描述雙極性接面電晶體結構及其 形成方法，在基極電極之侧壁上形成一摻有雜質可導電之空隔e 以提供形成基極連結之掺雜源，接著完成本質基極部分、射極部分及 集極部分。 美國專利US 5,593,905 (Johnson等人)描述雙極性接面電晶體結構 及其形成方法，基極連結(base link)經由一層基極連結擴散源擴散而 得，外質基極(extrinsic base)部分經由摻雜複晶基極電極擴散而得。 美國專利US 5,064,774(Pftester)描述-種形成自我對準(感aligned) 雙極性接面電晶體的方法，其在已被姓刻形成之射極側壁上形成空隔 極及外質基極部分乃由推雜形成，金屬矽化物形成 於外質基極及射極上。 美國專利US 5，134,454 (Neudeck等人)描述一種形成雙極性接面電 日日體之方，，它可用集極來自我對準基極，用基極來自我對準射極。 美國專利US 5,631，495 (Dunn等人)描述-種高效能 performance)集極性電晶體，它改善了繞線的方式，此電晶體 多重(multiple)接觸窗(contact)的基極接觸窗結構。 發明的綜合說明 雙極性接面電晶體(B】T)經常運—IC上 及場效刪整合在同—基板上。雙極性接_體興元件°】^3 基極(intrinsic base)、外質基極(extrinsic base)及基極& 極連結斜質基滅本質基極連結在 降低接雙層複晶綠鱗赌雜與基 (請先閲讀背面之注意事項再填寫本頁) 装· 訂 3 經濟部中央梂準局貝工消費合作社印装 五、發明説明（α ) 本較-子植人絲餅質基極、 找+m的、另一主要目的乃提供不需要使用金屬石夕化物來作為與射 tSiT刀的電性連結，且包含外質基極 '本錄極以及基極連結 的雙極性接面電晶趙β 這些目的乃藉由在有摻雜之石夕基板上之第二介電層之邊牆 (sidewalls)形成第一介電層圖樣㈣㈣所達成，接著用第一道離子植 入以形成外質基極，再移去第二介電層空隔(spacer)，接著進行第二 道ί子，：入以形成基極連結(baselink)，再移去第一介電層圓樣(Pattern) 使件第二道離子植入形成本質基極(intrlnsic bas.e)區域。 、有掺雜之複晶矽電極圖樣形成於本質基極與集極區域，此摻雜 之複晶=13摻雜有磷(p)或砷(As)，此電晶體結構係形成於n型磊晶 或N井區上，有換雜之複晶石夕電極圖樣之雜質(impurity)經由加熱擴散 至本質基極以形成射極’擴散至集極接觸區域以形成低電阻接觸，電 晶體結構也可以形成在P型磊晶上或P井區上。 圖式之簡要說明 圖1乃在P型基板上形成N型磊晶層或P型基板上形成N型井區 之剖面圖’N+埋層形成在n型磊晶層或N型井區内，N+集極形成在 N型磊晶層或n型井區内，接著再形成場氧化隔離區域、一層氧化墊 層、一層未摻雜複晶矽、一層氮化矽和有圖樣之光阻。 圖2係圖1經過氮化石夕蝕刻之剖面圖。 圖3為圖2結構之俯視圖。 圖4為圖2再沈積一層介電層之剖面圖。 圖5係圖4之介電層被回钱刻(back etched)以形成介電層空隔 (spacers) ° 圖6係圖5經過離子植入形成外質基極(extrinsic base)之剖面圖。 圖7為圖6之介電層空隔(spacer)被姓刻掉後，再經離子植入以形 成基極連結之剖面圖。 良紙張尺度適用中國國家標準（CNS ) A4規格（21〇><297公釐） —IL 一 J1..-------「装-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央樣準局貝工消費合作社印裝 五、發明説明（3 ) 一 囷8為圖7的俯視圖。 ，9為圖7之未被氮化石夕覆蓋之未掺雜複晶石夕被氧化之剖面圖。 ? 10為圖9中氮化石夕及未被氧化之複晶發被移去，再經由離子植 入形成基極及選擇性植入集極。 圖11為將圖1〇之墊層移去，再沈積一層捧雜複晶梦，再一 光阻圖樣之剖面圖。 圖12為圖11經過複晶蝕刻去除光阻，再加熱以形成射極及集極 接觸之剖面圖。 圖13描述圖π形成接觸窗(contact)至外質基極及射極之複晶矽、 集極之複晶矽之剖面圖。 發明之較佳實施例 圖1至圖13係本發明之雙極性接面電晶艎的較佳實施例及形成此 ，極性接面電晶體之方法《圖丨描述了在p型基板1〇上形成N型磊 晶層8 \在N型磊晶層8上形成N+埋層9和N+集極15。在N型磊晶 ，8上形成p型井區η來提供元件間的隔離，在p型基板1〇上之N 型磊晶層可被N型井區取代，而N+埋層9和N+集極15形成於N型 井區内’圖1中之場氧化區域12係利用矽局部氧化(L〇c〇s)技術形 成’在此實施例申之墊氧化層之厚度介於ι〇〇人至24〇人之間。 本實施例是一個npn雙極性接面電晶體，但這樣的技術也可完全 ，用到pnp雙極性接面電晶體，在此情況下n型基板1〇有一p型磊 晶層8形成’而p+埋層9和P+集極15形成於p型磊晶層8之内，且 在P型磊晶層8内形成之N型井區提供了元件間之隔離，在N型基板 10上之P型磊晶層可被P型井區取代，而p+詹層9和p+集極15形成 於P型井區内》 接著形成厚度介於ΙΟΟΑ至250人之第一未摻雜複晶矽層16，此薄 的未摻雜複晶矽層最後會被氧化掉，將不會出現在自我對準單層複晶 雙極性接面電晶體結構内。在薄複晶矽層16上形成第一介電層18， 在本f施例中’第一介電層18是氮化矽(Si3N4)，厚度介於1600人至 2400A之間’且利用低壓氣相沉積法沉積，並在第一介電層18上形成 一層有圖樣的光阻以造成第一光阻圖樣20及第二光阻圖樣21。 本紙張尺度適用中國國家榇準（CNS)从祕（2數297公兼） —S — i-;-------「裝-- (請先閱讀背面之注意事項再填寫本頁)Printed by A7 B7 of the Consumers Cooperative of the Central Bureau of the Ministry of Economic Affairs. 5. Description of the invention (丨) Background of the invention (1) Scope of the invention The invention relates to a structure of a bipolar junction transistor and a method for forming the same. The bipolar surface transistor has peaks that continue to form an extrfnsic base, an intrinsic base and a baselink, etc., and an emitter and a collector formed by impurity diffusion. Pole (coliector). (2) Description of related arts US Patent No. 5,592,017 (Johnson) describes the bipolar junction transistor structure and the method for forming the same, forming an electrically conductive spacer e doped with impurities on the side wall of the base electrode to provide a forming base The doped source connected to the electrodes, then the essential base part, emitter part and collector part are completed. U.S. Patent No. 5,593,905 (Johnson et al.) Describes the bipolar junction transistor structure and its formation method. The base link is diffused through a layer of base connection diffusion source, and the external base is partially passed through The doped multiple crystal base electrode is obtained by diffusion. U.S. Patent No. 5,064,774 (Pftester) describes a method for forming a self-aligned bipolar junction transistor, which forms a hollow spacer and an exoplasmic base portion on the side wall of the emitter that has been carved by the last name. Formed by doping, metal silicide is formed on the exoplasmic base and emitter. U.S. Patent No. 5,134,454 (Neudeck et al.) Describes a method for forming a bipolar junction solar heliosphere, which can be used to self-align the base with the collector and the emitter with the base. U.S. Patent No. 5,631,495 (Dunn et al.) Describes a high-performance performance polarized transistor that improves the way windings are made. This transistor has multiple contact windows with a base contact window structure. Comprehensive description of the invention The bipolar junction transistor (B) T is often integrated on the IC and the field effect is integrated on the same substrate. Bipolar junction_body element °】 ^ 3 base, external base, base & pole connection Gambling Miscellaneous (Please read the notes on the back before filling out this page) Packing and ordering 3 Printing by the Central Laboratories Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 5. Description of the invention (α) Electrode, looking for + m, the other main purpose is to provide a bipolar junction that does not require the use of a metal oxide as an electrical connection with the tSiT knife, and includes an exoplasmic base, a recording electrode, and a base connection. Crystal Zhao β These objectives are achieved by forming the first dielectric layer pattern on the side walls of the second dielectric layer on the doped stone substrate, and then using the first ion implantation to Form the exoplasmic base, and then remove the second dielectric layer spacer, followed by a second pass: insert to form a baselink, and then remove the first dielectric layer circle sample ( Pattern) The second ion implantation of the part forms the intrinsic base (intrlnsic bas.e) region. The doped complex silicon electrode pattern is formed in the essential base and collector regions. This doped complex = 13 is doped with phosphorus (p) or arsenic (As). This transistor structure is formed in n-type On the epitaxial or N-well area, the impurity of the mixed polycrystalline stone electrode pattern is diffused by heating to the essential base to form an emitter 'and diffuse to the collector contact area to form a low-resistance contact. The transistor structure It can also be formed on P-type epitaxy or P-well region. Brief description of the drawings FIG. 1 is a cross-sectional view of forming an N-type epitaxial layer on a P-type substrate or an N-type well area on a P-type substrate. 'N + buried layer is formed in the n-type epitaxial layer or N-type well area. The N + collector is formed in an N-type epitaxial layer or an n-type well region, and then a field oxidation isolation region, an oxide pad layer, an undoped polycrystalline silicon layer, a silicon nitride layer, and a patterned photoresist are formed. FIG. 2 is a cross-sectional view of FIG. 1 after nitride stone etching. FIG. 3 is a top view of the structure of FIG. 2. FIG. 4 is a cross-sectional view of another dielectric layer deposited in FIG. 2. FIG. 5 is a cross-sectional view of the dielectric layer of FIG. 4 being back etched to form dielectric spacers. FIG. 6 is a cross-sectional view of FIG. 5 in which an extra base is formed by ion implantation. Fig. 7 is a cross-sectional view of the dielectric layer spacer of Fig. 6 after being engraved and then subjected to ion implantation to form a base connection. Good paper size applies to China National Standard (CNS) A4 specification (21〇 > < 297mm) —IL-J1 ..------- "Packing-(Please read the precautions on the back before filling (This page) Printed by the Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 5. Description of the Invention (3) 8 is a top view of FIG. 7, and 9 is an undoped complex crystal that is not covered by the nitride of FIG. 7. The cross section of Shi Xi being oxidized. 10 is the nitrided Shi Xi and the non-oxidized polycrystalline hair in Figure 9 is removed, and then the base and selective implant collector are formed by ion implantation. Figure 11 is a diagram The pad of 10 is removed, and a layer of mixed polycrystalline dream is deposited, and then a cross-sectional view of the photoresist pattern is shown. Figure 12 is the photoresist removed by polycrystalline etching in Figure 11 and then heated to form the emitter and collector contacts. Fig. 13 is a cross-sectional view of the complex crystal silicon formed by the contact formation of the contact window (external contact) to the exoplasmic base and emitter and the collector of the complex crystal. Fig. 1 to Fig. 13 are the present invention. A preferred embodiment of the invention of a bipolar junction transistor and the method for forming the same, FIG. 丨 describes the formation of an N-type on a p-type substrate 10 Epitaxial layer 8 \ An N + buried layer 9 and an N + collector 15 are formed on the N-type epitaxial layer 8. A p-type well region η is formed on the N-type epitaxial layer 8 to provide isolation between components, and on the p-type substrate 1 The N-type epitaxial layer on 〇 can be replaced by an N-type well area, and the N + buried layer 9 and N + collector 15 are formed in the N-type well area. The field oxidation region 12 in FIG. 1 uses silicon local oxidation (L〇 COS) technology to form 'the thickness of the pad oxide layer applied in this embodiment is between ι 00 and 24 0. This embodiment is an npn bipolar junction transistor, but such technology can also be used. Completely, a pnp bipolar junction transistor is used. In this case, a p-type epitaxial layer 8 is formed on the n-type substrate 10, and a p + buried layer 9 and a P + collector 15 are formed in the p-type epitaxial layer 8. In addition, the N-type well region formed in the P-type epitaxial layer 8 provides isolation between the components. The P-type epitaxial layer on the N-type substrate 10 can be replaced by the P-type well region, and the p + layer 9 and p + The collector 15 is formed in the P-type well region. Then, a first undoped polycrystalline silicon layer 16 having a thickness of 100-250 is formed. This thin undoped polycrystalline silicon layer will be oxidized and will not Self-aligned monolayer In the bipolar junction transistor structure, a first dielectric layer 18 is formed on the thin polycrystalline silicon layer 16. In this embodiment, the first dielectric layer 18 is silicon nitride (Si3N4), and the thickness is between 1600 to Between 2400A 'and deposited by low-pressure vapor deposition, and a patterned photoresist is formed on the first dielectric layer 18 to cause the first photoresist pattern 20 and the second photoresist pattern 21. This paper scale applies to China National Standards of Standards (CNS) from the secret (2 numbers and 297 public) —S — i-; ------- "install-(Please read the precautions on the back before filling this page)
，1T —— 經濟部中央棣準局負工消费合作社印«. A7 B7 五、發明説明（4·) 介dm’示’利用乾侧技術餘刻第一介電層以形成第一 f第一圖樣17及第一介電層第二圖樣19，且移去光阻，第-介 &楚樣17及第—介電廣第二圖樣19均有邊牆(sidewaiis)。圖3 ISM ""ί??第一圖樣17和第一介電層第二圖樣19位置的俯視圖， ，3之虛線為場氧化隔離區域12之周圍，此部分之基一第一元 、第二元件區、第三元件區及集區接觸區，第—耕區是基板中 在介電層第一圖樣17之正下方區域，集極接觸區乃是基板中第 二介電層第二圖樣19之正下方區域和它周圍之位置，第二元件區與 第三元件區將在稍後敘述之。 ^ 如圖4所示，一厚度介於2500至4〇〇〇人間的第二介電層22(例如 二氧化矽)沉積於此結構内。圖5為利用乾姓刻全面蝕刻第二介電層以 在第一介電層第一圖樣17及第一介電層第二圖樣19之邊牆(sidewall) 亡形成一第二介電層空隔(spacer)22，之前所提及的第二元件區乃位於 第二介電層空隔22之正下方區域。 圖6中’外質基極(extrinsicbase)區域26乃是利用第一道離子植入 所形成，利用第一介電層第一圖樣17、第一介電層第二圖樣19以及 $—介電層第一圖樣17及第一介電層第二圖樣19之空隔(spacer)22、 場氧化區域12作為第一道離子植入的阻隔(mask)，在本實施例中N 型磊晶層或N型井區之npn雙極性接面電晶逋中，第一道離子植入24 之離子為 B1丨或 BF2，植入量從 3 X 1015i〇ns/cm2至 7X 1015i〇ns/cm2，, 1T ——Printed by the Consumers ’Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs«. A7 B7 V. Description of the invention (4 ·) The dm 'shows' the use of dry-side technology to etch the first dielectric layer to form the first f1 The pattern 17 and the second pattern 19 of the first dielectric layer are removed, and the photoresist is removed. The first-dielectric pattern 17 and the first-dielectric pattern 19 have sidewaiis. Figure 3 Top view of the ISM " " location of the first pattern 17 and the second pattern 19 of the first dielectric layer. The dotted line of 3 is around the field oxidation isolation region 12. The basis of this part is the first element, The second element area, the third element area, and the collective contact area. The first-cultivated area is the area directly below the first pattern 17 of the dielectric layer in the substrate. The collector contact area is the second dielectric layer in the substrate. The area immediately below the pattern 19 and its surroundings, the second element area and the third element area will be described later. ^ As shown in FIG. 4, a second dielectric layer 22 (such as silicon dioxide) having a thickness between 2500 and 4,000 meters is deposited in the structure. FIG. 5 is a full-etching of the second dielectric layer by using dry etching to form a second dielectric layer void on the side walls of the first pattern 17 of the first dielectric layer and the second pattern 19 of the first dielectric layer. The spacer 22 is a region directly below the second dielectric layer spacer 22 mentioned above. The 'extrinsicbase' region 26 in FIG. 6 is formed by the first ion implantation, using the first pattern 17 of the first dielectric layer, the second pattern 19 of the first dielectric layer, and $ -dielectric. Layer 22 of the first pattern 17 and second pattern 19 of the first dielectric layer, and the field oxidation region 12 serve as a mask for the first ion implantation. In this embodiment, an N-type epitaxial layer In the npn bipolar junction transistor of the N-type well area, the first ion implantation 24 ion is B1 丨 or BF2, and the implantation amount is from 3 X 1015 IOns / cm2 to 7X 1015 IOns / cm2.
且植入能量從lOKeV至80KeV。在有P磊晶層或p井區之口叩電晶 體中。第一道離子植入24使用之離子為P或As。植入量為從3X l〇15ions/cm2至 7X1015ions/cm2，且植入能量從 l〇KeV 至 80KeV。之 前所提子的基板中之第三元件區域就是外質基極所在的基板區域。 接著如圖7所示’第一介電層空隔(spacer)被姓刻掉，利用第二 道離子植入並以第一介電層第一圖樣17、第一介電層第二圖樣19和 場氧化區域12作為阻隔(mask)以形成基極連結(base link)30。在本例 中具有N型蟲晶層或n型井區之ηρη電晶艘’其第二道離子植入28 使用之離子為Β11或BF2 ’植入量從5Χ 1013ions/cm2至2.5Χ 10l4ions/cm2，且植入能量從i〇KeV至80KeV之間，在有p型磊晶層 或P型井區之電晶體中，第二道離子植入28所使用的離子為p或As， 本紙張·尺度適用中國國家栊康f CNS ) A4奴放f 210乂川7/,\备、 JII II— I— I —κι— —^ϋ -裝-- (請先閱讀背面之注意事項再填寫本頁) 訂And implantation energy from lOKeV to 80KeV. Electron crystals with P epitaxial layers or p-well regions. The ion used in the first ion implantation 24 is P or As. The implantation amount is from 3X1015ions / cm2 to 7X1015ions / cm2, and the implantation energy is from 10KeV to 80KeV. The third element region in the substrate mentioned previously is the region of the substrate where the exoplasmic base is located. Then, as shown in FIG. 7, the first dielectric layer spacer is engraved, and the second ion implantation is used and the first pattern 17 of the first dielectric layer and the second pattern 19 of the first dielectric layer are used. The field oxidation region 12 serves as a mask to form a base link 30. In this example, the ηρη crystal cell with an N-type worm crystal layer or an n-type well area has a second ion implantation 28. The ion used is B11 or BF2. The implantation amount is from 5 × 1013ions / cm2 to 2.5 × 10l4ions / cm2, and the implantation energy is between 10KeV and 80KeV. In a transistor with a p-type epitaxial layer or a P-type well area, the ion used for the second ion implantation 28 is p or As. This paper · The standard is applicable to China ’s national health Kang F CNS) A4 slave f 210 Han Chuan 7 /, \ preparation, JII II — I — I —κι — — ^ ϋ-equipment-(Please read the precautions on the back before filling in this Page) order
A A7 A7 五 發明説明（3：) 其植入量為5X10丨5—2至2 5x 1〇Mi〇ns/cm 從10KeV至80KeV。 之門且植入能量為 30之俯視圖’虛線乃是外質基極26和基極連社 ；-^ϊι:；τ9Τμ；« i 内的虚線乃麵極接： 二圖甚被第一介電層第一圖樣17或第一介電層第 裝 接著如圖10中所示，第—介電層第―_ J 觸£域。 _掉:且_之第-賴f 訂 ,接者利用第三道離子植入形本質基極(intrinsic base)34，其中利用 從第一層複晶矽所形成之二氧化矽32和場氧化隔離區域n作 隔(mask) ’在有N型蟲晶層或㈣井區之啊電晶中，第三道離子植 入3^所使用的離子為B11或册2，其植入量為從！ χ納咖㈣至i X10 ions/cm2 ,且植入能量為從5KeV至8〇KeV之間，在有p ，或二型井區之電晶體中，第三道離子植人38所使用的離子為p或 As，其植入量為丨X丨們卿/㈤至丨χ 1〇14i〇ng/cm2之間且 為從 5KeV 至 80KeV。 接著如圖11所示，使用氧化層蝕刻液移去第一元件區域及集極 接觸區域之氧化墊層，接著在基板上沉積一層有摻雜之第二複晶矽 層，此有摻雜之第二複晶石夕層在N型蟲晶層或n型井區的npn電晶體 中為N型摻雜，在p型磊晶層或p型井區的pnp電晶體中為p型摻雜， 一層光阻覆蓋在此摻雜的第二複晶矽層上並形成射極圖樣44和集極 接觸區圖樣45。 接著如圖12所示，此摻雜之第二複晶矽層利用光阻射極圖樣和 光阻集極接觸區圖樣以形成射極接觸電極41和集極接觸電極42，基 板將會被加熱至900°C〜1150eC，在加熱過程中，雜質將會從摻雜之複 本紙張尺度適财關家標準（CNS)从胁（21QX297公着 一 7 — A7 B7 五、發明説明（b ) 第—元件區域以形成射極46，且雜質 ίί 在npn電_，在_複晶轉極 彡朗麵極46，而秘雜複晶石夕 ^pnp ° 坊、接所*’在基板上形成一層第三介電層(如二氧化 梦），在第二介電層形成接觸窗。接觸窗52連接到外質基極26 接到ιΐίΐίίΐ1且f觸窗56連接到集極接觸電極42，而 基極連結(base _3〇提供了外質基極26和本質基極3 = 既然基極連結30將本質絲_繞而料—26 ’ 圍繞’如圖8中所示，故只要一個基極接觸窗ϋ m(Se=igned)雙紐接面電轉，和触、基極集 之金屬矽化物並不需要或使用到β 雖然本發明已以較佳實施例揭露如上，然其並非 疋本發明，任何熟習此項技藝者，在不脫離本^明之 =請為:此本發明之保護範園當芯 ----A 装—— (諳先閲讀背面之注意事項再填寫本頁) —♦訂 經濟部中央揉準局貞工消費合作社印簟 木紙張尺度適用中國國家梯準（CNS ) Α4規格（210x297公廣） —Ζ-A A7 A7 Five Description of the invention (3 :) The implantation amount is 5X10 丨 5-2 to 2 5x10MiOns / cm from 10KeV to 80KeV. The top view of the gate with implanted energy of 30 'the dotted line is the exoplasmic base 26 and the base association;-^ ϊι :; τ9Τμ; the dotted line inside «i is connected to the surface: the second picture is very first introduced The first pattern of the dielectric layer 17 or the first dielectric layer is then mounted as shown in FIG. 10, and the first dielectric layer __ contacts the region. _ Drop: And _ the first-Lai f order, the receiver uses a third ion implanted intrinsic base 34, which uses silicon dioxide 32 and field oxidation formed from the first layer of polycrystalline silicon The isolation area n is used as a mask. 'In a crystal with an N-type worm crystal layer or a manhole area, the ion used for the third ion implantation 3 ^ is B11 or 2 and the implantation amount is from !! χNaKa㈣ to i X10 ions / cm2, and the implantation energy is from 5KeV to 80KeV. In the transistor with p or type II wells, the third ion implants the ions used by 38 It is p or As, and the implantation amount is between X, We, and X, and it is from 10 KeV to 80 KeV. Next, as shown in FIG. 11, an oxide pad etching solution is used to remove the oxide pad layer in the first element region and the collector contact region, and then a doped second polycrystalline silicon layer is deposited on the substrate. The second polycrystalline stone layer is N-type doped in the n-type worm crystal layer or npn transistor in the n-type well region, and is p-type doped in the p-type epitaxial layer or pnp transistor in the p-type well region. A layer of photoresist covers the doped second polycrystalline silicon layer and forms an emitter pattern 44 and a collector contact region pattern 45. As shown in FIG. 12, the doped second polycrystalline silicon layer uses a photoresistor emitter pattern and a photoresistor collector contact area pattern to form an emitter contact electrode 41 and a collector contact electrode 42. The substrate will be heated to 900 ° ° C ~ 1150eC, during the heating process, impurities will change from the doped copy paper standard (CNS) standard (21QX297 Publication No. 7 — A7 B7 V. Description of the invention (b) No.-element area In order to form the emitter 46, and the impurities ί ί npn at _, _ complex crystal transition pole 面 face electrode 46, and the miscellaneous compound spar ^ pnp ° square, contact * 'on the substrate to form a third dielectric An electrical layer (such as a dioxide dream) forms a contact window in the second dielectric layer. The contact window 52 is connected to the exoplasmic base 26 and the f contact window 56 is connected to the collector contact electrode 42, and the base is connected ( base _3〇 provides exoplasmic base 26 and essential base 3 = since base connection 30 wraps essential wire _ around the material -26 'around' as shown in Figure 8, so long as one base contacts the window ϋ m ( (Se = igned) double-junction surface electrical conversion, and contact and base set of metal silicide do not need or use β. Although the present invention has The preferred embodiment is disclosed as above, but it is not the present invention. Anyone skilled in this art will not depart from the present invention. ^ == Please be: the protection scope of this invention ---- A equipment—— (谙(Please read the notes on the back before filling this page) — ♦ The paper size of the printed alder of the Central Working Group of the Ministry of Economic Affairs, Zhengong Consumer Cooperative is applicable to the Chinese National Standard (CNS) Α4 size (210x297) —Z-