TW384477B - Merged memory logic semiconductor device, memory test control circuit and memory test method - Google Patents

Abstract

A merged memory logic semiconductor device including first and second memories, pads, a logic circuit and test control circuits is provided. Memory data signals received to or generated from the first and second memories are applied to the pads. The logic circuit controls the first and second memories. The test control circuit transmits memory control signals and memory data signals to the first and second memories when the first and second memories are tested, and transmits the memory control signals and the memory data signals to the logic circuit during normal operation.

Description

V. Description of the invention (A7 B7

Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 1. The invention of the invention is related to a type of merging. The memory logic semiconductor device, in particular, a kind of memory measurement and electromechanical + w omit 'memory logic for testing merging Much memory of the abundance conductor device. — 2. The previous case explained that in a merged memory 'semi-logically-semi-drying device, a memory is either a dynamic random access memory (DRAM) or static energy_plus ^ Λ 乂 a static slave machine access memory (SRAM ) And logic circuits to control memory. Packages. Each one Feng, thousand conductors. Device to implement a system, which has a small size, light rent 丨, · ^ + ^ and exhibit high performance at low power consumption, etc. Features In order to test the memory included in the semiconductor memory device, a test device was connected to the pad of the high-conductor memory, but the memory installed in the merged semiconductor device cannot be tested because the memory It is integrated through the logic circuit installed in the merged memory logic semiconductor device. Therefore, an additional pad is required to test the memory installed in the merged memory logic semiconductor device. However, when the number of pads increases, the merge The size of the memory semiconductor device is increased to increase the manufacturing cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory test circuit incorporating a memory logic semiconductor, which can test a memory by using a conventional pad. Another object of the present invention is to provide a memory test method, which can reduce the body test time of a memory logic semiconductor device with a combination of memory and memory " capable of measuring logic memory and memory -------- --Installation-- 〆- (Read the "Notes on the back" before filling out this page) -4 This paper size applies to Chinese national standards (<: 1 ^) / 514 specifications (21〇 / 297 mm) A? B7 2 V. Description of the Invention (Provided in order to accomplish the above objectives-a kind of memory logic semiconductor = includes: many memories H, which receives memory control signals to multiple memories; other pads, which are received from many memories or from Its generation: the memory data signal is applied to other pads;-logic circuit to control many C memory; and-test control circuit, connected to other circuits, logic electricity, and many memories, when testing many memories It is used to transmit memory control signals and memory data signals to many memories in response to a test control signal 'and to transmit memory control signals and memory data signals to logic. Circuits during normal operation ... in order to π Provides a kind of merged memory logic semiconductor device into the above-mentioned project, including: the first bathroom-but. Hum. ^ No /, Le- 疋 memory body; a pad, which receives the memory control: No. Control the first and second memories; the other is that it receives the memory data signals generated from the first and second memories, or transmits the memory data signals to the first and second memories; a logic circuit, Xiao In order to control the first and second memories, the “and” memory test control circuit is connected to the pad, and the other pads ’logic circuits and the first and second memories are used to transmit when the first and second memories are tested. The memory control signal and the memory data signal to the first and second memories Mm are used to transmit the memory control signal and the memory data signal to the logic circuit during normal operation. In order to achieve the above goal, a merged memory is provided. A logic semiconductor device includes: a plurality of pads, applying one or more external clock signals and test enabling signals to the plurality of other pads; at least 2 memories, in which data is stored, and more built-in self-testers are used, For testing Memory function to respond to the clock signal and test enable signal, and transmit the result to other -5- This paper size applies the Chinese National Standard (CNS) Α4 specification (21〇χ297297) ------ -二 衣 ------ 1Τ ------ 丨 M (Read the first read and read the back. Please note the matter before filling out this page) The Central Standards Bureau of the Ministry of Economic Affairs Consumer Cooperatives Printed The Central Standards Bureau of the Ministry of Economic Affairs Printed by employees' consumer cooperatives A7 ---------- ---- B7 V. Description of invention (3)-Many 塾. In order to achieve the above objective, a combined memory logic semiconductor device is provided, including : A merged memory logic semiconductor device, including a remote, and-memory, including: first and second 塾, applying external brothers 与 and ：: clock ㈣ to m, third and fourth rounds, eight Do not apply = external first and second test enable signals to the third and fourth pads; $ five and sixth pads; first and second memory, which stores data, the first built self-tester, received the first —Memory unit, first and third pads, used to test the function of the first memory, in response to the first clock signal and the first test Signal, and transmit the result to the fifth pad; and—the second built-in self-tester is connected to the first memory unit, the second pad and the fourth pad, which are used to test the function of the second target carcass in response to The second clock signal and the second test enable signal are transmitted to the sixth pad. In order to achieve the above objective, a combined memory logic semiconductor device is provided, which has a logic circuit and a memory, including: a first pad, & adding an external clock signal to the first pad; second and third Pads, which respectively send the first and second test enable signals to the second and third integers; the fourth and fifth pads; the first and second memory units, which store data in the real; the first built-in self-test Is connected to the first memory unit and the first and second pads, for testing the function of the first memory, in response to the clock signal and the first-test enabling letter chain, and transmitting the result to the fourth pad; and The second built-in self-test device is connected to the first memory unit and the first pad and the second pad to test the energy of the first memory in response to the clock signal and the first test enable signal, and Transfer the result to the fourth frame. -6- This paper size applies Chinese National Standard (CNS) A4 specification (2 丨 〇 < 297 mm) (谙 Please read the notes on the back before filling this page) (4 A7 B7 DuPont Printing Co., Ltd. of the Central Bureau of Guidance, Ministry of Economic Affairs is provided for redundancy. To achieve the above goals-a group of people, a combination of garbage and memory, a semiconductor logic device, a logic circuit and a memory The body includes:-the first pad, the application: the external: the pulse signal to the first-塾; the second and the third backup, respectively apply the external brother one and the first test enable signal in & π. ^ 丨 ° present 1st and 3rd pads of the younger brother; 4th and 5th rounds; 'first and second memories, φ · change ^ 8τ stored data; a built-in self-test device, connected to the first memory unit and the first One, x ^ The main brother of the two brothers, used to test the functions of the first and second memory, in response to the clock signal and the first test second enable signal, and send the results to the fourth and fifth pads, respectively Provided for the first goal of Yuancheng—a kind of parallel memory memory semiconductor semiconductor memory-test method, the device There are: a logic circuit, a memory, and two built-in self-test devices, including the following steps: applying a clock signal and a test enable signal to start the built-in self-test device to the built-in self-test device; The tester generates a control signal for testing a function of the memory; generates an output data signal from the memory; and generates a test result signal from the built-in self-tester to display the test result of the memory. In order to complete the second goal. A memory test method for a combined logical memory semiconducting device is provided. The device has: a built-in self tester, connected to an external terminal, and a plurality of memories, including the following steps: a) the data socket The built-in self-tester and a lot of memory; and b) the built-in self-tester reads the data stored in a lot of memory. According to the present invention, the manufacturing cost of a merged memory logic semiconductor device can be reduced. Brief description of the drawings From the detailed description of the preferred specific examples and the accompanying drawings, ’this post will be understood -7- (read the back first, v notes before filling in this page)

I, ml 11-. ^ N | _ I--111 J, 'Shi · ^-IIII · · 1-. I I- 1— ΙΊ \ ^^ ....... 1— II i, T. ¾ The size of this paper is suitable for the national transfer (CNS) A4 specification of the rich countries (21 公 × 29? Moments) 5. Description of the invention (the above-mentioned goals and advantages are clear, in which. ········ Figure 1 is a block according to the present invention—and each unit Figure; ~ Λ 'the combination of the memory logic half f please read it. Read the back © Note and then according to the block diagram of the memory test control circuit in Figure 1; 3 疋 Figure 2 Circuit of the memory control signal controller Figure 4 is a diagram 2 memory please _ device ㈣ 路 _ ·, the second is according to the third specific example of the memory test control circuit of Figure 1 Figure 6 is Figure 5 memory control. Letter. Fasting device 圏. Figure 7 is ^ The circuit of the memory data controller .: Fig. 8 疋 'Fig. 5 The circuit diagram of the second memory-free data controller; Fig. 9 is an example of the eighth body according to the second and Xuanlu · λ of the present invention. Figure 10 is a block diagram of a potassium logic memory semiconductor semi-adapted device; FIG. 10 is a block diagram of a potassium logic memory semiconductor device according to the first = 1st example of the fragrant eighth sister of the present invention; Fig. 11 is a block diagram of a coupled memory logic semiconductor device according to a fourth specific example of the present invention; Fig. 12 is a timing chart of the signals of Figs. 9 to 11; The flowchart shows a memory test method of a merged memory logic semiconductor device according to the present invention. Specific Examples FIG. 1 is a block diagram of a merged memory logic semiconductor device i according to a first specific example of the present invention. Referring to FIG. The combined memory logic semiconductor device 5 includes: pads 7, 8, 9, and 10, a memory test control circuit 13, and a paper scale that conforms to the Chinese National Standard (CNS) A4 specification (2 丨 〇 × 297 mm) A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6 Logic circuit 15, and the first and second memories 17 and 19. The memory test control circuit 13 is connected to 塾 7, 8, 9 and 1Q And the data @ 路, the first and second memories 17 and 19 such as _ row are connected to the memory: test control circuit 13. The memory control signals used to control the first and second memories 17 and 19% then Applied to the 8. Two test control signals TESTkDQ and TESTMD1 for controlling the memory test control circuit 13 are connected to the pad g. And the first: the memory data signals of the second memory 17 and 19 are noisy / lost = Shi Er To pad 7, pads 7 and 8 are .. Existing pads-to use ... the first and second billions u and 19, and pads 9 and 10 plus pads to control the memory test control circuit u. 1Memory The tester (not shown) receives 塾 7, 8, 9 and 10 for testing and merging the first and second memories 17 and 19 of the memory logic semiconductor device 5: Yes, the memory tester (not shown) (Shown) The memory control signal pc and the memory data signal DQi are input to the memory test control circuit 13 through the pads 7 and 8. In addition, the memory test is controlled by the test control signal "addition and combination" The control signal 13 is used to test the first and second memory ports and 19, and the memory test control circuit 13 applies the memory control signal% and the memory data signal DQi to the first and second memories 17 and 19. The first and second memories 17 and 19 are operated by the memory control signal pc and the memory data signal DQi, and the results are transmitted to the memory test control circuit η, and the memory test control circuit 13 is transmitted via 塾 7 and 8 The first and second memories & and 19 to the memory tester (not shown) are transmitted, so the memory tester (not shown) analyzes the signals transmitted via the pads 7 and 8 to evaluate the first and second Memory i 7 and 19 functions. ，. (Please read the notes on the back. Please fill in this page)

, 1T

Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 V. Invention Description (If the first and second memories 17 and 19 are not tested, the logic logic semiconductor device W5 is properly connected, The TESTMDAr signal is combined with TE S TMm, so the memory test control circuit i 3 will not be partially made of bismuth. The memory control signal is applied from the outside with the memory data number DQl to perform the combined memory logic. During the normal operation of the FET conductor device 5, the applied signal is turned into a logic circuit 15, which controls the first and second memories 17 and 19 through the memory test control circuit 13. The specific example of the present invention can be used for the device 2 A memory logic semiconductor device incorporating a memory, but can also be used in a billion-body logic semiconducting squatting device with a merger of one or more memories. As described above, the merger according to a specific example of the present invention As for the memory logic semiconductor device 5, the conventional pads 7 and 8 can be used to test the first and second memories 17 and 19. ~ Fig. 2 is a diagram according to the first specific example 丨 memory test control circuit i3 Block diagram, see Considering FIG. 2, the memory test control circuit 13 according to the first specific example includes a main control signal generator 23, a memory control signal controller 25, and a memory data controller 27. In the main control signal generator 23, The test control signals TESTMD0 and TESTMD1 are applied to the input terminal, and the output terminal is connected to the memory control signal control chip 25 and the memory data controller 27. The main control signal generator 23. Generates the main control signals MEMTESTi, MEMTEST2 and NORMAL The control signals TESTMD0 and TESTMD1 are used to test the decay. For example, the main control signal generator 23 has a sheet as shown in Table 1. 10 Thai paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) --- ------, loading! (Please read the lack of attention on the back before filling out this page}, 11 _ ^ _ "printed by the Central Bureau of Standards of the Ministry of Economic Affairs A. __ B7 V. Description of the invention ( 8) (Table 1) Function TESTMD0 TESTMDI, main control signal-First memory test CL5 'L, MEMTEST1 Second memory test' Η, 'L, MEMTEST2 Normal operation CL5 SH' NORMAL 4H 'SH' The state is shown in Table 1. When the test control signal TESTMD0iTESTMD1 is a logic low 'L', the main control signal MEMTEST1 is activated to test the first memory 17 of FIG. 1, and when the shift-If test controls H TESTMD0 When the test control signal MESTMTD1 is a logic low 'L', the main control # number MEMTEST2 is started to test the second memory _19 in FIG. 1, and when the test control signal TESTMD0 is a remote low L 'while the test control signal TESTMD1 is high, even if the signal NORMAL operates to operate the logic circuit 15 of FIG. 1 normally. When the test control signals TES.TMD0 and TESTMDi are logic low 'L', the previous state is maintained. The memory control signal controller 25 receives the applied memory control signal PC via the pad 8 and is controlled by the main control signals MEMTEST1, MEMTEST2 and NORMAL · to transmit the main control signal PC to the first and second memories 17 of FIG. 1 And 19 and logic circuit 15 of FIG. 1 6 memory control signals pc include: column address strobe signal RASB, row address strobe signal CASB, write enable signal WEB, output enable signal OEB, and bit Address signal Ai. The memory controller data controller 27 receives the applied memory data signal DQi via the pad 7, and is controlled by the main MEMTEST1, MEMTEST2, and NORMAL to transmit the externally input memory data signal DQi to the first and the -11th of FIG. 1 -I scale is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) f binding — ί ^. (Read the first page and read the page without any notes before filling this page) A7 ——- ~ _. B7 V. Invention Explanation (9) The two memories Ϊ7 and 19 or the logic circuit 15 of FIG. 1 and transmitting the memory data signals generated by the first and first s memories 17 and 19 of FIG. I] 3Qi or the logic circuits 15 to i of FIG. Pad 7. As described above, the memory test control circuit I3 according to the first embodiment of the present invention can use the conventional pads 7 and 8 of FIG. 1 to test the first and second memories 17 and 1 of FIG. 1 without the logic circuit 15. 19. FIG. 3 is a circuit diagram of the memory circuit signal controller μ of FIG. 2. Referring to FIG. 3, the memory control signal controller 25 includes a buffer 31, a logic gate, and a memory controller 35. .............-The buffer 31 receives the memory control signal pc and transmits it to the logic gate 33. The buffer 31 changes the voltage level of the memory control signal%, such as transistor transistor logic (TTL ) Level voltage into a complementary metal oxide (CM0s) level voltage. The logic room 33 receives the output of the buffer 31 and transmits the output to the memory controller 35. The logic gate 33 includes first-third AND gates 33a, 3 and 33 ^. The first AND 33a receives the wheel of the buffer 31 and the main control signal MEMTEST1. When the output of the buffer 3 or the main control signal is dirty, it is printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs {Please read the back first (Please note this page to fill in this page)) When the logic is low, the -AND gate 33a will generate a logic low signal, and when the output of the buffer 31 and the main control signal MEMTEST1 are logic high, the first AND gate 33a will generate a logic low. Logic high signal. The second AND gate 33b receives the output of the buffer 3i and the main control signal NORMAL and transmits the output to the logic circuit 15 in FIG. 丨. When the output of the buffer B or the main control signal NORMAL is logic low, the second AND gate 3b A logic low signal is generated everywhere, and when the output of the buffer 31 and the main control signal are -12- the paper ruler; lit Caiguanjia County (CNS) Λ4 specifications (210χϋ ^ 7) A7 printed by the consumer cooperative -------- -B7 ___. V. Description of the invention (10) When normal is logic high, the second ANt > gate 33b generates a logic high signal. The third AND gate 33C receives the buffer The output of 31 and the main control signal MEMTEST2. When the output of the buffer n or the main control signal memtest2 * is logic low, the third AND gate 33b generates a logic low signal, and when the output of the buffer 31 and the main control signal MEMTEST2 are When the logic is low, the third AND gate 33c generates a logic high signal. 'The memory controller 35 includes first and second multiplexers 35 & and 351). A 2 input 1 output multiplexer will become the first. The multiplexer 35a is used. The first multiplexer 35a receives the output of the first AND gate 33a and the output of the logic circuit 15 of FIG. 1 and is controlled by the main control signal NORMAL. It is controlled with MEMTEST1 to transmit the output of the first AND gate 33a and the output of the logic circuit 15 of FIG. 1 to the first memory 17]. That is, when the constant master control signal normAL is activated, the first multiplexer 35a transmits the signal generated by the logic circuit 15 of FIG. 1 to the first memory Π in FIG. 丨, and when the master control signal ΜΜΤΕδΤ1 operates, the first The multiplexer 35a transmits the signal generated by the first AND gate 33a to the first memory 17 of FIG. A 2 input 1 output multiplexer is used as the second multiplexer 35b, the second multiplexer 35b receives the output of the third ANt) gate 33c and the output of the logic circuit 15 of FIG. 1 and is controlled by the main control signals NORMAL and MEMTEST2 Control to transmit the output of the third AND gate 33c and the output of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. That is, when the main control signal NORMAL operates, the second multiplexer 35b transmits a signal generated by the logic circuit 15 of FIG. 1 to the second memory 19 ′ of FIG. 1 and when the main control signal MEMTEST2 operates, the second multiplexer 35b The device 3: 5b transmits the signal generated by the third AND gate 33c to the second memory of FIG. 1 '13-This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) '~~' ~~ ~ ~~ -— --------- 'install --- ^ ---- 1T ------ (read the notes before reading the two back before filling out this page) 5. Description of the invention (11 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Figure 4 疋 Figure 2 Circuit of the memory data controller 27 The memory data controller 27 includes: input and output refer to the 'Figure 4' memory controller 45, output Controller 47 'Logic_Bamboo, 49. "Output buffer controller 4: The input / output buffer 41 includes an input buffer 仏 and a round-out buffer input buffer 41a to receive the memory data signal D, 43, the input is slow, the memory of the memory is Q, and the logic is accurate. For example, the output buffer 4 lb is controlled by the output buffer controller. So that the output from the output controller 47, that is, when the output buffer ¥ controller "output action ', that is, the output buffer 41b is activated to output from the external controller 47' and when the output buffer controller 49's The output does not move; the output buffer H4! B does not operate to prevent the output of the magic 47 from being transmitted from outside. The industrial logic gate 43 receives the rotation of the input buffer 4la and the signals memtest ^, norMAi ^ MEMTEST2 and transmits the output to The memory controller 45 and the logic gate 43 include first to third ANDMs 43a, 431) and 43. . The first AND gate 43a receives the output of the input buffer 41a and the main control signal MEMTEST1, and transmits the output to the memory controller. When the output of the input buffer 41a or the main control signal MEMTEST1 is logic low, the first AND gate 43a 43a generates a logic low signal, and when the output of the input buffer 4 and the main control signal MEMTEST1 are logic high, the ―and‖ gate “a

Install-(Read the notes on the back and then fill out this page) '17-^-, ¾

. »I II Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Invention Description (12) A logic high signal is generated. The second AND gate 43b receives the output of the input buffer 41a, the main control signal NORMAL, and transmits the output to the logic circuit 15 of FIG. 1 when the output of the input buffer 41a or the main control signal NORMAL is logic low. The second AND gate 43b generates a logic low signal, and when the output of the input buffer 41a and the main control signal NORMAL are logic high, the second AND gate 43b generates a logic high signal. + 'The third AND gate 43c receives the output of the input buffer 41a and the main control signal MEMTEST2, and transmits the output scratch-I & memory controller 45, when the output of the input buffer 41a or the main control signal MEMTEST2 is logic low The third AND 閛 43c generates a logic low signal, and when the output of the input buffer 41a and the main control signal MEMTEST2 are logic high, the third AND gate 43c generates a logic high signal. The memory controller 45 includes first and second multiplexers 45a and 45b. A 2 input 1 output multiplexer is used as the first multiplexer 45a. The first multiplexer 45a receives the output of the first AND gate 43a and the output of the logic circuit 15 of FIG. 1 and is controlled by the main control signals NORMAL and MEMTEST1. In order to transmit the output of the first AND gate 43a and the output of the logic circuit 15 of FIG. 1 to the first memory I7 of FIG. 1 '. That is, when the main control signal NORMAL operates, the first multiplexer 45a transmits a signal generated by the logic circuit 15 of FIG. 1 to the first memory Π of FIG. 1, and when the main control signal MEMTEST1 operates, the first multiplexer 45a The device 45a transmits the signal generated by the first AND gate 43a to the first memory 17 of FIG. A 2 input 1 output multiplexer is used as the second multiplexer 45b. The second multiplexer 45b receives the output of the third AND gate 43c and the output of the edit circuit 15 in FIG. I. (CNS) A4 specification (210 ×: 297 public dream_) --------- ^ Outfit -------- Order ------ 'M (Please read the precautions on the back .. (Fill in this page) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs kl ____B7 _____ 5. The invention description (13) is issued and controlled by the main control signals NORMAL and MEMTEST2 to transmit the output of the third AND gate 43c and the logic of Figure 1. The output of the circuit 15 is sent to the second memory 19 of FIG. 1. That is, when the main control signal NORMAL operates, the second multiplexer 45b transmits a signal generated by the logic circuit 15 of FIG. 1 to the second memory I9 ′ of FIG. 1 and when the main control signal MEMTEST2 operates, the second multiplexer 45b The device 45b transmits the signal generated by the third AND gate 43c to the second memory 19 of FIG. 1. The output controller 47 receives the signals generated by the logic circuit 15 of FIG. 1 and the first and second memories 17 and 19 of FIG. 1: , ... and remote-output to, output buffer 41b, a 3 input 1 round out multiplexer is used as the output controller 47, controlled by the main control signals NORMat, MEMTEST1 and MEMTEST2, that is, when the main control When the signal is NORMAL, the output controller 47 transmits the signal generated by the logic circuit 15 of FIG. 1 to the output buffer 4 lb. When the main control signal MEMTEST1 is activated, the output controller 47 transmits the signal of the first memory 17 of FIG. 1 to The output buffer 41b, and when the main control signal MEMTEST2 is activated, the output controller 47 transmits the signal generated by the second memory 19 of FIG. 1 to the output buffer 41b. The wheel-out buffer controller 49 includes first to third Logic gates 49a, 49b and 49c, AND gate NAND gates 49c and 49e. The first logic gate 49a receives the main control signals MEMTEST1 and MEMTEST2. When one of the main control signals MEMTEST1 and MEMTEST2 is logic high, the first logic gate 49a generates a logic high signal, and the main control signals MEMTEST1 and MEMTEST2 are logic When it is low, the first logic gate 49a will generate a logic low signal ^ -16 _ _ __________ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 public inverse) ---------- -\ 装 —— (锖 Please read the notes on the back before filling in this page)

1. 1T printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A 7 ___B7__ V. Description of the invention (14) The second logic gate 49b receives the first output buffer enable signal TRST1 generated by the first memory 17 in FIG. 1 and FIG. 1 When the second output buffer enable signal TRST1 or the second output buffer enable signal TRST2 is logic high, the second logic gate is generated by the second memory 19. 49b generates a logic high signal, and when both the first output buffer enable signal TRST1 and the second output buffer enable signal TRST2 are logic low, the second logic gate 49b generates a logic low signal. The fourth AND gate 49c receives the output of the first logic gate 49a and the output of the second logic gate 49b. When the output of the first logic gate 49a: or the output of the second logic gate 49b is logic low, the fourth AND gate is A logic low signal is generated, and when both the output of the first logic gate 49a and the output of the second logic gate 49b are logic high, the fourth AND gate generates a logic high signal. The third logic gate 49d receives the output of the fourth logic gate 49c and the main control signal. When the output of the fourth AND gate 49c or the main control signal is logic high, the third logic gate 49d generates a logic high signal, and when When both the output of the fourth AND gate 49c and the main control signal are logic low, the third logic gate 49d generates a logic low signal. The NAND gate 49e receives the output of the third logic gate 49d and the power supply voltage VCC and transmits the output to the control terminal of the output buffer 4 lb. The NAND gate 49e transmits the output of the third logic gate 49d to the control terminal of the output buffer 41b. That is, when the output of the third logic gate 49d is logic high, the NAND gate 49e generates a logic low signal, and when the output of the third logic gate 49d is logic low, the NAND gate 49e generates a logic high signal When the output of the NAND gate 49e is logic low, that is, when the output is activated, the output buffer H 4lb is activated, and when the paper size applies to China. National Standard (CNS) A4 specification (210X 297). ---- ---- Ά 衣 -------, ιτ ------ ΛΜ (Read the first and then read the back. Please pay attention to this page before filling in this page) A7 __ B7 1 ~~ · _-, Description of the invention ( 15) ~ When the output of the NAND gate 49e is logic high, that is, it does not operate, the output buffer 417 does not operate. 5 is a block diagram of a second specific example of the memory test control circuit according to FIG. 1. Referring to FIG. 5, the memory test control circuit 213 according to the second specific example includes a main control 彳 § generator 5 丨, a memory The control signal controller 53, the first memory data controller 55, and the second memory data controller 57 °. The main control signal generator 51 receives the test control signal TESTMDO from Canada through the pad 9 and transmits Then, the output of the output controller includes the output of the control signal controller, the first memory data controller 55, and the second memory data controller 57. The main control signal generator 5 i generates a main control signal, that is, a memory main control signal MEMTEST and a logic main control signal NORMAL in response to the test control signal TESTMD0. For example, the main control signal generator 5 i has 眞 値 shown in Table 2. (Table 2) Function TESTMD0 Main control signal First and second memory test 4L 'MEMTEST Normal operation CH5. „Normal Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs as shown in Table 2. When the test control signal TESTMD0 is logic low When the test control signal TESTMD0 is a logic high 'H, the main control signal MEMTEST operates to test the first and second memories 17 and 19 of FIG. 1, and the logic main control signal NORMAL is not operated for normal operation. Logic circuit 15 of circle 1. The memory control signal controller 53 receives the applied memory control number PC via 塾 8, and is controlled by the main control signals MEMTEST and NORMAL-18- This paper size applies the Chinese National Standard (CNS) A4 specifications _ (2IOX 297 mm) A7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs _______ B7 five 'invention description (16) system to transmit the memory control signal PC leather Figure 1 of the first and second memory 17 and 19 or the logic circuit 15 of Fig. 1. The memory control signal PC includes: column address strobe signal RASB, row address strobe signal CASB, write enable signal WEB, turn out The signal OEB and the address signal Ai. The first memory data controller 55 receives the applied memory data signal DQ 1 i 'via the pad 7 and is controlled by the main control signals MEMTEST and NORMAL to transmit the memory data signal DQli to the figure. 1's first memory / memory π or figure ”logic circuit 15 and the memory data signal DQU generated by the first memory 17 of FIG. 1 or the logic of FIG. a The second memory data controller 57 receives the applied memory data signal DQ2i via the pad 7 and is controlled by the main control signals MEMTEST and NORMAL to transmit the memory data signal DQ2i to the second memory 19 or FIG. 1 1 logic circuit 15 and transfers the memory data signal DQ2i generated by the second memory 19 in FIG. 1 or the logic circuit 15 to pad 7 in FIG. 1. As described above, the memory test control circuit 213 according to the second embodiment of the present invention can use the conventional pads 7, 8 and 71 of FIG. 1 to test the first and second memories 17 of FIG. 1 without the logic circuit 15 With 19. 'FIG. 6 is a circuit diagram of the memory control signal controller 53 of FIG. 5. Referring to FIG. 6, The memory control signal controller 53 includes: a buffer 61, a logic gate μ, and a memory controller 65. The buffer 61 receives the memory control signal pc and transmits it to the logic gate 63. The buffer 61 changes the voltage level of the memory control signal pc, for example, the voltage of the TTL level is converted to the voltage of the CMOS level. . The logic gate 63 receives the output of the buffer 61 and transmits the output: output to the memory control -19-this paper size is appropriate _ wTmT7 ^ (2l0x297 ^ t) (.Please read the precautions on the back before filling this page) binding -1 .. ¾ Printed by the Consumer Standards Cooperative of the Central Bureau of Standards A 7 B7 V. Description of the invention (17) The controller 65 includes the first and third AND gates 63a, 63b, and 63c. The first AND gate 63a receives the output of the buffer 61 and the memory main control signal MEMTEST. When the output of the buffer 61 or the memory main control signal MEMTEST is logic low, the first AND gate 63a generates a logic low signal. Moreover, when the output of the buffer 61 and the memory main control signal MEMTEST are logic high, the first AND gate 63a generates a logic high signal. The second AND gate 63b receives the output of the buffer 61 and the edit main control signal NORMAL, and transmits the output to the logic circuit 15 of FIG. 1, when the output of the buffer 01 or the logic main control signal NORMAL is logic low. At this time, the second AND gate 63b generates a logic low signal, and when the output of the buffer 61 and the logic main control signal NORMAL are logic high, the second AND gate 63b generates a logic high signal. The third AND gate 63c receives the output of the buffer 61 and the memory main control signal MEMTEST. When the output of the buffer 61 or the memory main control signal MEMTEST is logic high, the third AND gate 63c generates an operational high signal. The memory controller 65 includes first and second multiplexers 65a and 65b. A 2 input 1 output multiplexer is used as the first multiplexer 65a. The first multiplexer 65a receives the output of the first AND gate 63a and the output of the operation circuit 15 of FIG. 1 and is controlled by the main control signals NORMAL and MEMTEST. To transmit the output of the first AND gate 63a and the output of the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. That is, when the logic main control signal NORMAL operates, the first multiplexer 65a transmits a signal generated by the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1, and when the memory main control signal MEMTEST operates , The first -20- This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 cm). Equipment-(Please read the precautions on the back before filling this page),-° Μ Β7 Central Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Standards Bureau. 5. Description of the invention (18. Multiplexer 653 sends the signal generated by the first-and-63a to the first-memory of Figure 1. One 2 input 1 output multiplexer is the second most. The second multiplexer 65b is used by the second multiplexer 65b and receives the output of the third ANO gate 63e and the output of the logic circuit 15 'and is controlled by the main control signals Dai NORMAL and MEMTEST to transmit the rotation of the third AND gate 63c. The output from the logic circuit 15 of FIG. 1 is to the second memory 19 of the logic 1. That is, when the logic main control signal is normal, the second multiplexer 65b is the signal generated by the logic to the second of FIG. Memory 19, and when the memory master controls., Signal M. & MTEST #,., The The signal generated by the third AND gate 63c is forced out of the multiplexer to the second memory 19 in FIG. J. FIG. 7 is a circuit diagram of the fifth memory controller 55 in FIG. 5. Referring to FIG. 7, the first memory The physical data controller M includes: a first input, an output buffer 71 ', a first logic close 73, a first memory controller 75, a first output controller 77', and a first output buffer controller 79. The input / output buffer 71 includes a first input buffer 71a and a first round-out buffer 71b. The first input buffer 71a receives the memory data signal DQH and transmits the output to the first logic gate 73. The first input buffer The device 71a changes the voltage level of the memory data signal DQli, for example, converts the voltage at the τχ level to the CMOS level voltage. The first output buffer 711) is controlled by the first-round buffer controller so that The output of the first output controller 77 is transmitted from the outside, that is, when the output of the first-round out buffer controller 77 is actuated, the first output buffer is activated so as to transfer the output of the first output controller 77 from the outside. j And when the first-lose ^ paper standards apply to Chinese national standards (CNS) A4 specifications (read the precautions on the back before filling out this page) ------ install --------. Order --- 21 Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Β7 5. Description of the Invention (19) —: When the output of the output buffer controller 79 is not activated, the first output buffer 7ib is not activated to transmit the output of the first output controller 77 from the outside. The first logic gate 73 receives the output of the first input buffer 71a and transmits the output to the first memory controller 75. The first logic gate 73 includes first and second AND gates 73a and 73c. The first AND gate 73a receives the rotation of the first input buffer 71a and the memory main control signal MEMTEST. When the output of the first input buffer 囍 々 u or the memory main control signal MEMTEST is logic low, the first AND The gate 73a generates a logic low signal—, and ... and.—the first input. The output of the buffer 71a and the main control signal] ^ EMTEST is logic high, the first AND gate 73a generates a logic high signal . The second AND gate 73c receives the output of the first input buffer 71a and the main control signal NORMAL, and transmits the output to the logic circuit 15 of Fig. I. When the output of the first input buffer 71a or the main control signal NORMAL is logic low, the second AND gate 73c generates a logic low signal, and when the output of the first input buffer 71a and the main control signal NORMAL are logic high At this time, the second AND gate 73c generates a logic high signal. The first memory controller 75 includes a 2 input 1 first output multiplexer. The first memory controller 75 receives the output of the first AND gate 73a and the output of the logic circuit 15 of FIG. Controlled with MEMTEST to transmit the output of the first output AND gate 73a and the output of the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. That is, when the main control signal NORMAL is activated, the first memory controller 75 transmits a signal generated by the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1, and when the main control signal -22 is activated This paper size applies to China National Standard (CNS) A4 (210 X 297 cm) (Read the precautions on the back before filling in this B ..). Packing, .-0 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Making kl B7 V. Description of the invention (2Q) In the case of MEMTEST, the first memory controller 75 transmits the signal generated by the first output AND gate 73 ^ to the first memory 17 in FIG. The first output controller 77 includes a 2 input 1 output multiplexer. The second output controller 77 receives signals generated by the logic circuit 15 of FIG. 1 and the first memory 17 of FIG. 1 and transmits the output to the first output buffer. 71b, the second output controller 77 is controlled by the main control signals NORMAL and MEMTEST, that is, when the logic main control signal NORMAL is activated, the first output hanger 77 transmits a signal generated by the logic circuit 15 of FIG. 1 to the first The output buffer 71b, and when the memory main control signal MEMTHEST is activated, the first output controller 77 transmits the signal generated by the first memory 17 of FIG. 1 to the first output buffer 71b. The first output buffer controller 79 includes a third AND gate 79a, a first logic gate 79c, and a first NAND gate 79d. The third AND gate 79a receives the memory main control signal MEMTEST and the first output buffer enable signal TRST1. When the memory main control signal MEMTEST or the first output buffer enable signal TRST1 is logic low, the third AND The gate 79a generates a logic low signal, and when the memory main control signal MEMTEST and the first output buffer enable signal TRST1 are both logic high, the third AND gate 79a generates a logic high signal. The first logic gate 79c receives the output of the third AND gate 79a and the main control signal NORMAL. When the output of the third AND gate 79a or the logic main control signal NORMAL · is logic high, the first logic gate 79c generates a logic high signal Moreover, when the output of the third AND gate 79a and the main control signal NORMAL are both logic low, the first logic gate 79a generates a logic low signal. The first NAND gate 79d receives the output of the first logic gate 79a and the power supply -23- This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) --------- '# 衣-(Please read the note on the back before filling this page)

* 1T A7 ----------_ B7 Five 'invention description (21) -------- Press VCC and transmit the output to the control end of the first output buffer claw, the first = AND gate 79d transmission The output of the first logic gate to the working end of the first output buffer claw is 'ie' the first logic gate 79. The output is logic low when the —NA-D gate. 7: d generates a logic high signal 'and acts as the first logic gate π. At the same time, the output 疋 logic of the first NAND gate 79d generates a logic low signal. When the output of the first financial room 79 {1 is · logic low, that is, it is activated, that is, the first-output 'geng punch 7id is started, and when the output of NANE ^ is high, that is, it does not act. The output buffer 7lb is inactive. FIG. 8 is a circuit diagram of the second memory of FIG. 5 and the memory of the controller. Referring to FIG. 2, the second memory data controller 57 includes a second input / output buffer !! Gate 83, second memory controller 85, second round-out controller 87, and second output buffer controller 89. 'The second input / round-out buffer 81 includes a second input buffer Sla and a first Two output buffers 81b. The first input buffer Sla receives the memory data signal DQ2i and sends it out to the second logic gate 83. The second input buffer changes the voltage level of the memory data signal DQh, for example The voltage at the hole level is converted into a level voltage. The second output buffer 81b is controlled by the second output buffer controller 89 and transmits the output of the second output controller 87 from the outside, that is, when the second When the output of the output buffer controller 89 operates, the second output buffer Slb transmits the output of the second output buffer controller 87 from the outside, and when the output of the second output buffer controller S9 does not operate, the first The second output buffer 81b does not operate, so the second output controller is not transmitted from the outside. Output of 87. * 24-This paper size applies to China National Standard (CNS) A4 (210X297). (Please read the precautions on the back before filling this page}

1T printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative of the Central Standard Bureau of the Ministry of Economic Affairs, printed by A7 B7 V. Invention Description (22) The second logic level $ 3 receives the output of the second input buffer gia and transmits the output to The second memory controller S5 includes a fourth and fifth AND gates 83a and 83c. The fourth AND gate 83a receives the output of the second input buffer 81 & and the memory main control signal MEMTEST. When the output of the second input buffer 81a or the memory main control signal MEMTEST is logic low, the fourth AND gate 83a is A logic low signal is generated, and when the output of the second input buffer '81a and the memory main control signal MEMTEST1 are logic high, the fourth AND gate 83a generates a logic high signal j ...........- The fifth AND gate 83c receives the output of the second input buffer 8ia and the main control signal NORMAL and transmits the output to the logic circuit μ of FIG. 1. When the output of the second input buffer 81a or the main control signal is logic low, the first The fifth AND gate 83c generates a logic low signal, and when the output of the second round-in buffer 81a and the main control signal NORMAL · are logic high, the fifth AND gate 83c generates a logic high signal. The second memory controller 85 includes a 2 input 1 output multiplexer. The second memory controller 85 receives the output of the fourth AND gate 83a and the output of the logic circuit I5 of the 1 map, and is controlled by the master control signals NORMAL and MEMTEST. To transmit the output of the fourth AND gate 83a or the rotation of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. That is, when the logic main control signal NORMAL is activated, 'the second memory controller 85 transmits a signal generated by the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1' and when the memory main control signal MEMTEST is activated, The second memory controller 85 transmits the signal generated by the fourth AND gate 83a to the second memory 19 in FIG. -25- This paper size applies to China _ National Standard (CNS) A4 specification (210X297 male splash) (Please read the precautions on the back before filling out this page)-Pack one -------- Order ------ --------------- Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _________ B7 V. Description of the Invention (23) ~ The first output controller 87 includes a 2 input j output multiplexer The second input controller 87 receives the serial number generated by the logic circuit 15 in FIG. I and the second memory 19 in FIG. 1 and transmits the output to the second output buffer 81b. The second output controller 87 is controlled by the king control letter, that is, when the logic king control letter is activated, the second output controller 87 transmits the signal generated by the logic circuit 15 of FIG. 1 to the second output buffer 81b, and when activated When the memory main control signal is MEMTEST, the second-round output controllers transmit the signal generated by the second memory 19 in FIG. 1 to the second output buffer 8 ^. The first output buffer controller includes 9th and 6th AND gates 89a, 2nd logic gate 89c, and 1st NAND gate 89d. The π AND gate 89a receives the memory master control signal and the slave diagram} The output buffer enable signal TRST1 generated by the second memory 19 is when the master control 彳 δ MEMTEST or the roll-out buffer enable signal TRST2 is logic low The sixth AND gate 89a generates a logic low signal, and when the main control signal MEMTEST and the turn-out buffer enable signal are both logic high, the sixth AND gate 89a generates a logic high signal. The second logic gate 89c receives the output of the sixth AND gate 8 and the main control signal NORMAL. When the output of the sixth AND gate 89a or the main control signal 1 ^ 〇1? ^ 八 1 ^ 疋 logic high, the second logic The gate 89c generates a logic high signal, and when the output of the sixth AND gate 89a and the main control signal NOMAL are both logic low, the first logic gate 89c generates a logic low signal. The second NAND gate 89d receives the output of the second logic gate 89c and the power supply voltage vcc, and transmits the output to the control terminal of the second output buffer 81b. The second NAND gate 89d transmits the output of the second logic gate to the second output buffer. Punch 81b -26- This paper size is applicable to Chinese National Standards (CNS) A4 specifications (210X 2 male f) (Please read the precautions on the back before filling this page). 11 Central Bureau of Standards, Ministry of Economic Affairs Printed by employee consumer cooperative A7 B7 V. Description of the invention (24) Control terminal 'ie' When the output of the second remote gate 89c is logic low, the second NAND gate 894 generates a logic high signal, and when the second logic When the output of the gate 89c is logic high, the second NAND gate 89d generates a logic low signal. When the output of the second NAND gate 89d is logic low, that is, the second output buffer 81b is activated, and when the output of the NAND gate 89d is logic high, that is, the second output buffer 8 is not activated. action. FIG. 9 shows a merged memory logic semiconductor device according to a second specific example of the present invention. Referring to FIG. 9 'the merged memory logic semiconductor device 1 () 7 includes: first to sixth pads 4.11 ..'. H, — 113, 114., 115 and 116, the first built-in self-test device 121, the second built-in self-test device 123, the first memory 125, the second memory Ϊ27, and the logic circuit 129. External signals are input and combined through the first to fourth pads 111, 112, 113, and 114, and the memory logic semiconductor device 107 is merged, and signals of the combined memory logic conductor device are transmitted through the fifth and sixth pads. And ηδ to output 0 from the outside. Specifically, the first and second clock signals are turned into the integrated memory logic semiconductor device 107 through the first and second, η, 1η, and the external first and The second test enable signal is £ 11, one person and Enable-B are input through the third pad 113 and the third pad 114 to merge the memory logic semiconductor device 107. In addition, the first and second test result signals Err, r.a, and Error-B of the combined memory logic semiconductor device 107 are output to the outside through the fifth pad 1J5 and the sixth potential 116. The first built-in self-tester 121 receives the first clock signal aock_A and the first test enable signal Enable_A, and generates the first control letter nj, which is ranked 27. This paper is applicable to China National Standard (CNS) A4 Specification (^^ 7 ^ 7 II I.---II--II I \.-I ί (Please read the precautions on the back and fill in this page), \ s ° Central Standard of the Ministry of Economic Affairs A7 B7 printed by the Bureau ’s Consumer Cooperatives 5. Explanation of the invention (25) Address strobe signal RASB, row address strobe signal CASB, address signal Addr, nesting enable signal WEB and input data signal Datain to Apply to the first memory 125 and receive the first output data signal Dataout —A from the first memory 125 to output the first test result signal Error_A to the fifth integer 115 ° The second built-in self-tester 123 receives the second clock The signal Clpcl £ __B and the second test enable signal Enable_B generate a second control signal 133, that is, a column address strobe signal RASB, a row address strobe signal CASB, and an address signal Add. No. WE & · and · Input the data-in signal Data-in to apply to the first memory 127, from the first The second memory 127 receives the second output data signal Dataout-B and therefore outputs the second test result signal Erf〇r__B to the sixth pad 116. The first and second memories 125 and 127 are used to store data, including: respectively. To the input ends of the first and second built-in self-testers 121 and 123, respectively, to the output ends of the first and second built-in self-testers 121 and 123, the first memory 125 generates the first output data signal DataoiU__ A responds to the first control signal 131, and the second memory 127 generates a second output data signal Dataout_B in response to the second control signal 133. The logic circuit 129 controls the first and second memories 125 and 127. Figure 12 Signal timing diagrams of memory logic semiconductor devices used to test merged memory according to the second to fourth specific examples of the present invention. Referring to FIG. 12, the first clock signal Clock__A or the second Clock_B and the first test enable signal Enable are generated. —A or the second test enable signal Enable__B, and then generate the second control signals 13 1 and 133. After a preset time T1, the first or second test -28 is produced.-This paper size applies Chinese national standards ( CNS) Λ4 specifications 210X297 public trend) (Please read the notes on the back of this page and then fill in) installed ·

11T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 ----------- B7 V. Description of the Invention (26) ~ — Output the data signal D_Ut__MData〇ut__B, and then after a preset time, the first -Or the second test result signal Test 0m-eight or Ding Ru _ B. — The following describes the operation of the memory logic semiconductor device 7 according to the second embodiment of the present invention with reference to FIG. 12. Here, the operation and test of the first test = 125 to the first built-in self tester ⑵ The operations of the second memory 127 to the first built-in self-test device I23 are the same, so the operations of the first memory I25 to the first built-in self-test device U1 will be tested. When the first test is enabled, the signal. Eivaiber-A is enabled when the logic is high, the second built-in self-tester 121 is activated 'in this state' When the first clock signal Ciock-A is enabled to the logic high, that is, A first control signal 131 is generated from the first built-in self-tester 121 to be applied to the first memory 125. After a preset time, the first memory 125 generates a first output data signal Dataout-A as shown in FIG. II, in response to the first control signal 131 to be applied to the first built-in self-test 121 . The preset time T1 in FIG. 12 refers to a period of time. Once the first control signal 131 is input and the result is output as the first output data signal Dataout-a, that is, P is used to start and operate the first memory 125. The first built-in self-tester 121 analyzes the first output data signal Dataout_A and generates a result as the first test result signal Error_A to transmit to the fifth pad i5. The first built-in self-tester i2 i needs a time T2 as shown in FIG. 12 to analyze the first round of data signals 1) " 3〇1 ^-A and output the first test result signal Err0r-A, the first —Test result signal Error—A determines whether the function of the first memory 225 is normal. When the number of memories in the semiconductor device 107 in FIG. 9 increases, the number of built-in self-test devices 'the number of clock signals and the number of test enable signals' both increase to equal to -29. CNS) A4 specification (210X297 mm) -------— 'i pack — (Please read the precautions on the back side before filling in this page on J5)

1T A7 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (27) Number of memory. When the first and second test enable signals Enable_A and Enable_B are enabled at the same time, that is, the first and second memories 125 and 127 are tested at the same time »so the time of testing the first and second memories 125 and 127 is It is the same time as testing a memory, and in addition, the conventional pads are used together without the first to sixth pads 1U, 112, 113, 114, 115, and 116 to reduce the number of pads and manufacturing costs. FIG. 10 shows a merged memory logic semiconductor device 207 according to a third embodiment of the present invention. The merged memory logic semiconductor device 207 includes: first to fifth pads 2112, 213, 244-, 215, and -21-6 , The first and second built-in self-testers 221 and 223, the first and second memories 225 and 227, and the logic circuit 229 ° 5 external signals are input and combined through the first to third pads 21i, 213, and 214 The memory logic semiconductor device 207 outputs the combined signals of the memory logic semiconductor device 207 through the fourth and fifth pads 215 and 216. In detail, the external logic signal is input and combined into the memory logic semiconductor device 207 through the second pad 211, and the external first and second test enable signals are input and combined through the first and third pads 213 and 214. Memory logic semiconductor device 207. In addition, the first and second test result signals Enror_A and Error —B of the combined memory logic semiconductor device 207 are output through the fourth pad 215 and the fifth pad 216. The first built-in self-tester 22 1 receives the clock signal Clock and the first test enable signal Enable_A, and generates a first control signal 23 1, namely, the column address strobe signal RASB and the row address strobe pulse. Signal CASB _, address signal Adds, nest enable signal WEB and input data signal Datain to apply to -30- This paper size applies Chinese National Standard (CNS) A4 specification (210X29 " / mm) 'install- -(Please read the precautions on the back before filling out this purchase), \ = ° Employees' Cooperatives of the Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives A7 B7 V. Description of the Invention (28) The younger brother recalls 225 in one year. In addition, the first output data signal Dataout__A is received from the first memory 225 to output the first test result signal Err_r__A to the fourth pad 215. The second built-in self-tester 223 receives the clock signal Clock and the second test result. The enable signal Enable_B, ϋ generates a second control signal, namely the column address strobe signal RASB 'row address strobe signal CASB, the address signal Addr, the nest enable signal WEB and the input data signal Datain 4 Apply to the first memory 227, and receive the second output data signal '· -3 from the second memory 227 to output the first test. Test. The result belongs to -Error-B to the fifth integer 216. The first and second memories 225 and 227 are used for storing data, including: connected to the input ends of the second and second built-in self-testers 221 and 223, respectively, and connected to the first and second built-in self-testers respectively 221 and 223 output. The first memory 225 generates a first round-out data signal Dataout-A in response to the first control signal 1 'and generates a second output data signal Dataout-b in response to the second control signal 233. The logic circuit 229 controls the first and second memories 225 and 227. The operation of the merged memory logic semiconductor device 2007 according to the specific example of FIG. 3 of the present invention will be described below with reference to FIG. U. In the merged memory logic semiconductor device 2007 of FIG. The operation of a built-in self-tester 22m testing the first memory 225 is the same as the operation of the second built-in self-tester 223_testing the second memory 227. The operation of the first memory 225 is tested. When the first test enable signal Enable_A is enabled, which is logic high, the built-in self-tester 221 is activated. In this state, when the first clock signal ciock is enabled ___ -31-I paper size is suitable) ~ Listening (2ωχ297 公 楚) (Please read the note on the back before filling in this page)

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (29) When the logic high is reached, the first control signal 23 from the first built-in self-tester 221 is applied to the first memory Body 225. According to the preset time η in FIG. 12, the first memory 225 generates a first output data signal 1) £ ^ 〇 plus _ ^ in response to the first control signal 23i to be applied to the first built-in self-test 221 . The preset time τι in FIG. 12 refers to a period of time-once the first control signal 231 is input and the result is output as the first output data signal Dataout "A, that is, used to start and operate the second memory 225. The first internal The self-tester 2.4 analyzes the first-output. Data signal Dataout-A and generates the result as the first test result signal Εγγογ__Α to transmit to the first .. Four .. The pad generates an output data signal and adds 1 A to generate the first The time of the test result signal “a” in FIG. 12 is T2 »The first test result signal (“ 1 ”) determines whether the function of the first memory 225 is normal. _ — I When the number of memories in the semiconductor device 207 in FIG. 10 increases, the number of built-in self-tests and the number of test enable signals both increase to equal the number of memories. However, there is a common clock signal. When the first and second test enable signals Enable_A and Enable_B are enabled at the same time, the first and second memories 225 and 227 are tested simultaneously. Therefore, if the first and second test enable signals Enable—eight and Enable—B are enabled at the same time, the time to test the first and second memories 225 and 22? Is the same as the time to test one memory. Add the first to the fifth 塾 211, 213, 214, 215 and 216 together to use the conventional replacement to reduce the number of 塾 and the manufacturing cost. Group 11 shows the merged memory logic semiconductor device 307 according to the fourth embodiment of the present invention. The merged memory logic semiconductor device 307 includes: first to fifth pads 311, 313, 314, 3 15 and 3 16, each Self-Tester 321, -32- This paper ϋΐϋ Chinese National Standard (CNS) Λ4 specification (210X297 mm) ~~~ '~ ---------' W clothing ------, 1T- -----) 0 (Please read the notes on the back before filling this page) A 7 B7 V. Description of the invention (3Q) The first and second memory 325, 327, and logic circuit 329. The memory logic semiconductor device 307 that inputs external signals through the first to third pads 311, 313, and 314 and merges, and the memory logic semiconductor device that outputs and merges through the fourth and fifth pads 315 and 3 16 307 signal. In detail, the external clock signal Clock is input to the combined memory logic semiconductor device 307 through the first pad 211, and the external first and second test enable signals EnaWe_A and Enable__B are transmitted through the second pad 3'13. A memory logic semiconductor device 307 that is input and combined with the third pad 314. In addition, the combined memory logic semiconductor device _ · 307〇 the first '• and the second test result signals Error_ A and Error-B are output to the outside through the fourth pad 315 and the fifth pad 316. The built-in self tester 321 receives the clock signal Clock, the first and second test enable signals EnaMe_A and Enable__B, and generates the first and second control signals 33 1 and 333, ie, the column address strobe signal RASB, the row bit The address strobe pulse enable signal CASB, the address signal Addr, the enable signal WEB and the input data signal Datain are applied to the first and second memories 325 and 327. Receive first output data signals 1 ^ (3〇1 ^ -A and Dataout-B) from the first memory 325 and the second memory 327 to output the first and second test result signals Error-A and Error-B to the first Fourth and fifth pads 3 15 and 3 16. The second control signal 333 can share the first control signal 331. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) The second memory 325 and 327 are used for storing data, including the input terminal connected to the built-in self-test device 321 and the output terminal connected to the built-in self-test device 321. The first memory 325 generates the first output data. The signal Dataout___A is in response to the control signal 33 1 and the second memory 327 generates the second output data. The signal Dataout-B is in response to the second control signal 333. -33- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297) A7 B7 V. Explanation of the invention (31) The logic circuit 329 controls the first and second memories 325 and 327. The following is a description of the fourth specific example of the present invention with reference to FIG. Operation of the memory logic semiconductor device 307. When the first test enable signal Enable_A is enabled, that is, a logic high, the first built-in self tester 321 is activated. In this state, when the first clock signal aock_a is enabled to a logic high, that is, A first control signal 3 3 1 is generated from the first built-in self-tester 321 to be applied to the first memory 325. After a preset time η according to the figure, the first memory 325 generates a first output data signal Data〇ut-A, in response to the first control signal No. 331, and added to the built-in self-test 321. The preset time T1 in FIG. 12 refers to a period of time, once the first control signal 331 is input and The output result is the first output data signal Data_ut_A, that is, used to start and operate the first memory M5 a. The first built-in self-tester 32i analyzes the first output data signal Datacmt_A and generates the result as the first test. Result signal Wuting 〇1: One person is transmitted to the fourth pad 315. A hunger data signal of 13 产生 is generated — A is needed after T2 of FIG. 12 to generate a first test result signal Εγγ〇γ_α · 7 First test result Signal Error-A determines whether the function of the first memory 3 is normal. Test 4 The second memory 327 The operation is the same as that of the test of the first memory 325. Here, the clock signal Clock is shared with the built-in self-test 321 to operate the function of the first memory 3 2 7. The function test 'so when the first and second tests Enable signal Enable — When A and EnaMe ^ _B are enabled at the same time, the first and second memories 32S and 327 are tested simultaneously. Therefore, the time to test the first and second memories 325 and 327 and the time to test one memory Equal, which reduces test time. In addition, the first to fifth pads 311, 313, 314, 315, and 316 are not added. -34- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297) and installed— (Please read the back Note: Please fill in this page again.) 11. Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7. ® When the number of memory is increased in the semiconductor device of FIG. 11, the number of test enable signals is increased to match the number of memories. However, a built-in self-test and a clock signal β are used together. Figure I3 is according to the present invention. The flow chart of the test method of the combined memory logic semiconductor shovel device is shown in FIG. I3. The memory test method of the combined memory logic semiconductor device 407 includes the following steps: activating the first memory (401), Start the second memory (411), read data from the first memory (421), + read from the second memory .. (434)-the data will be nested into the first memory (441), Data writing second The memory (45) reads the data from the first memory (46), reads the data from the second memory (471), pre-charges the first memory (481) and charges the second memory ( 491). In the step of activating the first memory (401), the built-in self tester 321 is activated by an external signal, and the built-in self tester 321 activates the first memory 425. When the first memory is activated (411) In the step, the built-in self-tester 32 丨 activates the second memory 427. In the step of buying the data by the younger brother (421)? The built-in self-tester 321 reads and stores in the first 425 The data stored in the second self-tester 321 reads the data stored in the second memory 427. In the step of reading data from the first brother (§ 313), the built-in self-tester 321 reads the data stored in the second memory (427). 441), the built-in self-tester 321 writes the data '1,' or '〇, into the first 425. In the step of entering data into the first memory (4 5 1), the built-in The self-tester 3 2 1 writes the data 4 1, or '〇, and writes it to the second 427.' '35, This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 cm). —¾ 丨 I ( Please read the precautions on the back before losing this page),-= · 0 A7 B7 V. Description of the invention (33 In the first memory (46 0 and then read the data M ^) Little knowledge, built-in self-test The male 1 guest took the data written in the first memory 425, and the legitimate M α's Saitama a 丄. The main test file 425 in the memory 425 test was incorrectly stored in the built-in self-tester 3 2 In the tester ^, the data read from the -memory 425 is compared with the reference data, and the right-fetched data is different from the reference data repeatedly-an error signal is sent. In the step of reading data from the second memory (47 丨), the built-in self-test reads the data written in the second memory 427, and in the built-in self-test 321, the smell is taken from the first Second memory. Body 427 'Compared with reference and test data, and if the read data is different from the reference data, an error signal is generated and transmitted outward. In the step of precharging the first memory (481), it is "the previous step is used to write data to the first memory 425 or read data stored in the first memory 425, to precharge the first memory A memory 425. In the step of precharging the second memory 427 (491), it is a previous step for writing data to the second memory 427 or reading data stored in the second memory 427 , Pre-charge the second memory 427. Economy. Then the Central Consumers ’Bureau Consumer Cooperative printed by the method of the present invention can execute the test of the first and second memory 425 and 427, when the first and second When the memories 425 and 427 are 16M synchronous memories, the tests of the first and second memories 425 and 427 of the 14N Y-forward algorithm can be expressed by the following formula 1. Here, it is assumed that the data bus transmits 64 bits. (Formula 1)

Test period = data format X class X 12 8 K

-I

= 2 X 6 X 128K 36- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) A7 V. Description of invention (¾ B7 = 1,572,864 (cycle time) About the first and second memory 425 And 427 'method to execute all levels at the same time. S ^ · 3 11 clocks of Table 3 need to cross

-L_ Action 2 Standby 3 Standby Standby Read 6 Standby 7 8 9 10 11 Nesting Standby ··-· Reread. Take Precharge Standby Standby Action Standby Read Standby Read Standby Read Standby Read Precharge * — * · * • «> rr — ------ The first and second input data of the first round of data, the first of the second capital and the second round of output of the first round of resources, so the first—the total of the second memory 425 and 427 — Formula 2 means: J 忒 time can be from the following (please read the precautions on the back before writing this page).

1T Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Formula 2) Test time = 1,572,864 X 11 = 325,301,504 (cycle time) According to the formula 2 of the present invention, the test time is about the conventional test sleep, which is based on The memory test time of the present invention is reduced, 55% of 9, and 45% of the body test time. 1 is about conventional memory. The interleaving method according to the present invention is used to have 3 or more? A memory ta logic semiconductor device merged by the memory body, thereby greatly reducing the time. At the time of memory test -37- This paper size is applicable to China Lai Jia Standard (CNS) Λ4 is present (21QX 297 Gongchu) A 7 B7 V. Description of the invention (35) According to the present invention, it can be used without adding a whole It is common practice to test the internal memory, which can suppress the increase in manufacturing costs, and in addition, the time required to test the memory will be greatly reduced regardless of the number of memories. It is understood that the present invention is not limited to the specific examples described, and those skilled in the art can make many changes and modifications in the scope of the present invention. --------- Equipment ------ π -------- J (Please read the notes on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs- 38- This paper size is applicable to China National Standard (CNS) A4 (210X 297g t)

Claims (1)

Printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A8 B8 C8 ____ .. _ D8 VI. Patent Application Scope · A merged memory logic semiconductor device containing: a lot of memory; 其' It receives memory control signals for Controls many memories; other 接收 'receives data signals from or receives data from many memories;-logic circuits to control many memories; and a test control circuit, connected to other pads, logic 'Dong Lu and many memories' are used to transmit memory control signals and memory data signals when testing many memory devices .. Many. Record. Certificates, in order to respond to a test control signal, and a Used to transmit memory control signals and memory data signals to logic circuits during normal operation. 2. A merged memory logic semiconductor device, comprising: a first and a second memory; one of which receives a memory control signal for controlling the first and second memories; the other of which receives from Memory data signals generated by the first and second memories, or transmitting memory data signals to the first and second memories; a logic circuit for controlling the first and second memories; and a memory test control Circuits, connected pads, other pads, logic circuits, and first and second memories, used to transmit memory control signals and memory data signals to the first and second memories when testing the first and second memories 'And—used to transmit memory control signals and memory data signals to logic circuits during normal operation. 3. The combination of the memory logic semiconductor device of item 2 of the Shenlong Patent Fanyuan ____ -39- ^ 值 Gu f-, device ------ ΪΤ ------- I.-— V. (Please read the precautions on the back before filling this page) 6. Scope of patent application 4. Αδ Β8 C8 D8 The central standard of the Ministry of Economic Affairs is printed for employee consumer cooperatives, in which the memory test control circuit includes: a memory control A signal controller for transmitting memory control signals to the first and second memories and logic circuits; a memory data controller for transmitting memory test signals to the first and second memories and logic Circuit, or the memory data signals generated from the first and second memories and logic circuits are transmitted to other camps; and a main control signal generator is connected to the memory control signal controller and the memory data controller To control the memory control signals to be transmitted to the first and second memories, and the logic · electrical-circuit to return. The control signals should be tested, and the memory data signals to the first and second memories and the logic circuit to transfer From first to first; memory and logic circuits Memory data signal ^ 5 he Sook. — Yili ^ Tfe-made circuit 'is connected to one pad, the other pad, and a logic circuit. First and second memory. When the second memory is to be tested, the memory control signal is transmitted with Memory data signals to the first and second memories, and a normal circuit for transmitting memory control signals and memory data signals to a logic circuit. The memory test control circuit includes a memory control signal controller, Used to transmit memory control signals to the first and first memories and logic circuits;-a memory control signal controller to transmit memory data signals to the first and first memories and logic circuits, or The memory data signals generated from the first and second memories and logic circuits are transmitted to other pads, as well as the first memory number and the number (please read the precautions on the back before filling this page) -40- See paper Applicable to China National Standard (CNS) A4% # (2 丨 〇χ297mm) A8 B8 C8 D8 Patent application scope-a main control signal generator, connected to the memory control signal controller and memory data controller, The connection memory control signal is transmitted to the first and second memories and the logic circuit in response to the test control signal, and the memory data signal is transmitted to the first and second memory and the logic circuit to others. The memory test control circuit of item 4, wherein the main control signal generator is a generator, and when the second and second test control signals are inactive, the memory control signal controller outputs and records the body material. Controller .. Output ~ Transfer to the first memory unit. When the first and second test control signals act, the output of the memory control signal controller and the output of the memory data controller are transmitted to The second memory unit 'does not transmit the output of the memory control signal controller and the output of the memory data controller to the logic circuit when the first test control signal is inactive and the second test control signal is activated. 6. The memory test control circuit of item 4 of the patent application park, wherein the memory control signal controller includes: a buffer 'for receiving the memory control signal; a logic gate for receiving the output of the buffer And the main control signal are transmitted; an output to the logic circuit; and a consumer controller of the Central Standards Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs prints a memory controller to receive the logic closed output and the logic circuit output and transmit the output of the logic gate The output of the AND logic circuit goes to the first and second memories' in response to the main control signal. Logic 7. If the memory test control circuit in item 6 of the scope of patent application, the gate includes: ”-41-This paper size applies to China National Standard (CNS) A4g (210X297 mm) ABCD Employees of the Central Standards Bureau of the Ministry of Economic Affairs Consumption cooperative prints a patent application, a first AND gate, which is used to receive the output of the buffer and the -th-main control signal from the main control signal generator. When the _th main control signal is logic high, the transmission delay The output of the buffer to the memory controller, and to prevent the output of the buffer when the first main control signal is logic low, a second AND gate for receiving the output of the main control signal and the generation from the main control signal One of the second main control signals, when the second main control signal is logic high, the output of the buffer is transmitted to the logic circuit, and when the first main control signal is low, the buffer is blocked. Turn-out · and—the third AND brake switch, take-receive-buffer, the output and the third main control signal of one of the signal generators, go to the _ · 'second, ^ Tian Fu two king control signal Han logic High, teleport The output of the street device to the memory control device and the third main control signal is logic low to prevent the output of the buffer. 8. For example, the memory test control circuit of the patent application No. 6 and the memory controller Contains:% 8-the first multiplexer 'is used to receive the potential of the logic circuit ^ burst and logic gate output and transmit the output of the logic circuit or the output of the logic gate to the first-memory unit in response to the main control signal ; And a second multiplexer 'for receiving the logic circuit Sakizaki <output and logic gate output and transmitting the logic circuit's output and logic, m mτο in response to the main control signal. 9. If the scope of the patent application The memory test control of the 4th item. The memory data controller contains: qi 'where \ input / output buffer to apply the memory micro $ p; U body I material signal to the memory of the memory of the memory Its (notes on the back of the readers, please fill in this page). · 1T -42- Chinese paper standard (CNS) is applicable for private paper size. M Ting _ (21〇 &gt; &lt; 297 public splash) Application scope of patent A8 B8 C8 D8 Central Bureau of Standards, Ministry of Economic Affairs The industrial and consumer cooperatives print the logic gates to receive the output of the input / output buffer and the main control signal and send a round out to the logic circuit; the memory controller 'is used to receive the output of the logic gate and the logic circuit turn out and transmit Logic gate (output or output of logic circuit to the first and second memories in response to the main control signal; 〃-turn-out controller 'is used to receive the memory data signals and logic circuits generated by the first and second memories At the same time, the memory generated by the body "material second memory money material circuit output to the input / output buffer, in order to respond to the master. Control. System | number; and: the output buffer controller to receive the master control Signal and the first—memory resource signal generated by the fish memory body, transmit input ^ input; :: buffer: and, when the output action is through the input / output buffer into the output of the output controller, and when the wheel is out During the action, the output of the output controller is not transmitted through the wheel output buffer. 81 ίο. If the memory test control circuit of item 9 of the patent application park, the input / output buffers include: 、 Middle wheel: input buffer, use 忆 to recall the material number to logic;-output Buffer 'is used to transmit the output of the output controller in response to the output buffer controller. 11. ^ The memory test control circuit of item 9 of the patent application park, the gates include:, Middle-: the fourth AND gate, used to receive the -brother-master control signal of the input / output buffer, and the first-master When the control signal is high, please use the book binding with the factory. ^ '. Ball (please read the notes first and fill in this page before filling in this page) 43- Spring paper scale applicable tiiii ^ NS) A4a ^ (210 ^ ^ 17 A8 B8 C8 D8 System: ΓΑ two idles, used to receive the rotation of the buffer and-the second master control = logic = the two main control signal is logic high, the output of the buffer is transmitted to the logic circuit, and this flute-the central standard of the Ministry of Economic Affairs Bureau employee consumer cooperative prints the output of the buffer to the memory system! wm control, and when the first main control signal is low, stop the output of the buffer. Prevent the rotation of the buffer; to: when the control signal is logic low,-the sixth AND gate to receive the buffer The control signal of the device, when the third master controls the horn, recognizes Xingdi and Wang. When it comes to logic, the output of misinformation and the input of evil is sent to the memory control device. Let's go to the first, "'' Eye M, ^, and the Tian Wang two control signals when the logic is low, to prevent buffering. Device output. 12. If t, please refer to the memory measurement controller of item 9 of the patent scope, which includes: τ multiplexer to receive the output of the logic circuit and the output of the logic gate and combine the output of the logic circuit and the output of the logic gate to The first memory is in response to the main control signal; and the output of the heart receiving circuit and the logic closed output are transmitted to the second memory in response to the main control signal. &quot; 13. If you apply for a patent_ the 9th memory test control circuit, where the output controller is a multiplexer to receive the memory data signal and the output of the logic circuit from the first and second memories, and transmit The memory data signals generated by the first and second memories and the output of the logic circuit are the main control signals. 14. For example, the memory test control circuit of item 9 of the patent application chart, where -44- -------- ^ ------ 1T ----- ί \. {.. (Please read the precautions for the back page first and then fill out this page) & The paper size applies the Chinese National Standard (CNS) A4 size (210X297 mm) ABCD, patent application Fanyuan buffer controller includes: The first avoidance A gate for receiving the main control signal to control the first and second memory units; and a second logic gate for receiving the memory data signals of the first and second memory unit sounds; a seventh An AND gate is used to receive the output of the first and second logic gates; a third logic gate is used to receive the seventh g between the AND output and the main control signal to control the logic circuit; and '-NAND gate'. Receiving the output of the first three logics and the power supply voltage and transmitting the output to the input / output buffer. '、 15. For example, if the memory test control electronics of Item 4 of the patent application park, the main control signal generator is activated when the spring test control signal is activated, and the logic main control signal is activated when the test control signal is not activated. . 16. The memory test control circuit of item 4 of the patent application, wherein the memory control signal controller includes: a buffer to receive the memory control signal; a logic closed to receive the output of the buffer, A memory main control signal and a logic main control signal and transmitting an output to a logic circuit; and a memory controller for receiving an output between logic and an output of the logic circuit and transmitting an output of a logic gate or an output of the logic circuit To the first and second memories in response to the memory main control signal and the logic main control signal. -Π. If the memory test control circuit of the patent application No. 16 is included, the gates include: &quot; -45- This paper size is applicable to the Chinese Standard (CNS) Μ specification (21〇297 mm) ( (Please read the precautions before you fill out this page before filling in this page), 1— 1!-»......... Printed by the Consumer Cooperatives of the Central Commission of the Ministry of Light Industry. -、 玎 ^ ------------------- Scope of patent application A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs—No. -AN⑽ for receiving buffers When the wheel of the device outputs fish, the signal is recorded. When the body-billion system is recorded, the memory control signal of the death control body is controlled by the high-speed signal output to the memory controller, and when the buffer is low, The output of the control signal of the blocking king is the second AN⑽ of the logic two, which is used to receive the signal of the buffer. When the logic main control signal is logic high, it is reversed, and the control circuit is sent out. The money is the logic master. The output of the buffer stops the output of the buffer; and when the remote number is low, the resistance-the third AN wins. The "buffer" device_receives the output signal when the memory master controls For the left foot number - referred to the control output I * Wang body referred to Xing body care system called .. When the &amp; 鬲 is set, the transmission buffer system is hidden, and when the memory is low, the output of the buffer is blocked. The memory controller of the U-series system, such as the U-item of the patent application scope, includes: a control circuit, of which-the-multiplexer, which receives and outputs the logic circuit, outputs and transmits the output and logic of the logic circuit The idle input I body responds to the main control signal of the memory and the main logic control. A second multiplexer is used to receive the logic electric number, the output of the% 崎 and the output of the logic gate and transmit the output of the logic circuit. The output of the AND logic gate is sent to the second memory in response to the memory master control signal and the logic master = ^ control signal. 19. The memory test control of item 4 of the patent application park n a memory data controller includes: 〃 a first input / output buffer to apply a memory data signal therein; a logical memory and a memory first to— -^ ------- Factory-installed ------ ΐτ ------ i (Please read the precautions on the back before filling out this page) -46- This paper; ^ degree is applicable to China Standard (〇 阳) 8 specifications (210 \ 297 mm) The scope of the patent application is printed out by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and the memory is recalled to receive the input from the first-round input / output buffer to the logic circuit; &quot; System 彳 § number and logic main control signal And send an output logic circuit 'for receiving, — the output between logic and output to the second — and send the output of the — logic gate or the control signal of the logic circuit;', body, in response to the main control of the memory Signal and logic master, two human ft spots: controller 'is used to receive the memory memory path generated by the -th memory and go out and send the output of the punch circuit generated by the -memory to the -input field Ease. Should be the main memory control signal and logic main control signal; the serial number wheel: the buffer controller, used to receive the memory main control signal system signal and the memory data generated by the first memory unit: And send the wheel out to the first-round input / output buffer, when the output of the wheel-out buffer controller is actuated, the output of the first-output controller is transmitted through the first output W punch, and the output buffer control Loser When there is no action, it passes through the first input / round out buffer without transmitting the output of the first output controller. 20. The memory test control circuit according to item 19 of the patent application park, wherein the first input / output buffer includes:-a first input buffer for transmitting a memory data signal to the first logic gate; and —Output buffer for outward transmission of the first 'Output Controller'-47- This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page ) .-I!---........ I — ^ 1 1 Is -....... \---..... I In n I! I '^^, vm Aged --- --i-in ........-1 I--....... ..... · A8 B8 C8 D8 Printed by the Consumers' Cooperative of the China Railway Bureau of the Ministry of Light Industry System 6: Patent application scope output in response to the first output buffer controller. 21. The memory test control circuit according to item 19 of the patent application scope, wherein the operation gate includes: a first AND gate for receiving the output of the first input / output buffer and the main control signal of the memory, and sending When the main control signal of the memory is transmitted, the output of the first input / round-out buffer is transmitted to the first memory controller, and when the main control signal of the memory is logic low, the output of the first input / output buffer is blocked; The first and the alarm are used to receive the first .. output of the input / output buffer and the main control signal. When the main control signal is logic high, transmit the output of the first — input / output buffer to the logic circuit, and When the main production number is logic low, the output of the first input / output buffer is prevented. 22. The memory test control circuit in item 19 of the patent scope, where the first memory controller is a multiplexer to receive logic mines, the output of the first logic gate and the output of the first logic gate, and transmit the logic circuit The output and the output of the first logic gate respond to the main control signal of the memory and the control signal of the logic φ. 23. If the memory test control circuit of item 19 of the patent application park, wherein the first output controller is a multiplexer for receiving the memory data signal and the output of the logic circuit generated by the first memory unit, And transmit the memory data signal or the wheel of the logic circuit generated by the recorder's memory. "J W 主 弟"-the input / output buffer, in response to the memory main control signal and the logic master # control signal. 2. 24. If the memory test control circuit of item 18 of the scope of patent application, the ___ -48- ϋ 氐 Zhang National Standard (CNS) secret line (Canada Dong 1 1 --- (Please (Please read the notes on the back before filling out this page) A8 Βδ C8 D8 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs. 6. The scope of patent application. The output buffer controller includes: a third AND, used to receive the main control signal of the memory and generated by the first memory unit. Memory data signals; a first logic gate to receive the output of the third AND gate and the main control signal; and a first NAND gate to receive the output of the first logic gate and the power supply calendar. … .25 · If the patent application for the fourth memory test control circuit, the second memory data control .. controller package. Contains ::-…--a second input / output buffer, The memory data signal is applied to it; \ —The second logic gate is used to receive the output of the second input / output buffer, the main memory control signal and the logic main control signal, and send out a round to the series. Circuit; a second memory controller for receiving the output of the second logic gate and the output of the logic circuit and transmitting the output of the second logic gate or the rotation of the logic circuit to the second memory in response to the memory Main control signal and logic main control signal;-a second output controller for receiving the memory data signal and the output of the logic circuit generated by the second memory, and transmitting the memory data signal or logic generated by the first and the memory unit The output of the circuit is sent to the second input / round-out buffer in response to the main memory control signal and the logic main control signal; and—the second output buffer controller is used to receive the main memory control signal. National Standard (CN``) A4 · (210x ^ i ^ · (Please read the precautions on the back before filling out this page) ^ ------, 玎 --------- Patent application scope number. , Logic year control signal and flute-.Α birth memory data signal, remember the sister input / output buffer production + middle when the second output buffer controls the input / output buffer and transmits the fifth operation through the first Second ^ ^ The first—the output controller's wheel 4 », the second output buffer controller Ling Lingshan af I passes through the first network λ / output buffer without transmitting the first _ and 罘 —input wheels when the output action is taken. Out of the controller's rotation. If one of the patent application Fanyuan recognizes the hidden body, try the control circuit, where 筮 —input / output buffer contains: 'Brother blowing transmission notes, logic gates; and Beizhu L to Diyi. Out of the controller-the second output buffer, used to pass the second output to the fan in response to the second output buffer controller. 27. For example, if you apply for the memory test control circuit of Item 25 in the patent park, and approved the two logic gates include: "A 4th AND gate, used to Receive the second input / round out buffer's rotation out and the main memory control signal. When the main memory control signal is logic ^, 'transmit the output of the second input / output buffer to the second _ two spears-memory The controller, and when the main control signal of the memory is logic low, prevent the output of the first input / round out buffer__ and the fifth ANDM to receive the output of the second input / output buffer and the main control The signal, when the main control signal is logic high, transmits the output of the first input / output buffer to the logic circuit, and when the main control signal is logic low, prevents the second input / output retarder from rotating out.口 28. The memory test control circuit of item 25 of the patent application park, where -50- Applicable to China National Standard (CNS) A4 specification (210 ^^^ Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs, printed A8, B8, C8, D8. The scope of patent application 2 The memory controller is a multiplexer to receive the output of logic circuits And the output of the second logic gate, and transmit the output of the logic circuit and the output of the second logic gate to the memory, in response to the memory main control signal and the logic main control signal. Test control circuit, wherein the second output controller is a multiplexer for receiving the memory data signal and logic output generated by the second memory unit, and transmitting the memory data signal or logic circuit generated by the second memory It is output to the second input / output buffer in response to the memory control signal and the logic main control signal. 30. For example, the memory test control circuit of the patent application No. 25, wherein the second output buffer controls The device includes: a sixth AND gate for receiving a memory main control signal and a memory data signal generated by the second memory unit; a second logic gate Used to receive the output of the sixth AND gate and the main control signal; and-the second NAND gate is used to receive the output of the second logic gate and-the power supply voltage "31, such as the combination of the second item of the patent application park Memory logic semiconductor device, in which the memory system DRAM bank. 32. A type of merged memory logic semiconductor device, including: a lot of 蛰, applying one or more external clock signals and test enable signals to it; many other pads Γ '_ -51- This paper is loaded from the national standard of China (CNS> (21〇 &gt; &lt; 297 public envy) (Please read the precautions on the back before filling this page). 4 ° VI. The scope of patent application is at least 2 memories, which store data; and one or more Neiwei self-testers, which are used to test the memory function, respond to clock signals and test enable signals, and send the results to many other pads. 33. Such as The merged memory logic semiconductor device of the 32nd patent application, including the memory system DRAM bank. 34.-A merged memory logic semiconductor device including a logic circuit and a memory, the device The settings include:,: the first and second pads, which respectively apply external first and second clock signals to them; ............ · .y ----- /-third and fourth Pads, which respectively apply external first and second test enable signals to them; fifth and sixth pads; first and second memories, which store data; a first built-in self-test device, which is connected to the first memory A body unit, first and third, for testing the function of the first memory, in response to the first clock signal and the first test enable signal, and transmitting the result to the fifth pad; and a second built-in The tester is connected to the second memory unit, the second pad and the fourth pad, for testing the function of the second cockroach, in response to the second clock signal and the second test enabling signal, and transmitting the result to the first Six pads. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 35. If you apply for a combined memory logic semiconductor device with the scope of patent application No. 34, the memory system DRAM bank. 36. — A combined memory logic semiconductor device having a logic circuit and a memory, the device includes: a first coil, which applies an external clock signal to it _; -52- This paper size applies to Chinese national standards (CNS) A4 specifications (210X297 mm) A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Ladder Bureau of the Ministry of Economic Affairs 6. The second and third pads for patent application, plus external first and second test enable signals, respectively To it; the fourth and the fifth; the first and second memory units, in which data is stored; a first built-in self tester, connected to the first memory unit and the first and second pads for testing The function of the first memory is to respond to the clock signal and the first test enable signal and transmit the result to the fourth frame; and a second built-in self-tester is connected to the first memory unit and the first pad and The second pad is used to test the function of the first memory, the memory, the response to the clock signal and the first test enable signal, and the result to the fourth frame. _ 37. If you apply for the combined memory logic of item 36 of the patent, the semiconductor device, the memory system DRAM bank. 38. A merging memory logic semiconductor device having a logic circuit and a memory, the device includes: a first pad, which applies two external clock signals to it; a younger one and a younger one, applying an external first —Plate _: head, 丨 ^ ^ Dan Yi a test enable signal to it; the fourth and fifth pads; the first and second memory, which stores data; a built-in self-test, connected to the first The memory unit and the first to the first one are used to test the functions of the first and the second: the memory should be numbered and five pads. 15 39. For example, please refer to the combined memory logic semi-conductor of item 3.8 of the Patent Park, where the memory system DRAM bank. ^ Installation (please read the notes on the back before filling this page) Installation, π This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 6. Scope of patent application 'A8 B8 C8 D8 Ministry of Economic Affairs Printed by the Central Standards Bureau's Consumer Cooperatives. 40. A memory test method for the combination of the Great Logic Semiconductor device. The device has:-a logic circuit, a memory, and a built-in self-test. The method includes the following steps. Dish: Apply 'clock pulse No. 5.' and a test enable signal to enable the built-in self-test to the built-in self-test; the built-in self-test generates a control signal to test a function of the memory Ice Moon Dagger, "generates an output data signal from the memory; and from the built-in self-tester. Generate-test_-test-result Qian number to display the test results of the memory. 41. A kind of memory logic A memory test method for a semiconductor device, the device has: a built-in self-tester, connected to an external terminal, and many ☆ Ji Yihui 'The method includes the following steps: a) write data to the built-in self-tester and many Memory And b) the data in many memories are read by the built-in self tester. 42. The steps of writing data in the patent application include the following sub-steps: 1¾ inputting remnants: 轾. Say al) start a lot of memory A2) The built-in self-testing device reads the data in many memories; and mm turns _ to call the built-in self-testing device to store more data in the memory. 43, such as the patent application park No. 4 2 Among them, in the step a) of starting a lot of memory, start the built-in memory device to start a lot of memory. »,,,.. *:!.” Γίΐδρϊ3 a) According to 44_ Read, lrr3 steps? : 54- b) --------- Production ------ Ding ______ ^ Today, TJ (Please read the precautions on the back before filling out this page) ________- 54- The standard of this record applies China National Standard (CNS) A4 specification (21G x 297 public directors) Αδ B8 C8 D8 The scope of patent application includes the following sub-steps; M) The built-in self-tester reads the data stored in many memories; and b2) Charging the memory, 45. The method for testing memory according to item 41 of the patent application &gt; wherein in step a) of writing data, the built-in self-tester sequentially embeds the data into many memories. 46. For example, the method for testing memory of item 41 of the scope of patent application, wherein in step b) of reading data, the "built-in boat tester circulates data from a lot of memory. ^, '养' Please patent the stomach of Item 41 of the Fan Garden, in which the memory system DRAM is installed I: ----- Order ------ '^-(.. .... (Please read the precautions on the back first Refill this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs -55- Applicable to China National Standard (CNS) Α4 (210X297 mm)