GB2327506A

GB2327506A - Methods and means of testing memories of a combined memory / logic device

Info

Publication number: GB2327506A
Application number: GB9810262A
Authority: GB
Inventors: Jong-Hak Won; Jong-Taek Kwak; Sang-Bong Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1997-06-23
Filing date: 1998-05-13
Publication date: 1999-01-27
Anticipated expiration: 2018-05-13
Also published as: JP2007179731A; DE19823583A1; TW384477B; GB2327506B; GB9810262D0; JPH1117130A; DE19823583B4

Abstract

A memory / logic device 5 comprises memories 17, 19, a logic circuit 15 and test circuitry 13. The test circuitry 13 interconnects between input/output pads 7 - 10 of the device, the logic circuit 15 and the memories 17, 19 such that in a test mode the input/output pads 7 - 10 are directly connected to the memories 17, 19 and when in a normal mode the input/output pads 7 - 10 are coupled to the memories 17, 19 via the logic circuit 15. Also disclosed is a memory / logic device, and a method of testing the same, which comprises memories, input/output pads and one or more built-in memory test arrangements in which the said test arrangements respond to externally applied clock and test enable signals to provide test results on input/output pads. Further there is disclosed a method of testing a memory / logic device with a built-in test arrangement which comprises writing data in the test arrangement and the memories, then using the test arrangement to read the data stored in the memories.

Description

2327506 A MERGED MEMORY LOGIC SEMICONDUCTOR DEVICE The present invention

relates to a merged memory logic semiconductor device. and more particularly, to a memory test circuit for testing a plurality of memories of a merged memory logic semiconductor device.

In a merged memory logic semiconductor device, a memory, i.e., a dynamic random access memory (DRAM) or a static random access memory (SRAM) and a logic circuit for controlling the memory include to one semiconductor device. to realize a system that is small in size. lightweight, and delivers high performance with low power consumption.

To test the memory included in the semiconductor memory device, a test equipment is is connected to pads of the semiconductor memory. However, the memory installed in the merged memory logic semiconductor device cannot be tested. This is because the memory is connected to the pad through a logic circuit installed in the merge memory logic semiconductor device. Accordingly, pads are additionally required for testing the memory installed in the merged memory logic semiconductor device. However, when the number of the pads increases. a size of the merged memory logic semiconductor device increases, to thereby increase the manufacturing cost.

According to a first aspect of the present invention. there is provided a merged memory logic semiconductor device including: a plurality of memories; pads which receive memory control signals for controlling the plurality of memories: other pads to which memory data 1 signals received to or generated from the plurality of memories are applied: a logic circuit for controlling the plurality of memories; and a test control circuit connected to the other pads, the logic circuit and the plurality of memories, for transmitting the memory control signals and the memory data signals to the plurality of memories when the plurality of memories are tested. in response to a test control signal and for transmitting the memory control signals and the memory data signals to the logic circuit during a normal operation.

According to a second aspect of the present invention. there is provided a merged memory logic semiconductor device including first and second memories. a pad which receives memory control signals for controlling the first and second memories; another pad which receives memory data signals generated from the first and second memories or transmits memory data signals to the first and second memories; a logic circuit for controlling the first and second memories; and a memory test control circuit connected to the pad. the other pad, the logic circuit and the first and second memories, for transmitting the memory control is signals and the memory data signals to the first and second memories when the first and second memories are tested and for transmitting the memory control signals and the memory data signals to the logic circuit during a normal operation.

According to a third aspect of the present invention, there is provided a merged memory logic semiconductor device including: a plurality of pads to which one or more external clock signals and test enable signals are applied: a plurality of other pads, at least two memories in which data is stored; and one or more built-in self-tester for testing functions of the memories. in response to the clock signals and the test enable signal, and sending the 2 results to the other plurality of pads.

According to a fourth aspect of the present invention, there is provided a merged memory logic semiconductor device comprising a merged memory logic semiconductor device including a logic circuit and a memory, including: first and second pads to which external first and second clock signals are applied, respectively; third and fourth pads to which external first and second test enable signals are applied. respectively., fifth and sixth pads; first and second memories in which data are stored: a first built-in self- tester connected to the first memory unit. the first and third pads, for testing functions of the first memory, in response to the first clock signal and the first test enable signal. and sending the results to the fifth pad; and a second built-in self-tester connected to the second memory unit, the second pad and the fourth pad. for testing functions of the second memory, in response to the second clock signal and the second test enable signal. and sending the results to the sixth pad.

According to a fifth aspect of the present invention, there is provided a merged memory logic semiconductor device having a logic circuit and a memory, including: a first pad to which an external clock signal is applied; second and third pads to which external first and second test enable signals are applied, respectively; fourth and fifth pads, first and second memory units in which data are stored, a first built-in self-tester connected to the first memory unit and the first and second pads, for testing functions of the first memory, in response to the clock signal and the first test enable signal. and sending the results to the fourth pad: and a second built-in self-tester connected to the first memory unit and the first 3 and second pads, for testing functions of the first memory, in response to the clock signal and the first test enable signal. and sending the results to the fourth pad.

According to a sixth aspect of the present invention, there is provided a merged memory logic semiconductor device having a logic circuit and a memory, including: a first pad to which an external clock signal is applied; second and third pads to which external first and second test enable signals are applied, respectively., fourth and fifth pads., first and second memories in which data are stored, a built-in self-tester connected to the first memory unit and the first to third pads, for testing functions of the first and second memories, in response to the clock signal and the first and second test enable signals, and sending the results to the fourth and fifth pads, respectively.

According to a seventh aspect of the present invention, there is provided a memory test method of a merged logic memory semiconductor device having a logic circuit, a memory is and a built-in self-tester, including the steps of. applying a clock signal and a test enable signal for activating the built-in self-tester to the built-in self- tester; generating control signals for testing a function of the memory from the built-in self-tester: generating an output data signal from the memory; and generating a test result signal showing the test result of the memory from the built-in self-tester.

According to an eighth aspect of the present invention, there is provided a memory test method of a merged logic semiconductor device having a built-in self-tester connected to an external terminal and a plurality of memories, including the steps of: a) writing data in the 4 built-in self-tester and the plurality of memories: and b) reading data stored in the plurality of memories by the built-in self-tester.

Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a merged memory logic semiconductor device according to a first embodiment of the present invention:

FIG. 2 is a block diagram according to the first embodiment of a memory test control circuit of FIG. 1:

FIG. 3 is a circuit diagram of a memory control signal controller of FIG. 2; FIG. 4 is a circuit diagram of a memory data controller of FIG. 2; FIG. 5 is a block diagram according to a second embodiment of the memory test control circuit of FIG. 1:

FIG. 6 is a circuit diagram of a memory control signal controller of FIG. 5; is FIG. 7 is a circuit diagram of a first memory data controller of FIG. 5:

FIG. 8 is a circuit diagram of a second memory data controller of FIG. 5..

FIG. 9 is a block diagram of a merged memory logic semiconductor device according to a second embodiment of the present invention; FIG. 10 is a block diagram of a merged memory logic semiconductor device according to a third embodiment of the present invention..

FIG. 11 is a block diagram of a merged memory logic semiconductor device according to a fourth embodiment of the present invention; FIG. 12 is a timing diagram of signals of FIGS. 9 through 11; and, FIG. 13 is a flowchart showing a memory test method of the merged logic semiconductor device according to the present invention.

r, FIG. 1 is a block diagram of a merged memory logic semiconductor device according to a preferred embodiment of the present invention. Referring to FIG. 1, the merged memory logic semiconductor device 5 includes pads 7, 8. 9 and 10. a memory test control circuit 13. a logic circuit 15 and first and second memories 17 and 19.

The memory test control circuit 13 is connected to the pads 7, 8, 9 and 10, and the logic circuit 15 and the first and second memories 17 and 19. e.g DRAM banks are connected to the memory test control circuit 13.

A memory control signal PC for controlling the first and second memories 17 and 19 is applied to the pad 8. and test control signals TESTMDO and TESTNID1 for controlling the is memory test control circuit 13 are applied to the pads 9 and 10. Also, a memory data signal DQi input/output to the first and second memories 17 and 19 is applied to the pad 7. The pads 7 and 8 are existing pads for using the first and second memories 17 and 19, and the pads 9 and 10 are pads added externally to control the memory test control circuit 13.

A memory tester (not shown) is connected to the pads 7. 8. 9 and 10 to test functions of the first and second memories 17 and 19 of the merged memory logic semiconductor device 5. The memory tester (not shown) inputs the memory control signal PC and the memory data signal DQi to the memory test control circuit 13 through the pads 7 and 8. Also, the 6 memory test control signal 13 is controlled by a combination of the test control signals TESTY[D0 and TESTY[D1. Accordingly, in the testing of the first and second memories 17 and 19. the memory test control circuit 13 applies the memory control signal PC and the memory data signal DQi to the first and second memories 17 and 19. The first and second memories 17 and 19 operate by the memory control signal PC and the memory data signal DQi. and then the result is transmitted to the memory test control circuit 13. The memory test control circuit 13 transmits signals of the first and second memories 17 and 19 to the memory tester (not shown) through the pads 7 and 8. Accordingly. the memory tester (not shown) analyzes signals transmitted through the pads 7 and 8 to evaluate the functions of the first and second memories 17 and 19.

In the case that the merged memory logic semiconductor device 5 operates normally without testing the first and second memories 17 and 19, the memory test control circuit 13 does not partially operate due to the combination of test control signals TESTMDO and TESTMD1. When the memory control signal PC and the memory data signals DQis are applied externally to perform normal operation of the merged memory logic semiconductor device 5. the applied signals are input to the logic circuit 15, which controls the first and second memories 17 and 19 through the memory test control circuit 13.

The embodiment of the present invention is employed for a merged memory logic semiconductor device having two memories, however, may be employed for a merged memory logic semiconductor device having one or more memories.

7 As described above. the merged memory logic semiconductor device 5 according to the embodiment of the present invention may test the first and second memories 17 and 19 using the conventional pads 7 and 8.

FIG. 2 is a block diagram of the memory test control circuit 13 of FIG. 1 according to a first embodiment. Referring to FIG. 2. the memory test control circuit 13 according to the first embodiment includes a main control signal generator 23, a memory control signal controller 25 and a memory data controller 27.

In the main control signal generator 23, the test control signals TESTMDO and TESTMD1 are applied to an input terminal, and an output terminal is connected to the memory control signal controller 25 and the memory data controller 27. The main control signal generator 23 generates main control signals MEWEST1, MENITEST2 and NORMAL. in response to the test control signals TESTMDO and TESTNIDI. For example. the main control signal is generator 23 has truth values as shown in Table 1.

0 (Table 1)

Function TESTNID0 TESTNID1 Main control signal First memory test L' U MEWEST1 Second memory 1H3 L? MENITEST2 test Normal operation 'U 'H? NORMAL H' 'HY Hold present state a As shown in Table 1, when the test control signals TESTNID0 and TESTMD I are logic low U, the main control signal MENITEST1 is made active to test the first memory 17 of FIG. 1, and when the test control signal TESTNID0 is activated to logic high 'H' and the test control signal TESTMD I is logic low 'L', the main control signal MENITEST2 is active to test the second memory 19 of FIG. 1. Also, when the test control signal TESTMDO is logic low U and the test control signal TESTMD1 is logic high 'H', a signal NORMAL is active to normally operate the logic circuit 15 of FIG. 1. When the test control signals TESTNID0 and TESTMD1 are logic low U. the previous state is maintained.

The memory control signal controller 25 receives the memory control signal PC applied through the pad 8, and is controlled by the main control signals MEMTEST1, MEN[TEST2 and NORMAL to transmit the memory control signal PC to the first and second memories 17 and 19 of FIG. 1 and the logic circuit 15 of FIG. 1. The memory controi signal PC includes a row address strobe signal RASB, a column address strobe signal CASB, a writing is enable signal WEB, an output enable signal OEB. and an address signal Ai.

The memory data controller 1-7 receives the memory data signal DQi applied through the pad 7. and is controlled by the main MENITESTI. MENITEST2 and NORMAL to transmit the memory data signal DQi input externally to the first and second memories 17 and 19 of FIG. 1 or the logic circuit 15 of FIG. 1 and the memory data signal DQi generated from the first and second memories 17 and 19 of FIG. 1 or the logic circuit 15 of FIG. 1 to the pad 7.

9 As described above, the memory test control circuit 13 according to the first embodiment of the present invention may test the first and second memories 17 and 19 of FIG. 1 using the conventional pads 7 and 8 of FIG. 1 without the logic circuit 15.

FIG. 3 is a circuit diagram of a memory circuit signal controller 25 of FIG. 2. Referring to FIG. 3. the memory control signal controller 25 includes a buffer 3 1. a logic gate 33 and a memory controller 35.

The buffer 31 receives a memory control signal PC. and transmits the output to the logic gate 33. The buffer 31 changes the voltage level of the memory control signal PC. For C example, a voltage of a transistor transistor logic (TTL) level is converted into a voltage of a complementary metal oxide semiconductor (CMOS) level.

The logic gate 33 receives an output of the buffer 31. and transmits the output to the is memory controller 35. The logic gate 33 includes first through three AND gates 33a, 33b and 33c.

The first AND aate 33a receives the output of the buffer 31 and the main control signal c MEN[TEST1. When the output of the buffer 31 or the main control signal MENITEST1 is logic low. the first AND gate 33a generates a logic low signal. and when the output of the buffer 31 and the main control signal MENITEST1 are logic high, the first AND gate 33a generates a logic high signal.

The second AND gate 33b receives the output of the buffer 31 and the main control signal NORMAL and transmits the output to the logic circuit 15 of FIG. 1. When the output of the buffer 31 or the main control signal NORMAL is logic low. the second AND gate 33b generates a logic low signal. and when the output of the buffer 31 and the main control signal NORMAL are logic high. the second AND gate 33b generates a logic high signal.

The third AND gate 33c receives the output of the buffer 31 and the main control signal MEMTIEST2. When the output of the buffer 31 or the main control signal MEN[TEST2 is logic low, the third AND gate 33b generates a logic low signal, and when the output of the buffer 31 and the main control signal MENITEST2 are logic low. the third AND gate 33c generates a 16 ic high signal.

c 9 The memory controller 35 includes first and second multiplexers 35a and 35b.

is A 2-input. 1-output multiplexer is used as the first multiplexer 35a. The first multiplexer 35a receives the output of the first AND gate 33a and the output of the logic circuit 15 of FIG. 1. and is controlled by the main control signals NORMAL and MEIVITEST1, to transmit the output of the first AND gate 33a and the output of the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1. That is, when the main control signal NORMAL is 20 active. the first multiplexer 35a transmits signals generated from the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1, and when the main control signal MEIVITEST1 is active, the first multiplexer 35a transmits the signals generated from the first AND gate 33a to the first memory 17 of FIG. 1 11 A 2-input, 1-output multiplexer is used as the second multiplexer 35b. The second multiplexer 35b receives the output of the third AND gate 33c and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and MEWEST2, to transmit the output of the third AND gate 33c and the output of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1. That is, when the main control signal NORMAL is active. the second multiplexer 35b transmits the signals generated from the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1, and when the main control signal MEWEST2 is active, the second multiplexer 35b transmits the signal generated from the third AND gate 33c to the second memory 19 of FIG. 1.

FIG. 4 is a circuit diagram of the memory data controller 27 of FIG. 2. Referring to FIG. 4. the memory data controller 27 includes an input/output buffer 41, a logic gate 43, a memory controller 45, an output controller 47 and an output buffer controller 49.

is The inputloutput buffer 41 includes an input buffer 41a and an output buffer 41b.

The input buffer 41a receives the memory data signal DQi, and transmits the output to the logic gate 43. The input buffer 41a changes the voltage level of the memory data signal DQ. For example, a voltage of a TTL level is converted to a voltage of a CMOS level.

The output buffer 41b is controlled by the output buffer controller 49 to transmit the output of the output controller 47 externally. That is, when output of the output buffer controller 49 is active. the output buffer 41b is activated to transmit the output of the output controller 12 47 externally, and when the output of the output buffer controller 49 is inactive. the output buffer 41b is inactive to prevent transmission of the output of the output controller 47 externally.

The logic gate 43 receives the output of the input buffer 41a and signals MEMTIESTI, NORMAL and MEWEST2. and transmits the output to the memory controller 45. The logic gate 43 includes first through third AND gates 43a, 43b and 43c.

The first AND gate 43a receives the output of the input buffer 41a and the main control A signal MEWEST1, and transmits the output to the memory controller 45. When the output of the input buffer 41a or the main control signal MEMTIEST1 is logic low. the first AND gate 43a generates a logic low signal. and when the output of the input buffer 41a and the main control signal MEMTIEST1 are logic high, the first AND gate 43a generates a logic high signal.

is The second AND gate 43b receives the output of the input buffer 41a and the main control signal NORMAL, and transmits the output to the logic circuit 15 of FIG. 1. When the output of the input buffer 41a or the main control signal NORMAL is logic low. the second AND gate 43b generates signals of logic low, and when the output of the input buffer 41a and the main control signal NORMAL are logic high. the second AND gate 43b generates a logic high signal.

The third AND gate 43c receives the output of the input buffer 41a and the main control 13 signal MEMTIEST2, and transmits the output to the memory controller 45. When the output of the input buffer 41a or the main control signal MENITEST2 is logic 1 ow, the third AND gate 43c generates a logic low signal. and when the output of the input buffer 41a and the main control signal MEMTIEST2 are logic high, the third AND gate 43c generates a logic high signal.

The memory controller 45 includes first and second multiplexers 45a and 45b.

A 22-input. 1-output multiplexer is used as the first multiplexer 45a. The first multiplexer 45a receives the output of the first AND gate 43a and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and MEMTIESTI, to transmit the output of the first AND gate 43a and the output of the logic circuit 15 of FIG.

1 to the first memory 17 of FIG. 1. That is. when the main control signal NORMAL is active. the first multiplexer 45a transmits signals generated from the logic circuit 15 of FIG.

is 1 to the first memory 17 of FIG. 1. and when the main control signal MEN[TEST1 is active, the first multiplexer 45a transmits signals generated from the first AND gate 43a to the first memory 17 of FIG. 1.

A 2-input, 1-output multiplexer is used as the second multiplexer 45b. The second multiplexer 45b receives the output of the third AND gate 43c and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and MENITEST2, to transmit the output of the third AND gate 43c and the output of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1. That is, when the main control 14 signal NORMAL is active, the second multiplexer 45b transmits signals generated from the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1. and when the main control signal MEMTIEST2 is active, the second multiplexer 45b transmits signals generated from the third AND gate 43c to the second memory 19 of FIG. 1.

The output controller 47 receives signals generated from the logic circuit 15 of FIG. 1 and the first and second memories 17 and 19 of FIG., 1. and transmits the output to the output buffer 4 lb. A 3-input, 1-output multiplexer is used as the output controller 47. The output controller 47 is controlled bv the main control signals NORMAL. MEMTESTI and MEMTIEST2. That is, when the main control signal NORMAL is active, the output controller 47 transmits signals generated from the logic circuit 15 of FIG. 1 to the output buffer 41b, when the main control signal MEWEST1 is active. the output controller 47 transmits signals from the first memory 17 of FIG. 1 to the output buffer 41b. and when the main control signal MEMTIEST2 is active. the output controller 47 transmits signals is generated from the second memory 19 of FIG. 1 to the output buffer 41b.

The output buffer controller 49 includes first through third logic gates 49a. 49b and 49d. a fourth AND gate 49c and a NAND gate 49e.

The first logic gate 49a receives the main control signals MEMTIEST1 and MEWEST2. When one of the main control signals MEMTEST1 and.MEMTEST2 is logic high, the first logic gate 49a generates a logic high signal, and when all of the main control signals MEMTEST1 and MEWEST2 are logic low, the first logic gate 49a generates a logic low is signal.

The second logic gate 49b receives a first output buffer enable signal TRST I generated from the first memory 17 of FIG. 1 and a second output buffer enable signal TRST2 generated from the second memory 19 of FIG. 1. When the first output buffer enable signal TRST1 or the second output buffer enable signal TRST2 is logic high, the second logic gate 49b generates a logic high signal. and when both the first output buffer enable signal TRST1 and the second output buffer enable signal TRST2 are logic low, the second logic gate 49b generates a logic low signal.

The fourth AND gate 49c receives the output of the first logic gate 49a and the output of the second Logic gate 49b. When the output of the first Logic gate 49a or the output of the second logic gate 49b is logic low. the fourth AND gate generates a logic low signal, and both the output of the first Logic gate 49a and the output of the second Logic gate 49b are is logic high, the fourth AND gate generates a logic high signal.

The third Logic gate 49d receives the output of the fourth AND gate 49c and the main control signal NORMAL. When the output of the fourth AND gate 49c or the main control signal is logic high, the third Logic gate 49d generates a logic high signal. and both the output of the fourth AND gate 49c and the main control signal are logic low. the third Logic gate 49d generates a logic low signal.

C The NAND gate 49e receives the output of the third Logic gate 49d and a power supply 16 voltage WC. and transmits the output to a control terminal of the output buffer 41b. The NAND gate 49e transmits the output of the third Logic gate 49d to the control terminal of the output buffer 41b. That is. when the output of the third Logic gate 49d is logic high, the NAND gate 49e generates a logic low signal. and when the output of the third Logic gate 49d is logic low, the NAND gate 49e generates a logic high signal. When the output of the NAND gate 49e is logic low, i.e., active. the output buffer 41b is activated, and when the output of the NAND gate 49e is logic high, i.e.. inactive, the output buffer 41b is deactivated.

FIG. 5 is a block diagram of a second embodiment of the memory test control circuit of FIG. 1. Referring to FIG. 5. the memory test control circuit 213 according to the second embodiment includes a main control signal generator 5 1. a memory control signal controller 53. a first memory data controller 55 and a second memory data controller 57.

is The main control signal generator 51 receives a test control signal TESTNID0 applied through the pad 9, and transmits the output to the memory control signal controller 53, the first memory data controller 55 and the second memory data controller 57. The main control signal generator 51 generates main control signals, i.e.. a memory main control signal MEN[TEST and a logic main control signal NORMAL, in response to the test control signal TESTMDO. For example. the main control signal generator 51 has truth values as shown in Table 2.

17 (Table 2)

Function TESTMDO Main control signal First and second memory L5 MEWEST test Normal operation 7HT NORMAL As shown in Table 2. when the test control signal TESTMDO is logic low, the memory main control signal MEWEST is active, to test the first and second memories 17 and 19 of FIG. 1. and when the test control signal TESTMDO is logic high U, the logic main control signal NORMAL is activated. to normally operate the logic circuit 15 of FIG.

The memory control signal controller 53 receives a memory control signal PC applied through the pad 8, and is controlled by the main control signals MEMTEST and NORMAL, to transmit the memory control signal PC to the first and second memories 17 and 19 of FIG. 1 or the logic circuit 15 of FIG. 1. The memory control signal PC includes a row address strobe signal RAS13. a column address strobe signal CASB, a write enable signal WEB, an output enable signal OEB and an address signal Ai.

The first memory data controller 55 receives memory data signals DQ 1 i applied through the pad 7. and is controlled by the main control signals MEWEST and normal to transmit the memory data signal DQli to the first memory 17 of FIG. 1 or the logic circuit 15 of FIG.

1, and the memory data signal DQli generated from the first memory 17 of FIG. 1 or the logic circuit 15 of FIG. 1 to outside the pad 7.

The second memory data controller 57 receives a memory data signal DQ2iapplied through 18 the pad 7'. and is controlled by the main control signals MEMTIEST and NORMAL, to transmit the memory data signal DQ2i to the second memory 19 of FIG. 1 or the logic circuit 15 of FIG. 1, and the memory data signal DQ2i generated from the second memory 19 of FIG. 1 or the logic circuit 15 of FIG. 1 to the pad 7' As described above, the memory test control circuit 213 according to the second embodiment of the present invention can test the first and second memories 17 and 19 of FIG. 1 using conventional pads 7. 8 and 7' without the logic circuit 15 of FIG. 1.

FIG. 6 is a circuit diagram of the memory control signal controller 53 of FIG. 5. Referring to FIG. 6. the memory control signal controller 53 includes a buffer 61, a logic gate 63 and a memory controller 65.

The buffer 61 receives a memorv control signal PC. and transmits the output to the logic aate 63. The buffer 61 changes the voltage level of the memory control signal PC. For 0 example, a voltage of a TTL level is converted to a voltage of a CMOS level.

The logic gate 63 receives the output of the buffer 61, and transmits the output to the memory controller 65. The logic gate 63 includes first through third AND gates 63a, 63b and 63c.

The first AND gate 63a receives the output of the buffer 61 and the memory main control signal MEMTIEST. When the output of the buffer 61 or the memory main control signal MEMTIEST is logic low, the first AND gate 63a generates a logic low signal. and when the 19 output of the buffer 61 and the memory main control signal MENITEST are logic high, the first AND gate 63a generates a logic high signal.

The second AND gate 63b receives the output of the buffer 61 and the logic main control signal NORMAL and transmits the output to the logic circuit 15 of FIG. 1. When the output of the buffer 61 or the logic main control signal NORMAL is logic low, the second AND gate 63b generates a logic low signal, and when the output of the buffer 61 and the logic main control signal NORMAL are logic high, the second AND gate 63b generates a logic high signal.

The third AND gate 63c receives the output of the buffer 61 and the memory main control signal MEMTIEST. When the output of the buffer 61 or the memory main control signal MEMTIEST are logic high. the third AND gate 63c generates a logic high signal.

The memory controller 65 includes first and second multiplexers 65a and 65b.

A 2-input. 1-output multiplexer is used as the first multiplexer 65a. The first multiplexer 65a receives the output of the first AND gate 63a and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and MENITEST to transmit the output of the first AND gate 63a and the output of the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1. That is, when the logic main control signal NORMAL is active. the first multiplexer 65a transmits the signal generated from the logic circuit 15 of FIG. 1 to the first memory 17 of FIG. 1, and when the memory main control signal MENITEST is active. the first multiplexer 65a transmits the signal generated from the first AND gate 63a to the first memory 17 of FIG. 1.

A 2-input. 1-output multiplexer is used as the second multiplexer 65b. The second multiplexer 65b receives the output of the third AND gate 63c and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST, to transmit the output of the third AND gate 63c and the output of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1. That is, when the logic main control signal NORMAL is active. the second multiplexer 65b transmits a signal generated from the logic to the second memory 19 of FIG. 1. and when the memory main control signal MEWEST is active. the second multiplexer 65b transmits the signal generated from the third AND gate 63c to the second memory 19 of FIG. 1.

FIG. 7 is a circuit diagram of the first memory data controller 55 of FIG. 5. Referring to is FIG. 7, the first memory data controller 55 includes a first input/output buffer 71, a first logic gate 73. a first memory controller 75. a first output controller 77 and a first output buffer controller 79.

The first input/output buffer 71 includes the first input buffer 71a and the first output buffer 71b.

The first input buffer 71a receives the memory data signal DQ1i and transmits the output to the first logic gate 73. The first input buffer 71a changes the voltage level of the memory 21 data signal DQU. For example, a voltage of the 17L level is converted to a voltage of the CMOS level.

The first output buffer 71b is controlled by the first output buffer controller 79 to transmit the output of the first output controller 77 externally. That is, when the output of the first output buffer controller 77 is active. the first output buffer 71b is activated to transmit the output of the first output controller 77 externally, and when the output of the first output buffer controller 79 is inactive, the first output buffer 71b is inactive to transmit the output of the first output controller 77 externally.

The first logic gate 73 receives the output of the first input buffer 71a and transmits the output to the first memory controller 75. The first logic gate 73 includes first and second AND gates 73a and 73c.

is The first AND gate 73a receives the output of the first input buffer 71a and the memory main control signal ME1ATEST. When the output of the first input buffer 71a or the memory main control signal MEMTIEST is logic low. the first AND gate 73a generates a logic low signal. and when the output of the first input buffer 71a and the memory main control signal MEMTIEST are logic high. the first AND gate 73a generates a logic high 20 signal.

The second AND gate 73c receives the output of the first input buffer 71a and the main control signal NORMAL and transmits the output to the logic circuit 15 of FIG. 1. When 22 the output of the first input buffer 71a or the main control signal NORMAL is logic low, the second AND gate 73c generates a logic low signal, and when the output of the first input buffer 71a and the main control signal NORMAL are logic high, the second AND gate 73c generates a logic high signal.

is The first memory controller 75 includes a 2-input, 1-output multiplexer. The first memory controller 75 receives the output of the first AND gate 73a and the output of the logic circuit of FIG. 1, and is controlled by the main control signals NORMAL and MEN[TEST to transmit the output of the first AND gate 73a and the output of the logic circuit 15 of FIG.

1 to the first memory 17 of FIG. 1. That is, when the logic main control signal NORMAL is active, the first memory controller 75 transmits signals generated from the logic circuit of FIG. 1 to the first memory 17 of FIG. 1, and when the memory main control signal MEN[TEST is active, the first memory controller 75 transmits signals generated from the first AND gate 73a to the first memory 17 of FIG. 1.

The first output controller 77 includes a 2-input, 1-output multiplexer. The second output controller 77 receives signals generated from the logic circuit 15 of FIG. 1 and the first memory 17 of FIG. 1, and transmits the output to the first output buffer 71b. The second output controller 77 is controlled by the main control signals NORMAL and MEN[TEST.

That is, when the logic main control signal NORMAL is active, the first output controller 77 transmits signals generated from the logic circuit 15 of FIG. 1 to the first output buffer 71b, and when the memory main control signal MEWEST is active, the first output controller 77 transmits signals generated from the first memory 17 of FIG. 1 to the first 23 output buffer 71b.

The first output buffer controller 79 includes a third AND gate 79a, a first logic gate 79c and a first NAND gate 79d.

The third AND gate 79a receives the memory main control signal MEWEST and the first output buffer enable signal TRST1. When the memory main control signal MEN[TEST or the first output buffer enable signal TRSTI is logic low, the third AND gate 79a generates a logic low signal, and when both the memory main control signal MEN[TEST and the first output buffer enable signal TRST1 are logic high, the third AND gate 79a generates a logic high signal.

The first logic gate 79e receives output of the third AND gate 79a and the main control signal NORMAL. When output of the third AND gate 79a or the logic main control signal is NORMAL is logic high, the first logic gate 79c generates a logic high signal. and when the output of the third AND gate 79a and the main control signal NORMAL are logic low, the first logic gate 79a generates a logic low signal.

The first NAND gate 79d receives the output of the first logic gate 79a and a power supply voltage VCC and transmits the output to a control terminal of the first output buffer 71b.

The first NAND gate 79d transmits the output of the first logic gate to the control terminal of the first output buffer 71b. That is. when output of the first logic gate 79c is logic low, the first NAND gate 79d generates signals of logic high, and when the output of the first 24 logic gate 79c is logic high, the first NAND gate 79d generates signals of logic low. When the output of the first NAND gate 79d is logic low, i. e., active, the first output buffer 71d is activated, and when the output of the NAND gate 79d is logic high, i.e., inactive, the first output buffer 71b is inactive.

FIG. 8 is a circuit diagram of the second memory data controller 57 of FIG. 5. Referring to FIG. 8, the second memory data controller 57 includes a second input/output buffer 81, a second logic gate 83, a second memory controller 85. a second output controller 87 and a second output buffer controller 89.

The second inputloutput buffer 81 includes a second input buffer 81a and a second output buffer 81b.

The second input buffer 81a receives the memory data signal DQ2i and transmits the output to the second logic gate 83. The second input buffer 81a changes the voltage level of the memory data signal DQ1i. For example, a voltage of the TTL level is converted to a voltage of the CMOS level.

The second output buffer 81b is controlled by the second buffer controller 89 and transmits the output of the second output controller 87 externally. That is, when the output of the second output buffer controller 89 is active, the second output buffer 81b transmits the output of the second output controller 87 externally, and when the output of the second output buffer controller 89 is inactive, the second output buffer 8 1 b is inactive, and thus the output of the second output controller 87 is not transmitted externally.

The second logic gate 83 receives the output of the second input buffer 81a and transmits the output to the second memory controller 85. The second logic gate 83 includes fourth and fifth AND gates 83a and 83c.

The fourth AND gate 83a receives the output of the second input buffer 8 1 a and the memory main control signal MEWEST. When the output of the second input buffer 81a or the memory main control signal MEWEST is logic low. the fourth AND gate 83a generates a logic low signal. and when the output of the second input buffer 81a and the memory main control signal MEWEST are logic high, the fourth AND gate 83a generates a logic high signal.

The fifth AND gate 83c receives the output of the second input buffer 81a and the main control signal NORMAL and transmits the output to the logic circuit 15 of FIG. 1. When the output of the second input buffer 81a or the main control signal is logic low, the fifth AND gate 83c generates a logic low signal. and when the output of the second input buffer 81a and the main control signal NORMAL are logic high, the fifth AND gate 83c generates a logic high signal.

The second memory controller 85 includes a 2-input. 1-output multiplexer. The second memory controller 85 receives the output of the fourth AND gate 83a and the output of the logic circuit 15 of FIG. 1, and is controlled by the main control signals NORMAL and 26 MEMTEST to transmit the output of the fourth AND gate 83a or the output of the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1. That is, when the logic main control signal NORMAL is active. the second memory controller 85 transmits signals generated from the logic circuit 15 of FIG. 1 to the second memory 19 of FIG. 1, and when the memory main control signal MEWEST is active, the second memory controller 85 transmits signals generated from the fourth AND gate 83a to the second memory 19 of FIG. 1.

The second output controller 87 includes a 2-input, 1 -output multiplexer. The second output controller 87 receives signals generated from the logic circuit 15 of FIG. 1 and the second memory 19 of FIG. 1, and transmits the output to the second output buffer 8 lb. The second output controller 87 is controlled by the main control signals NORMAI and MEWEST. That is, when the logic main control signal NORMAL is active. the second output controller 87 transmits signals generated from the logic circuit 15 of FIG. 1 to the second output buffer 81b. and when the memory main control signal MEMTEST is active, the second output controller 87 transmits signals generated from the second memory 19 of FIG. 1 to the second output buffer 81b. The second output buffer controller 89 includes a sixth AND gate 89a, a second logic gate 89c and a second NAND gate 89d.

The sixth AND gate 89a receives the memory main control signal ME1ATEST and the output buffer enable signal TRST1 generated from the second memory 19 of FIG. 1. When the main control signal MEWEST or the output buffer enable signal TRST2 is logic low, 27 the sixth AND gate 89a generates a logic low signal, and when both the main control signal MEMTIEST and the output buffer enable signal TRST1 are logic high. the sixth AND gate 89a generates a logic high signal.

0 The second logic gate 89c receives the output of the sixth AND gate 89a and the main control signal NORMAL. When the output of the sixth AND gate 89a or the main control signal NORMAL is logic high. the second logic gate 89c generates a logic high signal, and when both the output of the sixth AND gate 89a and the main control signal NORMAL are logic low. the second logic gate 89c generates a logic low signal.

The second NAND gate 89d receives the output of the second logic gate 89c and a power supply voltage VCC and transmits the output to a control terminal of the second output buffer 8 lb. The second NAND gate 89d transmits the output of the second logic gate to the control terminal of the second output buffer 81b. That is, when the output of the second is logic gate 89c is logic low, the second NAND gate 89d generates signals of logic high, and when the output of the second logic gate 89c is logic high, the second NAND gate 89d generates a logic low signal. When the output of the second NAND gate 89d is logic low, i.e.. active, the second output buffer 81b is activated, and when the output of the NAND gate 89d is logic high, i.e., inactive, the second output buffer 81b is inactive.

FIG. 9 shows a merged memory logic semiconductor device according to a second embodiment of the present invention. Referring to FIG. 9, the merged memory logic semiconductor device 107 includes first through sixth pads Ill, 112, 113, 114, 115 and 28 1 116. a first built-in self-tester 121, a second built-in self-tester 123. a first memory 125, a second memory 127 and a logic circuit 129.

External signals are input into the merged memory logic semiconductor device 107 through the first through fourth pads 111. 112. 113 and 114. and signals of the merged memory logic semiconductor device are output externally through the fifth and sixth pads 115 and 116.

In detail, external first and second clock signals Clock-A and Clock-B are input into the merged memory logic semiconductor device 107 through the first and second pads 111 and 112. and external first and second test enable signals EnableA and Enable- B are input into the merged memory logic semiconductor device 107 through the third and fourth pads 113 and 114. Also, first and second test result signals Error-A and Error-B of the merged memory logic semiconductor device 107 are output externally through the fifth and sixth pads 115 and 116.

The first built-in self-tester 121 receives the first clock signal ClockA and the first test enable signal Enable-A, and generates first control signals 131, i.e., a row address strobe signal RASB, a column address enable signal CASB, an address signal Addr. a write enable signal WEB and an input data signal Datain to apply to the first memory 125. A first output data signal Dataout-A is received from the first memory 125 to output the first test result signal Error-A to the fifth pad 115.

29 The second built-in self-tester 123 receives the second clock signal Clock-B and a second test enable signal Enable-B, generates second control signals 133, i.e.. a row address strobe signal RASB, a column address enable signal CASB. an address signal Addr, a writing enable signal WEB and an input data signal Data-in to apply to the second memory 127. A second output data signal Dataout-B is received from the second memory 127 and thus a second test result signal Error_B is output to the sixth pad 116.

The first and second memories 125 and 127 for storing data, include input terminals connected to the first and second built-in self-testers 121 and 123, respectively, and output terminals connected to the first and second built-in self-testers 121 and 123. respectively.

The first memory 125 generates first output data signals DataotitA, responding to the first control signals 131, and the second memory 127 generates second output data signals DataoutB, responding to the second control signal 133.

is The logic circuit 129 controls the first and second memories 125 and 127.

FIG. 12 is a timing diagram of signals for testing a merged memory logic semiconductor device according to second through fourth embodiments of the present invention. Referring to FIG. 12, first clock signal Clock-A or second clock signal Clock-B and first test enable signal Enable-A or second test enable signal Enable-B are generated, and then first and second control signals 131 and 133 are generated. After a predetermined time TI, first or second output data signal dataout-A or dataout-B is generated. Then, after a predetermined time. first or second test result signal Testout-A or Testout-B is generated.

1 The operation of the merged memory logic semiconductor device 7 of FIG. 9 according to the second embodiment of the present invention will be described with reference to FIG. 12. Here, the operation of testing a first memory 125 through the first built-in self-tester 121 is equivalent to that of testing a second memory 127 through the second built-in selftest unit 123. Accordingly, the operation of testing the first memory 125 through the first builtin self-tester 121 will be described.

When the first test enable signal Enable-A is enabled, i.e., logic high, the first built-in self tester 121 is activated. In this state, when the first clock signal Clock_A is enabled to logic high. a first control signal 131 is generated from the first built-in self-tester 121 to apply to the first memory 125. Then. the first memory 125 generates the first output data signal Dataout-A after a predetermined time T1 as shown in FIG. 12, in response to the first control signal 131 to apply to the first built-in self-tester 121. The predetermined time T1 of FIG. 12 is a period for activating and operating the first memory 125 as soon as the first is control signals 131 are input. and outputting the result as the first output data signal Dataout-A. The first built-in self-tester 121 analyzes the first output data signal Dataout-A and generates the result as the first test result signal Error-A to transmit to the fifth pad 115. The first built-in self-tester 121 requires a time T2 as shown in FIG. 12 to analyze the first output data Daaout-A and outputting the first test result signal Error-A. The first test result signal Error-A determines whether the function of the first memory 125 is normal or not.

When the number of memories increases in the semiconductor device 107 of FIG. 9, the 31 number of built-in self-testers. clock signals and test enable signals increases to be equal to that of the memories.

When the first and second test enable signals Enable-A and Enable-B are simultaneously enabled. the first and second memories 125 and 127 are simultaneously tested. Accordingly. the period for testing the first and second memories 125 and 127 is equal to that for testing one memory. Also, conventional pads are used in common without the first through sixth pads 111, 112 113, 114, 115 and 116. to reduce the number of pads and manufacturing cost.

is FIG. 10 shows a merged memory logic semiconductor device 207 according to a third embodiment of the present invention. The merged memory logic semiconductor device 207 includes first through fifth pads 211. 213, 214, 215 and 216. first and second built-in selftesters 221 and 223, first and second memories 225 and 227. and a logic circuit 229.

External signals are input to the merged memory logic semiconductor device 207 through the first to third pads 211. 213 and 214, and signals of the merged memory logic semiconductor device 207 are output externally through the fourth and fifth pads 215 and 216.

In detail, an external clock signal Clock is input to the merged memory logic semiconductor device 207 through the first pad 211, and external first and second test enable signals Enable-A and Enable-B are input to the merged memory logic semiconductor device 207 32 through the second and third pads 213 and 214. Also. the first and second test result signals Error-A and Error-B of the merged memory logic semiconductor device 207 are output externally through the fourth and fifth pads 215 and 216.

The first built-in self-tester 221 receives the clock signal Clock and the first test enable signal Enable-A and generates a first control signals 231, i.e., a row address strobe signal RASB, a column address enable signal CASB, an address signal Adds, a write enable signal WEB and an input data signal Datain to apply to the first memory 225. Also, the first output data signal Dataout-A is received from the first memory 225 to output the first test result signal Error-A to the fourth pad 215.

The second built-in self-tester 223 receives the clock signal Clock and the second test enable signal Enable-B. and generates second control signals, i.e., a row address strobe signal RASB, a column address enable signal CASB. an address signal Addr, a write enable signal is WEB and an input data signal Data-in to apply to the second memory 227. The second output data signal Dataout-B is received from the second memory 227 to output the second test result signal Error-B to the fifth pad 216.

The first and second memories 225 and 227 for storing data include input terminals connected to the first and second built-in self-testers 221 and 223, respectively, and output terminals connected to the first and second built-in self-testers 221 and 223, respectively.

The first memory 225 generates the first output data signal Dataout-A, responding to the first control signals 23 1, and generates the second output data signal Dataout-B, in response 33 to the second control signals 233.

The logic circuit 229 controls the first and second memories 225 and 227.

The operation of the merged memory logic semiconductor device 207 of FIG. 10 according to the third embodiment of the present invention will be described with reference to FIG.

12. In the merged memory logic semiconductor device 207 of FIG. 10, operation of testing the first memory 225 through the first built-in self-tester 221 is equivalent to that of testing the second memory 227 through the second built-in self-tester 223. Here. the operation of testing the first memory 225 through the first built-in self-tester 221 will be described.

When the first test enable signal Enable-A is enabled, i.e., logic high, the first built-in self tester 221 is activated. In this state, when the clock signal Clock is enabled to logic high, the first control signals 231 are generated from the first built-in self- tester 221 to apply to is the first memory 225. Then. the first memory 225 generates the first output data signal Dataout-A after a predetermined time T1 of FIG. 12, in response to the first control signals 231 to apply to the first built-in self-tester 221. The predetermined time TI of FIG. 12 is a period for activating and operating the first memory 225 as soon as the first control signals 231 are input, and outputting the result as the first output data signal Dataout-A. The first built-in self-tester 221 analyzes the first output data signal Dataout-A and generates the result as the first test result signal ErrorA to transmit to the fourth pad 215. The period for generating the first test result signal Error-A after generating the output data signal Dataout-A is T2 of FIG. 12. The first test result signal Error-A determines whether the 34 function of the first memory 225 is normal or not.

When the number of memories increases in the semiconductor device 207 of FIG. 10, the number of built-in self-testers and the test enable signals increases to be equal to that of the memories. However, one clock signal is used in common.

When the first and second test enable signals Enable-A and Enable-B are simultaneously enabled, the first and second memories 225 and 227 are simultaneously tested. Accordingly, in the case that the first and second test enable signals Enable-A and Enable-B are simultaneously enabled, the period for testing the first and second memories 225 and 227 is equal to that for testing one memory, which reduces the test time. Also. conventional pads are used in common without addition of the first through fifth pads 211, 213, 214, 215 and 216, to thereby reduce the number of pads and the fabricating cost.

FIG. 11 shows a merged memory logic semiconductor device 307 according to a fourth embodiment of the present invention. The merged memory logic semiconductor device 307 includes first through fifth pads 311. 313, 314, 315 and 316, a built-in self-tester 321, first and second memories 325 and 327 and a logic circuit 329.

External signals are input to the merged memory logic semiconductor device 307 through the first through third pads 311, 313 and 314 and signals of the merged memory logic semiconductor device 307 are output externally through the fourth and fifth pads 315 and 316.

In detail, external clock signal Clock is input to the merged memory logic semiconductor device 307 through the first pad 211. and external first and second test enable signals Enable-A and Enable-B are input to the merged memory logic semiconductor device 307 through the second and third pads 313 and 314. Also. the first and second test result signals Error-A and Error-B of the merged memory logic semiconductor device 307 are output externally through the fourth and fifth pads 315 and 316.

The built-in self-tester 321 receives the clock signal Clock. and the first and second test enable signals Enable-A and Enable-13, and generates first and second control signals 331 and 333. Le., a row address strobe signal RASB, a column address enable signal CASB, an address signal Addr. a writing enable signal WEB and an input data signal Datain to apply to the first and second memories 325 and 327. The first output data signal Dataout-A and Dataout-B are received from the first and second memories 325 and 327 to output first and second test result signals Error_A and Error-B to the fourth and fifth pads 315 and 316.

is The second control signals 333 may commonly use the first control signal 331.

The first and second memories 325 and 327 for storing data include input terminals in common connected to the built-in self-tester 32 1, and output terminals connected in common to the built-in self-tester 321. The firstmemory 325 generates the first output data signal Dataout-A, in response to the control signals 331, and the second memory 327 generates the second output data Dataout-B, in response to the second control signals 333.

36 The logic circuit 329 controls the first and second memories 325 and 327.

The operation of the merged memory logic semiconductor device 307 according to the fourth embodiment of the present invention of FIG. 11 will be described with reference to FIG. 12.

When the first test enable signal Enable-A is enabled, i.e., logic high, the built-in self-tester 321 is activated. In this state, when the clock signal Clock is enabled to logic high, the 1First control signals 331 are generated from the built-in self-tester 321 to apply to the first memory 325. Then, the first memory 325 generates the first output data Dataout-A after a predetermined time T1 of FIG. 12, in response to the first control signals 331 to apply to the built-in self-tester 321. The predetermined time T1 of FIG. 12 is a period for activating and operating the first memory 325 as soon as the first control signals 331 are input, and outputting the result as the first output data signal Dataout-A. The built-in self-tester 321 is analyzes the first output data signal DataotitA and generates the result as the first test result signal Error-A to transmit to the fourth pad 315. T2 of FIG. 12 is required for generating the first test result signal Error-A after generating the output data signal Dataout-A. The first test result signal ErrorA determines whether the function of the first memory 325 is normal or not.

The operation of testing the function of the second memory 327 is equivalent to that of testing the first memory 325. Here, the clock signal Clock and the built-in self-tester 321 are used in common for the operation of testing the function of the second memory 327.

37 Accordingly, when the first and second test enable signals Enable-A and Enable-B are simultaneously enabled. the first and second memories 325 and 327 are simultaneously tested. Therefore, the period of testing the first and second memories 325 and 327 is equal to that of testing one memory, which reduces the testing time. Also, conventional pads are used in common without the addition of first through fifth pads 311, 313, 314. 315 and 316, to thereby reduce the number of pads and the fabricating cost.

When the number of the memories increases in the semiconductor device of FIG. 11, the number of test enable signals increases to match the number of the memories. However, one built-in self-tester and one clock signal are used in common.

FIG. 13 is a flowchart of a test method of a merged memory logic semiconductor device according to the present invention. Referring to FIG. 13, the test method of a memory of the merged memory logic semiconductor device 407 includes the steps of activating a first memory (401). activating a second memory (411), reading data from the first memory (421), reading data from the second memory (43 1), writing data in the first memory (44 1), writing data in the second memory (451), re-reading data from the first memory (461), re-reading out data from the second memory (47 1), precharging the first memory (48 1) and precharging the second memory (491).

In the step of activating the first memory (401), the built-in selftester 321 is activated by external signals, and the built-in self-tester 321 activates the first memory 425.

In the step of activating the second memory (411), the built-in selftester 321 activates the 38 1 second memory 427.

in the step of reading data from the first memory (421), the built-in self-tester 321 reads data stored in the first memory 425.

In the step of reading data from the second memory (431), the built-in self-tester 321 reads data stored in the second memory 427.

In the step of writing data in the first memory (441), the built-in selftester 321 writes data of '1' or '0' in the first memory 425.

In the step of writing data in the second memory (451), the built-in selftester 321 writes data of 'I' or '0' in the second memory 427.

is In the step of re-reading data from the first memory (461), the builtin self-tester 321 reads data written in the first memory 425. Reference data during normal first memory 425, is stored in the built-in self-tester 321. Accordingly, in the built-in self-tester 321, the data read from the first memory 425 is compared to the reference data. and if the read data is different from the reference data, an error signal is generated and n=mitted externally.

In the step of re-reading out data from the second memory (471), the built-in self-tester 321 reads data written in the second memory 427. In the built-in self-tester 321, the data read from the second memory 427 is compared to the reference data, and if the read data is 39 different from the reference data, an error signal is generated and transmitted externally.

In the step of precharging the first memory (481), which is a pre-step for writing data in the first memory 425 or reading data stored in the first memory 425, the first memory 425 is precharged.

In the step of precharging the second memory 427 (49 1), which is a prestep for writing data in the second memory 427 or reading data stored in the second memory 427, the second memory 427 is precharged.

By the test method of the present invention, test on the first and second memories 425 and 427 is performed in an interleave method. When the first and second memories 425 and 427 are 16M synchronous memories, a test cycle of the first and second memories 425 and 427 using 14N Y-March algorithm is expressed by a following formula 1. Here. it is assumed that a data bus transmits 64bit. (Formula 1) Test cycle = data format x stage x 128K 2 x 6 x 128K 1,572,864 (cycle time) 11 clocks of Table 3 are required for simultaneously performing each stage with respect to the first and second memories 425 and 427 in an interleave method.

is (Table 3)

1 2 3 4 5 6 7 8 9 10 11 1st active stand-by stand-by stand-by rmd stand-by V starid-by re- pre- stand-by memory block 2nd stand-by stand-by active staM-by stand-by read stand-by read stand-by pre c memory block input I st data 2nd data input input data output 1 st data 2nd dm 0 Output data is Accordingly, the total test time on the first and second memories 425 and 427 is expressed by the following Formula 2.

(Formula 2) Test time = 1,572,864 x 11 = 325.301,504(cycle time) Me test time of Formula 2 according to the present invention is approximately 55 % of the conventional test time. That is, the memory test time according to the present invention is reduced to approximately 45 % of the conventional memory test time.

4 The interleave method of the present invention may be applied to a merged memory logic semiconductor device having three or more memories. to thereby greatly reduce the memory test time.

In the present invention, an internal memory can be tested using conventional pads without adding pads. which suppresses an increase in production costs. Also, the time for testing the memories is greatly reduced regardless of the number of memories.

42

Claims

CLAIMS:

1. A merged memory logic semiconductor device comprising:

a plurality of memories; pads which receive memory control signals for controlling the plurality of memories; other pads to which memory data signals received to or generated from the plurality of memories are applied:

a logic circuit for controlling the plurality of memories; and a test control circuit connected to the other pads, the logic circuit and the plurality of memories, for transmitting the memory control signals and the memory data signals to the plurality of memories when the plurality of memories are tested, in response to a test control signal and for transmitting the memory control signals and the memory data signals to the logic circuit during a normal operation.

2. A merged memory logic semiconductor device comprising: first and second memories; a pad which receives memory control signals for controlling the first and second memories; another pad which receives memory data signals generated from the first and second memories or n- ansmits memory data signals to the first and second memories., a logic circuit for controlling the first and second memories; and a memory test control circuit connected to the pad, the other pad, the logic circuit and the first and second memories, for transmitting the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and for transmitting the memory control signals and the memory data signals to the logic circuit 43 during a normal operation.

3. The merged memory logic semiconductor device of claim 2, wherein the memory test control circuit comprises:

a memory control signal controller for transmitting the memory control signals to the first and second memories and the logic circuit; a memory data controller for transmitting the memory data signals to the first and second memories and the logic circuit or transmitting memory data signals generated from the first and second memories and the logic circuit to the other pad; and a main control signal generator connected to the memory control signal controller and the memory data controller, for controlling transmission of the memory control signals to the first and second memories and the logic circuit in response to the test control signal, transmission of the memory data signals to the first and second memories and the logic, and transmission of the memory data signals generated from the first and second memories and is the logic circuit to the other pad.

4. A memory test control circuit connected to a pad, another pad. a logic circuit and first and second memories, for transmitting memory control signals and memory data signals to the first and second memories when the first and second memories are to be tested and for transmitting memory control signals and memory data signals to the logic circuit during a normal operation, the memory test control circuit comprising:

a memory control signal controller for transmitting the memory control signals to the first and second memories and the logic cricuit; 44 1 a memory data controller for transmitting the memory data signals to the first and second memories and the logic circuit or transmitting memory data signals generated from the first and second memories and the logic circuit to the other pad; and a main control signal generator connected to the memory control signal controller andthe memory data controller for connecting transmission of the memory control signals to the first and second memories andthe logic circuit in response to the test control signal, transmission of the memory data signals to the first and second memories andthe logic circuit to the other pad.

5. The memory test control circuit of claim 4, wherein the main control signal generator is a generator in which the output of the memory control signal controller and the output of the memory data controller are transmitted to the first memory unit when the first and second test control signals are inactive, the output of the memory control signal controller and the output of the memory data controller are transmitted to the second memory unit when the first test control signal is active and the second test control signal is inactive, and the output of the memory control signal controller and the output of the memory data controller are not transmitted to the logic circuit when the first test control signal is inactive and the second test control signal is active.

6. The memory test control circuit of claim 4. wherein the memory control signal controller comprises:

a buffer for receiving the memory control signals; a logic gate for receiving the output of the buffer and the main control signals and transmitting one of the outputs to the logic circuit; and a memory controller for receiving the output of the logic gate and the output of the logic circuit, and transmitting the output of the logic gate and the output of the logic circuit to the first and second memories, in response to the main control signals.

7. The memory test control circuit of claim 6, wherein the logic gate comprises: a first AND gate for receiving the output of the buffer and a first main control signal from the main control signal generator, transmitting the output of the buffer to the memory controller when the first main control signal is logic high, and blocking the output of the buffer when the first main control signal is logic low; a second AND gate for receiving the output of the main control signal and a second main control signal from the main control signal generator. transmitting the output of the buffer to the logic circuit when the second main control signal is logic high, and blocking the output of the buffer when the second main control signal is logic low; and a third AND gate for receiving the output of the buffer and a third main control signal from the main control signal generator. transmitting the output of the buffer to the memory controller when the third main control signal is logic high, and blocking the output of the buffer when the third main control signal is logic low.

8. The memory test control circuit of claim 6. wherein the memory controller comprises: a first multiplexer for receiving the output of the logic circuit and the output of the logic gate and transmitting the output of the logic circuit or the output of the logic gate to the first 46 memory unit, in response to the main control signals; and a second multiplexer for receiving the output of the logic circuit and the output of the logic gate. and transmitting the output of the logic circuit and the output of the logic gate to the second memory unit. in response to the main control signals.

9. The memory test control circuit of claim 4, wherein the memory data controller comprises:

an input/output buffer to which the memory data signals are applied; a logic gate for receiving the output of the input/output buffer and the main control signals and transmitting one of the outputs to the logic circuit; a memory controller for receiving the output of the logic gate and the output of the logic circuit and transmitting the output of the logic gate or the output of the logic circuit to the first and second memories, in response to the main control signals; an output controller for receiving memory data signals generated by the first and second memories and the output of the logic circuit and transmitting the memory data signals generated by the first and second memories or the output of the logic circuit to the input/output buffer, in response to the main control signals; and an output buffer controller for receiving the main control signals and memory data signals generated by the first and second memories, transmitting the output to the inputloutput buffer, and passing the output of the output controller through the input/output buffer when the output is active. and not passing the output of the output controller through the input/output buffer when the output is inactive.

47

10. The memory test control circuit of claim 9, wherein the inputloutput buffer comprises: an input buffer for transmitting the memory data signal to the logic gate; and an output buffer for transmitting the output of the output controller externally, in response to the output buffer controller.

11. The memory test control circuit of claim 9. wherein the logic gate comprises:

a fourth AND gate for receiving the output of the inputloutput buffer and a first main control signal, transmitting the output of the buffer to the memory controller when the first main control signal is logic high. and blocking the output of the buffer when the first main control signal is logic low; a fifth AND gate for receiving the output of the buffer and a second main control signal, transmitting the output of the buffer to the logic circuit when the osecond main control signal is logic high, and blocking the output of the buffer when the second main control signal is logic low; and a sixth AND gate for receiving the output of the buffer and a third main control signal, transmitting the output of the buffer to the memory controller when the third main control signal is logic high, and blocking the output of the buffer when the third main control signal is logic low.

12. The memory test control circuit of claim 9. wherein the memory controller comprises: a third multiplexer for receiving the output of the logic circuit and the output of the logic aate and transmitting the output of the logic circuit and the output of the logic gate to the 0 first memory, in response to the main control signals; and 48 a fourth multiplexer for receiving the output of the logic circuit and the output of the logic gate and transmitting the output of the logic circuit and the output of the logic gate to the second memory, in response to the main control signals.

13. The memory test control circuit of claim 9, wherein the output controller is a multiplexer for receiving the memory data signals generated by the first and second memories and the output of the logic circuit, and transmitting the memory data signals generated by the first and second memories and the output of the logic circuit, in response to the main control signals.

14. The memory test control circuit of claim 9, wherein the output buffer controller comprises:

a first logic gate for receiving the main control signals for controlling the first and second is memory units:

a second logic gate for receiving the memory data signals generated by the first and second memory units, a seventh AND gate for receiving the outputs of the first and second logic gates; a third logic gate for receiving the output of the seventh AND gate and the main control signals for controlling the logic circuit; and a NAND gate for receiving the output of the third logic gate and a power supply voltage and transmitting the output to the input/output buffer.

49

15. The memory test control circuit of claim 4, wherein the main control signal generator activates the memory main control signal when the test control signals are active and activates the logic main controi signal when the test control signal is inactive.

16. The memory test control circuit of claim 4. wherein the memory control signal controller comprises:

a buffer for receiving the memory control signals; a logic gate for receiving the output of the buffer, the memory main control signal and the logic main control signal, and transmitting one of the outputs to the logic circuit; and a memory controller for receiving the output of the logic gate and the output of the logic circuit, and transmitting the output of the logic gate or the output of the logic circuit to the first and second memories, in response to the memory main control signal and the logic main control signal.

17. The memory test control circuit of claim 16, wherein the logic gate comprises:

a first AND gate for receiving the output of the buffer and the memory main control signal, transmitting the output of the buffer to the memory controller when the memory main control signal is logic high, and blocking the output of the buffer when the memory main control signal is logic low; a second AND gate for receiving the output of the buffer and the logic main control signal, transmitting the output of the buffer to the logic circuit when the logic main control signal is logic high, and blocking the output of the buffer when the logic main control signal is logic low; and so 1 a third AND gate for receiving the output of the buffer and the memory main control signal, transmitting the output of the buffer to the memory controller when the memory main control signal is logic high, and blocking the output of the buffer when the memory main control signal is logic low.

18. The memory test control circuit of claim 16, wherein the memory controller comprises: a first multiplexer for receiving the output of the logic circuit and the output of the logic gate and transmitting the output of the logic circuit and the output of the logic gate to the first memory, in response to the memory main control signal and the logic main control signal; and a second multiplexer for receiving the output of the logic circuit and the output of the logic gate and transmitting the output of the logic circuit and the output of the logic gate to the second memory, in response to the memory main control signal and the logic main control signal.

is

19. The memory test control circuit of claim 4, wherein the first memory data controller comprises:

a first inputloutput buffer to which the memory data signals are applied:

a first logic gate for receiving the output of the first inputloutput buffer, the memory main control signal and the logic main control signal and transmitting one of the outputs to the logic circuit; a first memory controller for receiving the output of the first logic gate and the output of the logic circuit, and transmitting the output of the first logic gate or the output of the logic 51 circuit to the first memory, in response to the memory main control signal and the logic main control signal: a first output controller for receiving memory data signals generated by the first memory and the output of the logic circuit and transmitting memory data signals generated by the first memory or the output of the logic circuit to the first input/output buffer. in response to the memory main control signal and the logic main control signal; and a first output buffer controller for receiving the memory main control signal. the logic main control signal and the memory data signals generated by the first memory unit and transmitting the output to the first input/output buffer.

wherein the output of the first output controller passes through the first input/output buffer when the output of the first output buffer controller is active, and the output of the first output controller does not pass through the first input/output buffer when the output of the first output buffer controller is inactive.

20. The memory test control circuit of claim 19, wherein the first input/output buffer comprises: a first input buffer for transmitting the memory data signal to the first logic gate; and a first output buffer for transmitting the output of the first output controller externally, in response to the first output buffer controller.

21. The memory test control circuit of claim 19, wherein the first logic gate comprises: a first AND gate for receiving the output of the first inputloutput buffer and the memory main control signal, transmitting the output of the first input/output buffer to the first 52 memory controller when the memory main control signal is transmitted, and blocking the output of the first input/output buffer when the memory main control signal is logic low; a second AND gate for receiving the output of the first inputloutput buffer and the main control signal, transmitting the output of the first input/output buffer to the logic circuit when the main control signal is logic high, and blocking the output of the first inputloutput buffer when the main control signal is logic low.

22. The memory test control circuit of claim 19, wherein the first memory controller is a multiplexer for receiving the output of the logic circuit and the output of the first logic gate and transmitting the output of the logic circuit and the output of the first logic gate, in response to the memory main control signal and the logic main control signal.

23. The memory test control circuit of claim 19, wherein the first output controller is a multiplexer for receiving the memory data signals generated by the first memory unit and is the output of the logic circuit and transmitting the memory data signals generated by the first memory or the output of the logic circuit to the first input/output buffer, in response to the memory main control signal and the logic main control signal.

24. The memory test control circuit of claim 18, wherein the first output buffer controller comprises:

a third AND gate for receiving the memory main control signal and memory data signals generated from the first memory unit; a first logic gate for receiving the output of the third AND gate and the main control signal; 53 and a first NAND gate for receiving the output of the first logic gate and a power supply voltage.

25. The memory test control circuit of claim 4, wherein the second memory data controller comprises: a second inputloutput buffer to which the memory data signals are applied, a second logic gate for receiving the output of the second inputloutput buffer, the memory main control signal and the logic main control signal, and transmitting one of the outputs 10 to the logic circuit; a second memory controller for receiving the output of the second logic gate and the output of the logic circuit and transmitting the output of the second logic gate or the output of the logic circuit to the second memory, in response to the memory main control signal and the logic main control signal: a second output controller for receiving memory data signals generated from the second memory and the output of the logic circuit, and transmitting the memory data signals generated from the second memory unit or the output of the logic circuit to the second inputloutput buffer, in response to the memory main control signal and the logic main control signal: and 20 a second output buffer controller for receiving the memory main control signal, the logic main control signal and the memory data signal generated from the second memory inputloutput buffer, wherein the output of the second output controller passes through the second input/output is 54 buffer when the output of the second output buffer controller is active, and the output of the second output controller does not pass through the second inputloutput buffer when the output of the second output buffer controller is inactive.

26. The memory test control circuit of claim 25, wherein the second input/output buffer comprises: a second input buffer for transmitting the memory data signal to the second logic gate; and a second output buffer for transmitting the output of the second output controller externally, in response to the second output buffer controller.

27. The memory test control circuit of claim 25, wherein the second logic gate comprises:

a fourth AND gate for receiving the output o the second input/output buffer and the memory main control signal, transmitting the output of the second input/output buffer to the second memory controller when the memory main control signal is logic high, and blocking the is output of the second inputloutput buffer when the memory main control signal is logic low; and a fifth AND gate for receiving the output of the second input/output buffer and the main control signal, transmitting the output of the second input/output buffer to the logic circuit when the main control signal is logic high, and blocking the output of the second input/output buffer when the main control signal is logic low.

28. The memory test control circuit of claim 25, wherein the second memory controller is a multiplexer for receiving the output of the logic circuit and the output of the second logic gate and transmitting the output of the logic circuit and the output of the second logic gate to the memory, in response to the memory main control signal and the logic main control signal.

29. The memory test control circuit of claim 25. wherein the second output controller is a multiplexer for receiving the memory data signals generated from the second memory unit and the output of the logic, and transmitting the memory data signals generated from the second memory or the output of the logic circuit to the second input/output buffer, in response to the memory main control signal and the logic main control signal.

30. The memory test control circuit of claim 25, wherein the second output buffer controller comprises: a sixth AND gate for receiving the memory main control signal and the memory data signal generated from the second memory unit: a second logic gate for receiving the output of the sixth AND gate and the main control signal: and a second NAND gate for receiving the output of the second logic gate and a power supply voltage.

3 1. The merged memory logic semiconductor device of claim 2, wherein the memories are DRAM banks.

32. A merged memory logic semiconductor device comprising:

56 a plurality of pads to which one or more external clock signals and test enable signals are applied; a plurality of other pads; at least two memories in which data is stored: and one or more built-in self-tester for testing functions of the memories, in response to the clock signals and the test enable signal. and sending the results to the other plurality of pads.

33. The merged memory logic semiconductor device of claim 32. wherein the memories are DRAM banks.

1.0

34. A merged memory logic semiconductor device including a logic circuit and a memory, comprising:

first and second pads to which external first and second clock signals are applied, respectively; third and fourth pads to which external first and second test enable signals are applied, respectively; fifth and sixth pads:

first and second memories in which data are stored; a first built-in self-tester connected to the first memory unit, the first and third pads, for testing functions of the first memory, in response to the first clock signal and the first test enable signal, and sending the results to the fifth pad; and a second built-in self-tester connected to the second memory unit, the second pad and the fourth pad, for testing functions of the second memory, in response to the second clock 57 signal and the second test enable signal, and sending the results to the sixth pad.

35. The merged memory logic semiconductor device of claim 34. wherein the memories are DRAM banks.

36. A merged memory logic semiconductor device having a logic circuit and a memory, comprising: a first pad to which an external clock signal is applied: second and third pads to which external first and second test enable signals are applied, respectively; fourth and fifth pads; first and second memory units in which data are stored, a first built-in self-tester connected to the first memory unit and the first and second pads, for testing functions of the first memory, in response to the clock signal and the first test enable signal. and sending the results to the fourth pad; and a second built-in self-tester connected to the first memory unit and the first and second pads, for testing functions of the first memory, in response to the clock signal and the first test enable signal, and sending the results to the fourth pad.

37. The merged memory logic semiconductor device of claim 36, wherein the memories are DRAM banks.

38. A merged memory logic semiconductor device having a logic circuit and a memory, 58 comprising:

a first i)ad to which an external clock signal is applied:

second and third pads to which external first and second test enable signals are applied, respectively; fourth and fifth pads; first and second memories in which data are stored:

a built-in self-tester connected to the first memory unit and the first to third pads, for testing functions of the first and second memories, in response to the clock signal and the first and second test enable signals, and sending the results to the fourth and fifth pads, respectively.

39. The merged memory logic semiconductor device of claim 38, wherein the memories are DRAM banks.

40. A memory test method of a merged memory logic semiconductor device having a logic circuit, a memory and a built-in self-tester. comprising the steps of.

applying a clock signal and a test enable signal for activating the builtin self-tester to the built-in self-tester; generating control signals for testing a function of the memory from the built-in self-tester; generating an output data signal from the memory; and generating a test result signal showing the test result of the memory from the built-in self tester.

41. A memory test method of a merged memory logic semiconductor device having a built- 59 in self-tester connected to an external terminal and a plurality of memories, comprising the steps of: a) writing data in the built-in self- tester and the plurality of memories; and b) reading data stored in the plurality of memories by the built-in self-tester.

42. The memory test method of claim 41, wherein the step a) of writing data comprises the sub-steps of:

al) activating the plurality of memories; a2) reading the data stored in the plurality of memories by the built-in self-tester; and a3) writing the data in the plurality of memories by the built-in self- tester.

43. The memory test method of claim 42, wherein in the step al) of activating the plurality of memories, the built-in self-tester is activated to activate the plurality of memories.

44. The memory test method of claim 41, wherein the step b) of reading data comprises the sub-steps of: bl) reading the data stored in the memory by the built-in self-tester.. and b2) precharging the memories.

45. The memory test method of claim 41, wherein in the step a) of writing data, the built-in self-tester sequentially writes data in the plurality of memories.

46. The memory test method of claim 41, wherein in the step b) of reading data, the builtin self-tester sequentially reads data from the plurality of memories.