TW383423B - Chemical mechanical polishing method with controllable polishing depth - Google Patents

Abstract

A kind of chemical mechanical polishing method with controllable polishing depth which is applied to semiconductor circuit with memory area. The surface of semiconductor circuit is covered by polysilicon layer. This kind of chemical mechanical polishing method is to form a predetermined thickness of silicon oxide on the surface of polysilicon and forming silicon nitride as barrier on the surface of silicon oxide; then, defining the memory area of semiconductor circuit which is to remove the silicon nitride, silicon oxide and polysilicon outside the memory area; forming another silicon oxide to cover whole semiconductor circuit and applying chemical mechanical polishing on the silicon oxide to expose the surface of silicon nitride; last, removing the exposed silicon nitride and complete the processes.

Description

V. Description of the invention (1) The invention relates to a planarization process (planariza1: ion process), and in particular to a chemical mechanical polishing (CMP) method capable of controlling the depth of polishing. «Refer to Figures 1A ~ 1C. This is a flow chart of the conventional chemical mechanical polishing method for dynamic random access memory (DRAM). As shown in FIG. 1A, 'a semiconductor substrate 10 for constructing a semiconductor circuit', such as a Shi Xi substrate, can be divided into a memory region 丨 2 and an active region 丨 4. The surfaces of the memory region 12 and the active region 14 are simultaneously covered with a top layer 16, such as a polysilicon layer on the capacitor electrode. The memory area 12 is flipped to form dynamic random access memory (DRAM) or other types of memory. The active area 14 is used to form a logic circuit or other circuits. In general, since the memory region 12 will form an additional capacitor 'on the surface of the dynamic random access memory or other types of memory, the thickness is often higher than that of the logic circuit or other circuits in the active region. ^ Then “as shown in FIG. 1B”, the top layer (the polycrystalline silicon layer of the electrode on the capacitor) other than the memory region 丨 2 is removed by etching. A thicker BPTE0s layer 18 is deposited on the semiconductor substrate 10 (including the memory region 12 and the active region 14), and the BPTE0S layer 18 is etched back or chemically mechanically polished to obtain a planarized semiconductor circuit surface, as Figure 1C. However, it is difficult to precisely control the depth of the chemical mechanical polishing, that is, the thickness of the BPTEOS layer 18 on the top layer 16. In general, the CMP deviation of the chemical mechanical polishing is about 2000 Angstroms. However, the process with a thinner line width, such as the 0.18 μm process, cannot tolerate such a large error. Generally, when the thickness of the BPTEOS layer 18 on the top layer 16

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If it is too large, it will cause trouble for subsequent contact etching. Conversely, when the thickness of the BPTEOS layer 18 on the top layer 16 is too small, the lower top layer 16 may be damaged. In view of this, the main object of the present invention is to provide a chemical mechanical polishing method, which can effectively control the thickness of the BPTE0s layer 18 above the top layer 16 within a predetermined range. According to the present invention, the contact erosion can be avoided to achieve the above grinding method. In such a bulk circuit, a second dielectric layer of a predetermined thickness has a suitable barrier layer (a third dielectric etch selectivity ratio is formed on the second dielectric layer of the CMP. The dielectric layer is often high in this type). In the case of semiconductors composed of a polycrystalline silicon layer, the dielectric layer can be a BPTE0S layer. In the step of covering the semiconductor etching process and other methods, the first surface is covered with a dielectric layer and a Barrier etch, and the first dielectric is selected. Floor. Third, the chemical mechanical polishing circuit is exposed in addition to the other components. In addition, it is a deposition method. Another purpose is to provide a chemical mechanical polishing method where the top layer 16 of the circuit is damaged and the subsequent accuracy is accurate. The present invention is to provide a chemical-mechanical research that firstly needs to provide a semiconductor layer having a memory region. Then, a second dielectric layer is sequentially formed on the top surface. The second dielectric layer and the first selective ratio are used as a chemical mechanical polishing method. Then, the outer layer and the top layer of the memory region are removed by etching, and the third dielectric layer is appropriately mechanically polished throughout the dielectric layer and the second dielectric layer of the semiconductor circuit to expose the second dielectric layer to complete the planarization process. The memory region of the semiconductor circuit is connected to the domain; and the top layer of the semiconductor circuit is usually a first dielectric layer, a second dielectric layer, a third silicon oxide layer, a silicon nitride layer, and

In addition, the second dielectric layer, the first dielectric layer, and the top f outside the memory region can be removed by dry etching. The exposed second dielectric layer can be removed by dry etching or wet etching. # a ί Make the above and other objects, features, and advantages of the present invention more clear *, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Schematic illustrations 1A ~ 1 c The figure is a flowchart of a conventional dynamic random access memory chemical mechanical polishing method (DRAM CMP); and 2A ~ 2F are the flowcharts of the dynamic random access memory chemical mechanical polishing method (DRAM CMP) of the present invention? Example Please refer to Figs. 2A to 2F. This is a flowchart of a dynamic random access memory chemical mechanical polishing method (DRAM CMP) of the present invention. First, as shown in FIG. 2A, a semiconductor circuit is provided, which has a memory region and covers a top layer. As is conventional, a semiconductor substrate 20, such as a silicon substrate, used to construct a semiconductor circuit can be divided into a memory region 22 and an active region 24. The surfaces of the memory region 22 and the active region 24 are covered with a top layer 26, such as a polycrystalline silicon layer of an electrode on the valley. In this embodiment, the memory area 22 is used to form a dynamic random access memory (DRAM) or other types of memory. The active area 24 is used to form a logic circuit or other circuits. Under normal circumstances, because the memory area 22 will additionally form a capacitive upper electrode (such as the top layer 26) on the surface of the dynamic random access memory or other types of memory, the type is often higher than that in the active area 24. Logic or other circuits. thick

V. Description of the Invention (4) Next, as shown in FIG. 2B, a first dielectric layer and a second dielectric layer with a predetermined thickness are sequentially formed on the surface of the top layer, wherein the second dielectric layer and The first dielectric layer has a first etching selectivity. In this embodiment, the first dielectric layer 28 and the second dielectric layer 30 may be oxide layers and silicon nitride layers formed by a deposition method, respectively. The CMP selection ratio of the silicon nitride layer and the silicon oxide layer is approximately 疋 1: 2. The thickness of the first dielectric layer 28 is the thickness of the dielectric layer to be retained on the surface of the top layer 26 (capacitor upper electrode) after the subsequent chemical mechanical polishing, and the first dielectric layer 30 is used in the subsequent chemical mechanical polishing step. , As a barrier layer. Since the second dielectric layer 30 for barrier is formed on the surface of the first dielectric layer 28, the chemical mechanical polishing step allows the thickness of the dielectric layer to be retained on the surface of the top layer 26 to be accurately determined in this step. The depth of mechanical grinding can be precisely controlled, which is caused by the difficulty in controlling the grinding depth. The damage to the top layer and the contact etching are not easy, and can be solved at the same time. Next, as shown in FIG. 2C, the second dielectric layer, the first dielectric layer, and the top layer are etched to define the top layer pattern of the memory region. In the H example, a photoresist layer 32 is first formed on the second dielectric layer 30, and the active area 24 and the memory body area 22 are not intended to retain the top layer 26 (capacitance upper electrode). Then, this photoresist layer 32 is used. For the mask, the second dielectric layer 30 °, the dielectric layer 26 and the top layer 26 are etched to define a capacitor power-on scheme of the memory region. After the definition step is completed, the photoresist layer 32 is removed. Next, as shown in FIG. 2D, a third dielectric layer is formed to cover the body circuit and the second dielectric layer, wherein the third dielectric layer and the second human electrical layer have a second choice. In contrast, in this embodiment, the G3 5 'layer 34 may be a BpTE0s layer formed by a deposition method to cover the entire half.

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5. Description of the invention (5) Conductor circuit. The CMP selection ratio of the silicon nitride layer 32 and the BPTEOS layer 34 is approximately 1: 6. Since the first dielectric layer 28 and the second barrier layer 30 for barrier have been formed on the surface of the memory region 22 with a predetermined thickness, that is, the thickness to be retained on the surface of the top layer 26 after chemical mechanical polishing ( As described above), the third dielectric layer 34 is mainly used for planarization of the active region 24. Next, as shown in FIG. 2E, the third dielectric layer is chemically and mechanically polished until the second dielectric layer is exposed. In this embodiment, the CMP selection ratio of the second dielectric layer 32 (silicon nitride layer) and the third dielectric layer 34 (BPTEOS layer) is approximately! : 6, when the chemical mechanical polishing is continued until the surface of the second dielectric layer 32 (silicon nitride layer) is exposed, the “卩” speed of the semiconductor circuit in the memory region 22 will be much lower than the etching rate of the active region 24. The chemical mechanical polishing method can be stopped after the second dielectric layer 32 (silicon nitride layer) is exposed, and the thickness of the dielectric layer of the memory region 22 above the top layer 26 can be accurately controlled. Then, as shown in FIG. 2F In the embodiment of removing the exposed second dielectric, when the step of chemical mechanical polishing is stopped, that is, after the flattening process is completed, the second dielectric exposed on the surface is removed by using a dry type #etching $ wet method. Layer 32 (silicon nitride layer). K body region 22 In summary, the chemical mechanical polishing method of the present invention can effectively control: the thickness of the dielectric layer of the body circuit on the surface of the memory region. The grinding depth of Research 1 can be precisely controlled, because of the uneven grinding depth: the damage to the top layer and the contact etching can not be easily solved at the same time._ Although the present invention has been disclosed in the preferred embodiment above, the present invention is limited, anyone familiar with this technique Or, in: f is not used for and scope When do alterations and modifications due

V. Description of the invention (6) Subject to the scope of the attached patent application. iumw C: \ ProgramFiles \ Patent \ 0503-3876-E.ptd page 9

Claims (1)

6. Scope of Patent Application 1. A chemical mechanical polishing method, comprising: providing a semiconductor circuit having a memory region and covering a top layer; forming a first dielectric layer of a predetermined thickness on a surface of the top layer; forming a second dielectric An electric layer is on the surface of the first dielectric layer, the second dielectric layer and the first dielectric layer have a first etching selection ratio; and the second dielectric layer, the first dielectric layer and the top layer are etched, The top pattern of the memory area is defined by this; a third dielectric layer is formed to cover the semiconductor circuit and the second dielectric layer, and the third dielectric layer and the second dielectric layer have a second etch Selection ratio; chemically and mechanically grinding the third dielectric layer to expose the second dielectric layer; and removing the exposed second dielectric layer. 2. The chemical mechanical polishing method according to item 1 of the scope of patent application, wherein the memory area of the semiconductor circuit is higher than other areas of the semiconductor circuit. 3. The chemical machine polishing method according to item 1 of the scope of patent application, wherein the top layer of the semiconductor circuit is a polycrystalline silicon layer of an electrode on a capacitor. 4. The chemical mechanical polishing method according to item 1 of the scope of patent application, wherein the first dielectric layer is a silicon oxide layer and the second dielectric layer is a silicon nitride layer. 5. The chemical mechanical polishing method according to item 4 of the scope of patent application, wherein the first dielectric layer and the second dielectric layer are formed by a deposition method. 6. The chemical mechanical polishing method described in item 1 of the scope of patent application, which C: \ ProgramFiles \ Patent \ 0503-3876-E.ptd page 10 6. In the scope of patent application, the second dielectric layer is a silicon nitride layer, and the third dielectric layer is a BPTEOS layer. 7. The chemical mechanical polishing method according to item 6 of the patent application scope, wherein the second dielectric layer and the third dielectric layer are formed by a deposition method. 8. The chemical mechanical polishing method according to item 1 of the patent application scope, wherein the top layer of the memory region is patterned by an etching method. 9. The chemical mechanical polishing method according to item 1 of the patent application scope, wherein the exposed second interlayer is removed by a dry etching method. 10. The chemical mechanical polishing method according to item 1 of the scope of patent application, wherein the exposed second dielectric layer is removed by a wet etching method. C: \ ProgramFiles \ Patent \ 0503-3876-E. Ptd page 11