經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（丄） 本發明所羼的分解 本發明係屬於，欲保持CMOS閛極（gate)之遲延時間為 一定值的電路中，只附加簡單之電路並且以低消耗功率， 即能獲得正確之浬延時間信號的遲延時間控制電路。 本發明的背景 由於CMOS閘極的遲延時間隨電路元件的溫度變化而改 變，而電路元件的溫度又因電源電壓的變動或消耗功率的 變化而發生變化。另方面，在VLSI測試条統（test system) 上，要產生時序信號（timing signal)的電路欲獲得正確 之時序信號時，務必保持遲延時間爲一定值。由於此，欲 穩定遲延時間，在既有習知技藝上有下列之電路： ⑴利用CMOS閛極的遲延時間與溫度之親係，檢出CMOS 閘極的遲延時間而控制LSI內的發熱電路。 ⑵利用發熱量成比例於頻率的關係，將電路的動作頻 率在整醱上經常保持一定，而使發熱量亦保持一定，Μ保 持CMOS閘極的運延時間為一定值。 ⑶利用CMOS閘極的遲延時間與罨源電壓之蹰係，檢出 CMOS閛極的遲延時間而控制LSI的霣源電壓。 於上述第0)項及第⑵項的電路，由於CMOS的消耗功率 為一定值之故，不能作為低消耗功率，並且附加霄路亦要 加大甚多。例如，在第⑴項邸要追加遲延時間檢出電路及 加熱元件。在第⑵項邸要迫加對動作電路有互補動作的虚 擬（dunny)電路。在第(3)項的電路，為補償電源電壓產生 霣路的電位下降，電路整體的電源霣壓將變大，同時，使 (請先聞讀背面之注意事項再填寫本頁) •^1 訂 Λ 本紙張尺度適用中國國家標準（CNS ) Α4現格（210Χ 297公釐） 5 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（2 ) 其消耗功率亦增加。 雖然，第0)項，第(2)項及第⑶項的任一方法，均能保 持遲延時間爲一定值，惟要控制各閘極之100 PS/閛極或 200 ps/閘極等的遲延時間，邸需要其他之裝置。例如， 第(3)項之因電源電麽而生的遲延時間的赛化董不大，因此 ，欲保持遅延時間爲一定值，即要包含元件之禳差而生的 涯延時間差值，及隨動作頻率之變化而產生溫度變化而生 的遲延時間的差值，來改變CMOS閘極輓出端的容量，以變 更遲延時間的方法等，需要併用複雜的遲延時間控制裝置 ，乃使電路規模加大。 本發明的目的 本發明係Μ實現在保持CMOS閘極的遅延時間爲一定值 之電路中，只附加低消耗功率並且簡單之電路，邸能獲得 正確之遲延時間信號的遲延時間控制電路為目的。 本發明的電路構成 本發明的埋延時間控制電路含有：輪入一定週期的脲 波於將邏輯元件Μ串聯連接的遲延電路中，設置前端運延 電路All以及後端遲延霣路Β12,由遲延霣路411所產生的 脲波A作重設定（reset)，而由遲延霣路812所產生的脲波 B作設定（set)，Μ正反器（fl ip-flop)成為遲延時間/工 作變換電路14、變換工作（duty)為電壓準位（level)信號 的稹分器15、控制遲延電路的遲延時間，使工作為一定之 遲延時間控制部16、調整遲延時間之設定值的遲延時間設 定電壓DAC 17、由遲延時間控制部16的遲延控制電壓*再 (請先閲讀背面一6意事項再填寫本t 裝· 訂Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Explanation of the invention (丄) The invention belongs to the circuit which is to keep the delay time of the CMOS gate to a certain value. A simple circuit with low power consumption, that is, a delay time control circuit capable of obtaining a correct delay time signal. BACKGROUND OF THE INVENTION The delay time of the CMOS gate changes with the temperature of the circuit element, and the temperature of the circuit element changes with the power supply voltage or the power consumption. On the other hand, on a VLSI test system, a circuit that needs to generate a timing signal needs to keep the delay time to a certain value in order to obtain the correct timing signal. Because of this, in order to stabilize the delay time, there are the following circuits in the conventional art: ⑴ Use the relationship between the delay time and temperature of the CMOS pole to detect the delay time of the CMOS gate to control the heating circuit in the LSI. ⑵Using the relationship between the amount of heat generated and the frequency, the circuit's operating frequency is often kept constant, and the amount of heat generated is also kept constant. M keeps the delay time of the CMOS gate to a certain value. (3) The delay time of the CMOS gate and the source voltage are used to detect the delay time of the CMOS gate to control the source voltage of the LSI. The circuits in the above items (0) and (2) cannot be regarded as low power consumption because the power consumption of the CMOS is a certain value, and the additional roads must be greatly increased. For example, a delay time detection circuit and a heating element are added to the second house. In the second house, a dummy circuit with complementary actions to the action circuit must be added. In the circuit of item (3), in order to compensate for the potential drop in the circuit caused by the power supply voltage, the power supply voltage of the entire circuit will increase and at the same time, (please read the precautions on the back before filling out this page) Ordering Λ This paper size applies Chinese National Standard (CNS) Α4 is now standard (210 × 297 mm) 5 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Its power consumption also increases. Although any of the methods (0), (2), and (3) can keep the delay time to a certain value, it is necessary to control the 100 PS / PS or 200 ps / gate of each gate. For delays, the residence needed other equipment. For example, the delay time of the delay time due to the power supply of item (3) is not large. Therefore, if you want to keep the delay time to a certain value, that is, to include the difference between the delay time of the components, And the delay time difference caused by the temperature change with the change of the operating frequency, to change the capacity of the CMOS gate pull-out terminal, to change the delay time, etc., it is necessary to use a complex delay time control device in combination with the circuit scale. Increase. Object of the present invention The present invention aims to achieve a delay time control circuit that can obtain a correct delay time signal in a circuit that maintains the delay time of a CMOS gate to a certain value, and only adds a low-power and simple circuit. The circuit configuration of the present invention The buried time control circuit of the present invention includes: a urea circuit of a certain period is rotated in a delay circuit that connects the logic element M in series, a front-end delay circuit All and a back-end delay loop B12 are provided, and the delay The urea wave A generated from Kushiro 411 is reset, and the urea wave B generated from delayed Kushiro 812 is set, and the M flip-flop (fl ip-flop) becomes the delay time / working change. Circuit 14, Divider 15 which converts duty to voltage level signal 15, Controls the delay time of the delay circuit so that the operation is a certain delay time Control unit 16, Delay time setting which adjusts the set value of the delay time Voltage DAC 17, Delay control voltage by the delay time control unit 16 * Again (Please read the first 6 notes on the back before filling in this t
L " 本紙張尺度適用中國國家標準（CNS ) A4规格（210X 297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3 ) 產生另一遲延控制電壓的邏楫臨限值電壓控制電路18, Μ 及Μ遲延控制霄歷控制遲延時間之1C内的一般電路之邇輯 電路13。 在遲延時間控制部16,設有比較積分器15的輪出電壓 VI與遲延時間設定電壓DAC 17的_出電壓V2,而產生控制 遲延時間之電壓的電路。在邏輯臨限值電騣控制電路18, 包含：產生電源VDD及霣源VSS之中間數值的基準電壓產生 電路181、NVcont與PVcont能以對稱變動電®所構成之臨 限值產生電路183、以及Μ產生兩電源之中間值的基準電 壓產生電路181之中間電壓，及MNVcont與PVcont所控制 的臨限值產生電路183之中間霉壓爲_入霣壓，而產生PV cont之臨限值電壓控制電路182。 運延時間/工作變換電路24,經由脈波產生器20_入 時鐘（clock)信號，而設置以串嫌連接邇延元件之可變邇 延電路A21。惟亦得将前述可變遲延電路戍21的_入信號_ 入於重設定端子，而輸出信號輪入於設定端子來構成正反 器。或著，邐延時間/工作變換電路，亦可將運延元件以 串聯連接，並將轤出反轉連接於輸入，而構成環式振盪器 (ring oscillator)的可變邇延電路BM，同時，亦得以該 可變遲延電路B31的輪出為觸發器（trigger〉，而產生一定 寬度之脲波，並將其_出输入於積分器15,作成固定脈波 產生器32。 於前述所構成之遲延時間控制電路中，欲保持CMOS聞 極的遲延時間為一定值之電路，只附加簡單之電路而Μ低 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝· 7 .經濟部中央樣準局員工消費合作社印裝 A7 B7 五、發明説明（4 ) 消耗功率，就能達成。又具有能實現指定需要獲得正確之 遅延時間信號的遲延時間控制電路的功用。 本發明的實施例 第1画表示本發明的實施例之方塊圔。該電路包含有 :輸入一定週期的脈波，而在串聯建接箱要遲延的遲延電 路中之前端遲延電路All與後端遲延霣路B12、由遲延電路 All所產生的脈波A作重設定，並Μ遲延電路B12所產生的 脈波Β作設定，形成為正反器的遲延時間/工作變換電路 14、將工作變換的霣壓準位信號的積分器15、欲使工作為 一定而控制遲延霉路的遲延時間之遲延時間控制部16、調 整埋延時間設定值的S延時間設定電壓DAC 17、從遲延時 間控制部16之遲延控制電IS NVcont，產生另一遲延控制電 壓PVcont的邇輯臨限值電壓控制電路18、Μ及以遲延控制 霣壓控制遲延時間的1C内之一般電路的暹輯轚路13。 第2圖U〉為使用於遲延電路All、運延電路Β12Μ及 一般電路的邏輯霄路13之倒反器（Inverter)電路，其遲延 時間MQ3及Q4的閘極電壓PVcont及NVcont而控制之。第2 圖（b)，係表示第2圖（a)的倒反器霄路之動作情形。Q3及 Q4係由閘極轚壓使其電阻值成為可變，而Μ與翰出端out 的漂浮容量之關係，使遲延量亦成爲可變，乃將Μ閘極電 靨作1延控制。 第3圖爲表示在第1圖所示之霣路的動作。遲延電路 All及《延電路Β12為，具有傳送一定週期的脲波輸入之串 聯連接的閘極組件，並如第2圖所示*由閘極電壓PVcont 本紙張尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） ---------，厂裝_：------訂----^---- ,ν •" (請先閲諫背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5 ) 及NVcont而控制遲延時間。 首先，由在遲延電路之前端的運延霄路All之A1信號 及A2信號，產生脲波信號A，又在運延電路後端之遲延電 路B12.的B1信號及B2信號，產生脈波信號B。脈波信號A 及B在運延時間/工作變換電路14的正反器作重設定/設 定之控制，並產生_出Q。該時，設定信號B由所串聯的 閛極組件之遅延時間，使其有前後之時序（TUing)。正反 器（F/F)的輪出功率Q輓入於積分器15,而變換為Μ輸出 Q的” ΓΜ及”0"的時間比率變化為霉壓VI。 如第4圓所示，積分器15的輸出VI與遅延時間設定電 壓DAC 17的輸出V2相比較，而產生控制遲延時間之電壓NV cont。從遲延時間控制部16所輪出的電壓NVcont為，控制 遲延電路以及其他邏輯電路13的下降時間之外，尚要產生 對醮於NVcont而要控制上昇時間之電壓PVcont之故，乃要 鴒入於邏輯臨限值霄壓控制霣路18。 如第5圖所示，邏輯臨限值電壓控制霄路18,係要產 生電壓PVcont，其電路中包含有：要產生電源VDD及電源 VSS的中間值的基準電壓產生電路181，構成NVcont及PVcont 的電壓變動相對稱之臨限值產生電路183、Μ及Μ產生兩 電源的中間值之基準電壓產生電路181的中間電魘，及以 NVcont與PVcont所控制之臨限值產生霄壓183的中間電壓 為_人電壓，而要產生PVcont的臨限值電壓控制電路182 0 在前述之說明，係在«延時間控制部16產生NVcont， 本紙張尺度逋用中國國家標準（CNS ) A4規格（210Χ29"7公釐） (請先閲讀背面之注意事項再填寫本莧) -裝- 訂 A7 B7 五、發明説明（6 ) 請 先 閲 % 背 之 注 意 事 項 再 填 、 Ϊ裝 頁 而以邐辑臨限值霣壓控制電路18產生PVcont。惟亦得以相 反方法，Μ邇延時間控制部16產生PVcont，而以邏輯臨限 值霉壓控制霄路18產生NVcont。 訂 第6圖表示本發明之第2實施例。於該霣路，遲延時 間/工作變換電路24,係經由脲波產生器20輪人時鐘信號 ，並設置以串聯連接之遲延元件的可變遲延霉路A21，而 將其蠄入信號繪入於重設定端子*鴒出信號幘入於設定端 子，以形成正反器。時鐘信號經由脲波產生器20輪入於能 以PVcont及NVcont控制運延時間的串脚連接的遲延元件之 可變遲延電路A21，而其繪入與輪出邸連接於遲延時間/ 工作變換電路24的設定重設定正反器之重設定蠄入端子及 設定輸入端子。該正反器的Q輪出信號，只於可變遲延霉 路A21通過脈波之時間保持爲”L”的通輯，並成爲與時鐘信 號同一遇期的反覆信號，即因應可變遲延電路A21的遲延 時間成為工作週期（duty cycle)會變化的信號。 經濟部中央標準局員工消費合作社印製 第7圏表示本發明的第3實施例。於該電路*遲延時 間/工作變換霄路，係串聯連接遲延元件並反轉翰出連接 於ϋ入而形成環式振盪器（ring oscillator〉之可變遲延 霄路B31，並Μ其輪出為觸發器（trigger)而產生一定寬度 的脲波，並將其II出輪入於積分器15而成為固定脈波產生 器32。該環式振盪器的振盪頻率相當於可變遲延電路B31 的«延時間之兩倍，而Μ此振盡輪出作爲上昇與下降動作 的脈波寬度，蠄入於一定的固定脲波產生器32之後，邸可 得脲波寬度一定而遇期變化之信號D。則，順應可變遲延 本紙法尺度適用中國國家榡準（CN’S ) Α4規格（210Χ 297公釐） 10 - 10 A7 B7 經濟部中央標準局貝工消費合作社印装 五、發明説明（ 霄路B31的遲延時間，可使其成為工作週期變化的信號。 於此場合之可變遲延電路B31的輪出C與固定脈波產生器 32的鎗出D之時序鼷係，表示於第8圖。 本發明之效果： 本發明如前述所說明之構成，而具有欲保持CMOS閘極 的遲延時間爲一定值之電路中，只Μ簡單之附加電路並且 Μ低消耗功率即能逹成。又具有能實現指定需要獲得正確 之遲延時間信號的遲延時間控制霣路的效果。 圖面簡要說明 第1圖為本發明之電路方塊圔。 第2圖為本發明之倒反器（Inverter)的基本電路圖及 其時序圓（timing diagro·)。 第3圖為本發明的霣路之時序圖。 第4圖表示本發明之遲延時間控制部的一例之電路圈 〇 第5鼴表示本發明的通輯臨限值電壓控制電路之一例 的霉路圖。 第6圜為本發明第2實麁例的電路方塊圖。 .第7圖為本發明第3實施例的轚路方塊圖。 第8圖表示本發明第3實施例的電路之時序圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（21ΌΧ297公釐） ---------1 ·裝------訂------^ ^ (請先閲讀背面乏注意事項再填寫本頁) -T 1 - 11L " This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (3) Logic Producing another delay control voltage The limit voltage control circuit 18, the M and the M delay circuit 13 are the general circuit 13 of the general circuit within the delay time of 1C. The delay time control unit 16 is provided with a circuit that compares the wheel-out voltage VI of the integrator 15 and the output voltage V2 of the delay time setting voltage DAC 17 to generate a voltage that controls the delay time. The logic threshold electric control circuit 18 includes a reference voltage generating circuit 181 that generates an intermediate value between the power source VDD and the source VSS, a threshold value generating circuit 183 that can be configured to symmetrically change the voltage between NVcont and PVcont, and The intermediate voltage of the reference voltage generating circuit 181 which generates the intermediate value of the two power sources, and the intermediate mold voltage of the threshold value generating circuit 183 controlled by MNVcont and PVcont are _into the pressure, and the threshold voltage control of PV cont is generated. Circuit 182. The delay time / operation conversion circuit 24 inputs a clock signal via the pulse generator 20_, and sets a variable delay circuit A21 connected to a delay element in series. However, the _input signal_ of the aforementioned variable delay circuit 戍 21 must be input to the reset terminal, and the output signal must be input to the set terminal to form a flip-flop. Alternatively, the delay time / operation conversion circuit can also connect the delay elements in series and connect the output inversion to the input to form a variable delay circuit BM of a ring oscillator. In this way, the rotation of the variable delay circuit B31 can be used as a trigger to generate a urea wave of a certain width and input it to the integrator 15 to form a fixed pulse wave generator 32. In the delay time control circuit, the circuit that wants to keep the delay time of the CMOS electrode to a certain value, only simple circuits are added, and the low paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) (Please read first Note on the back, please fill in this page again) Equipment · 7. Printed by A7 B7, Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs 5. Description of Invention (4) Consumption of power can be achieved. It also has the necessary delay to achieve the specified requirements The function of the delay time control circuit of the time signal. The first drawing of the embodiment of the present invention shows a block 圔 of the embodiment of the present invention. The circuit includes: inputting a pulse of a certain period, and In the delay circuit to delay the connection of the box, the front-end delay circuit All and the back-end delay loop B12, the pulse wave A generated by the delay circuit All is reset, and the pulse wave B generated by the M delay circuit B12 is set to form Delay time / operation conversion circuit 14 for the flip-flop, integrator 15 for suppressing the level signal for converting the operation, delay time control section 16 for controlling the delay time of the delay mold road to make the operation constant, and adjust the delay Time set value S delay time setting voltage DAC 17, delay control voltage IS NVcont from delay time control section 16 generates another threshold voltage control circuit 18, M of delay control voltage PVcont and delay control voltage The Siegiri Road 13 of the general circuit within 1C that controls the delay time. Figure 2 U> is an inverter circuit for the logic circuit 13 of the delay circuit All, the delay circuit B12M and the general circuit. The delay time MQ3 and Q4 are controlled by the gate voltages PVcont and NVcont. Fig. 2 (b) shows the operation of the inverter road in Fig. 2 (a). Q3 and Q4 are pressed by the gate Make its resistance variable, The relationship between the floating capacity of M and the out of the outlet makes the delay amount variable, and the M gate electrode is controlled for 1 delay. Fig. 3 shows the operation of the road shown in Fig. 1. The delay circuits All and "B12" are gate devices connected in series to transmit a certain period of urea wave input, and as shown in Figure 2 * by the gate voltage PVcont This paper standard applies Chinese National Standard (CNS) Α4 Specifications (210 X 297 mm) ---------, factory-installed _: -------- Order ---- ^ ----, ν • " (Please read the back of 谏Please fill in this page again for attention) Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (5) and NVcont to control the delay time. First, the urea wave signal A is generated from the A1 and A2 signals of the Yanxiao Road All at the front end of the delay circuit, and the pulse wave signal B is generated by the B1 and B2 signals of the delay circuit B12. At the back end of the delay circuit. . The pulse wave signals A and B are controlled by resetting / setting in the delay time / inverter of the working conversion circuit 14 and generate _out Q. At this time, the delay time of the set signal B from the serially connected dynode components is provided so that it has a timing sequence (TUing). The round output power Q of the flip-flop (F / F) is pulled into the integrator 15 and the time ratios of "ΓM and" " 0 " which are converted to M output Q are changed to mold pressure VI. As shown in the fourth circle, the output VI of the integrator 15 is compared with the output V2 of the delay time setting voltage DAC 17 to generate a voltage NV cont that controls the delay time. The voltage NVcont from the delay time control unit 16 is to control the fall time of the delay circuit and other logic circuits 13 and to generate a voltage PVcont that is opposed to the NVcont and to control the rise time. Control the road 18 at the logic threshold. As shown in FIG. 5, the logic threshold voltage control circuit 18 is to generate a voltage PVcont. The circuit includes: a reference voltage generation circuit 181 to generate an intermediate value between the power source VDD and the power source VSS, and constitutes NVcont and PVcont. The voltage variation is proportional to the threshold value generating circuit 183, and M and M generate the intermediate voltage of the reference voltage generating circuit 181 which is the intermediate value of the two power sources, and generate the intermediate voltage 183 with the threshold value controlled by NVcont and PVcont. The voltage is _person voltage, and the threshold voltage control circuit for generating PVcont is 182 0. In the foregoing description, NVcont is generated in «delay time control unit 16". This paper uses the Chinese National Standard (CNS) A4 specification (210 × 29 " 7mm) (Please read the notes on the back before filling in this card) -Booking-Order A7 B7 V. Description of the invention (6) Please read the notes on the back of the book and fill in the pages, and then edit the page The threshold pressure control circuit 18 generates PVcont. However, the reverse method is also possible. The M delay time control unit 16 generates PVcont, and the logic threshold value mold pressure control Xiaolu 18 generates NVcont. Fig. 6 shows a second embodiment of the present invention. In this circuit, the delay time / working conversion circuit 24 is a 20-round human clock signal via the urea wave generator, and a variable delay circuit A21 with a delay element connected in series is set, and the input signal is plotted in The reset terminal * 鸰 output signal is input to the setting terminal to form a flip-flop. The clock signal is fed into the variable delay circuit A21 of the delay element connected to the serial pin by PVcont and NVcont to control the delay time via the urea wave generator 20, and it is drawn into the delay time / working conversion circuit connected to the wheel exit The 24 reset reset input and reset input terminals of the flip-flop. The Q-round signal of this flip-flop is only a general album of the time when the variable delay mold A21 passes the pulse wave, and becomes a repeated signal with the same period as the clock signal, that is, the variable delay circuit The delay time of A21 becomes a signal that the duty cycle will change. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. (7) shows a third embodiment of the present invention. In this circuit, the delay time / working conversion path is a variable delay path B31 that is connected in series with the delay element and reverses the output to the input to form a ring oscillator (ring oscillator), and its rotation is A trigger generates a urea wave with a certain width, and turns II out of it into the integrator 15 to become a fixed pulse wave generator 32. The oscillation frequency of this ring oscillator is equivalent to the « The delay time is twice, and the pulse width of the vibration wave as a rising and falling action is inserted into a certain fixed urea wave generator 32, and a signal D with a constant urea wave width and a change in time is obtained. 。 Then, in compliance with the variable delay paper method, the Chinese National Standard (CN'S) A4 (210 × 297 mm) 10-10 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (Xiaolu B31 The delay time can make it a signal that the duty cycle changes. In this case, the timing sequence of the wheel-out C of the variable delay circuit B31 and the gun-out D of the fixed pulse wave generator 32 is shown in Fig. 8. Effects of the Invention: As described above, in the circuit with the delay time of the CMOS gate to be constant, only simple additional circuits and low power consumption can be achieved. It also has the delay required to achieve the required accuracy. The effect of the delay time control circuit of the time signal. Brief description of the drawing Figure 1 is the circuit block of the present invention. Figure 2 is the basic circuit diagram of the inverter of the present invention and its timing circle (timing diagro · ). Fig. 3 is a timing diagram of the circuit of the present invention. Fig. 4 is a circuit circle showing an example of the delay time control unit of the present invention. Fig. 5 is an example of the general threshold voltage control circuit of the present invention. Figure 6 shows the circuit block diagram of the second embodiment of the present invention. Figure 7 shows the circuit diagram of the third embodiment of the present invention. Figure 8 shows the circuit of the third embodiment of the present invention. Timing chart. This paper size is applicable to China National Standard (CNS) A4 specification (21Ό × 297 mm) --------- 1 · Installation ------ Order -------- ^ ^ (please first (Read the notes on the back and fill out this page) -T 1-11