JP3703880B2 - Delay time control circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a delay time control circuit that can obtain an accurate delay time signal with a simple additional circuit and low power consumption in a circuit that keeps the delay time of a CMOS gate constant.
[0002]
[Prior art]
The delay time of the CMOS gate changes due to a change in power supply voltage or a change in element temperature caused by a change in power consumption. On the other hand, in the VLSI test system, it is necessary to keep the delay time constant in order to generate an accurate timing signal by a circuit that generates the timing signal.
For this reason, in order to stabilize the delay time, there are the following circuits as conventional techniques.
(1) Using the relationship between the delay time of the CMOS gate and the temperature, the delay time of the CMOS gate is detected and the heat generation circuit in the LSI is controlled.
(2) Utilizing the relationship in which the heat generation amount is proportional to the frequency, the operation frequency of the circuit is always maintained at a constant value as a whole, so that the heat generation amount is kept constant and the delay time of the CMOS gate is kept constant.
(3) Utilizing the relationship between the delay time of the CMOS gate and the power supply voltage, the delay time of the CMOS gate is detected and the power supply voltage of the LSI is controlled.
[0003]
[Problems to be solved by the invention]
In the circuits (1) and (2), the power consumption of the CMOS becomes a constant value, so that the power consumption cannot be reduced. In addition, the additional circuit becomes large. For example, in (1), a delay time detection circuit and a heating cell are added. In (2), a dummy circuit that operates complementarily to the operation circuit is added.
In the circuit (3), since the potential drop of the power supply voltage generation circuit is compensated, the power supply voltage of the entire circuit is increased and the power consumption is increased.
Any of the methods (1) to (3) can maintain a constant delay time. However, in order to control the delay time per gate such as 100 ps / gate or 200 ps / gate, another method is available. is necessary.
For example, since the change in the delay time due to the power supply voltage in (3) is not so large, the delay time including the difference in the delay time due to the variation in the elements and the difference in the delay time due to the temperature change due to the change in the operating frequency is set. In order to keep the circuit constant, it is necessary to use a plurality of delay time control means such as a method of changing the delay time by changing the capacitance of the output terminal of the CMOS gate, which increases the circuit scale.
It is an object of the present invention to realize a delay time control circuit that can obtain an accurate delay time signal with a simple additional circuit and low power consumption in a circuit that keeps the delay time of a CMOS gate constant. .
[0004]
[Means for Solving the Problems]
In order to achieve the above object, the delay time control circuit of the present invention is configured as follows.
In other words, a front-end delay circuit A11 and a rear-end delay circuit B12 are provided in a delay circuit in which a pulse having a constant cycle is input and delay cells are connected in series, and reset by the pulse A generated by the delay circuit A11. A delay time / duty conversion circuit 14 composed of a flip-flop set by the generated pulse B is provided, an integrator 15 for converting the duty into a voltage level signal is provided, and the delay time of the delay circuit is controlled so that the duty becomes constant. A delay time control unit 16 is provided, a delay time setting voltage DAC 17 for adjusting a set value of the delay time is provided, and a logical threshold voltage control for generating another delay control voltage from the delay control voltage of the delay time control unit 16 A logic which is a general circuit in an IC provided with a circuit 18 and whose delay time is controlled by a delay control voltage The road 13 is provided.
[0005]
The delay time control unit 16 is provided with a circuit that compares the output V1 of the integrator 15 with the output V2 of the delay time setting voltage DAC 17 and generates a voltage for controlling the delay time.
The logic threshold voltage control circuit 18 includes a reference voltage generation circuit 181 that generates an intermediate value between the power supply VDD and the power supply VSS, and includes a threshold generation circuit 183 that is configured such that NVcont and PVcont vary in voltage symmetrically. A threshold voltage for generating a PVcont by inputting an intermediate voltage of a reference voltage generation circuit 181 that generates an intermediate value of both power supplies and an intermediate voltage of a threshold generation circuit 183 controlled by NVcont and PVcont. A control circuit 182 is provided.
[0006]
The delay time / duty conversion circuit 24 is provided with a variable delay circuit A21 in which a clock signal is input via the pulse generator 20, and delay cells are connected in series, and an input signal of the variable delay circuit A21 is input to a reset terminal. The flip-flop is configured by inputting an output signal to the set terminal.
Alternatively, as a delay time / duty conversion circuit, there is provided a variable delay circuit B31 constituting a ring oscillator in which delay cells are connected in series, the output is inverted and connected to the input, and the output of the variable delay circuit B31 is used as a trigger. A fixed pulse generator 32 for generating a pulse having a constant width and inputting the output to the integrator 15 is provided.
[0007]
[Action]
In the delay time control circuit configured as described above, a circuit that keeps the delay time of the CMOS gate constant can be realized with a simple additional circuit and with low power consumption. Also, there is an effect of realizing a delay time control circuit that can be obtained by specifying an accurate delay time signal.
[0008]
【Example】
FIG. 1 shows a block diagram of an embodiment of the present invention. This circuit is reset by the front-end delay circuit A11 and the rear-end delay circuit B12 among the delay circuits connected in series that receive and delay pulses of a constant period, and the pulse A generated by the delay circuit A11. The delay time / duty conversion circuit 14 composed of a flip-flop set by the pulse B generated by the above, an integrator 15 for converting the duty into a voltage level signal, and a delay for controlling the delay time of the delay circuit so that the duty becomes constant. Logic threshold voltage control circuit for generating another delay control voltage PVcont from the time control unit 16, the delay time setting voltage DAC17 for adjusting the set value of the delay time, and the delay control voltage NVcont of the delay time control unit 16 18 is a general circuit in an IC whose delay time is controlled by a delay control voltage. Constituted by the management circuit 13.
[0009]
FIG. 2A is an inverter circuit of a circuit used for the delay circuit A11, the delay circuit B12, and the logic circuit 13 which is a general circuit, and the delay time is controlled by the gate voltages PVcont and NVcont of Q3 and Q4. .
FIG. 2B shows operation waveforms of the inverter circuit of FIG. The resistance values of Q3 and Q4 are variable depending on the gate voltage, and the delay amount is variable depending on the stray capacitance of the output terminal OUT, so that the delay control by the gate voltage is possible.
[0010]
FIG. 3 shows the operation of the circuit shown in FIG. The delay circuit A11 and the delay circuit B12 are cascaded gates that propagate pulse inputs having a fixed period, and the delay time is controlled by the gate voltages PVcont and NVcont as shown in FIG.
First, a pulse signal A is generated by the A1 signal and A2 signal of the delay circuit A11 at the front end of the delay circuit, and a pulse signal B is generated by the B1 signal and B2 signal of the delay circuit B12 at the rear end of the delay circuit. .
The pulse signal A and the pulse signal B reset / set the flip-flop (F / F) in the delay time / duty conversion circuit 14 to generate an output Q. At this time, the timing of the set signal B varies depending on the delay time of the cascaded gate row.
[0011]
The output Q of the F / F is input to the integrator 15 and converted into a voltage V1 that changes depending on the time ratio of “1” and “0” of the output Q.
As shown in FIG. 4, the output V1 of the integrator 15 is compared with the output V2 of the delay time setting voltage DAC17 to generate a voltage NVcont that controls the delay time.
[0012]
The voltage NVcont output from the delay time control unit 16 controls the fall time of the delay circuit and other logic circuits 13, and generates a voltage PVcont that controls the rise time corresponding to NVcont. Input to the voltage control circuit 18.
[0013]
As shown in FIG. 5, the logic threshold voltage control circuit 18 is configured such that the reference voltage generation circuit 181 that generates an intermediate value between the power supply VDD and the power supply VSS, and the NVcont and PVcont have voltage fluctuations symmetrically. The threshold value generation circuit 183 receives the intermediate voltage of the reference voltage generation circuit 181 that generates an intermediate value of both power supplies and the intermediate voltage of the threshold value generation circuit 183 controlled by NVcont and PVcont, and generates PVcont. The threshold voltage control circuit 182 generates a voltage PVcont.
[0014]
In the above description, the delay time control unit 16 generates NVcont and the logic threshold voltage control circuit 18 generates PVcont. Conversely, the delay time control unit 16 generates PVcont, The threshold voltage control circuit 18 may generate NVcont.
[0015]
FIG. 6 shows another embodiment of the present invention. In this circuit, the delay time / duty conversion circuit 24 is provided with a variable delay circuit A21 in which a clock signal is input via a pulse generator 20, delay cells are connected in series, and an input signal of the variable delay circuit A21 is received. It consists of a flip-flop that is input to the reset terminal and the output signal is input to the set terminal.
The clock signal is connected via a pulse generator 20 to the input of a variable delay circuit A21 in which delay cells whose delay time can be controlled by PVcont and NVcont are connected in cascade. The input and output of the variable delay circuit A21 are connected to the reset input and set input of the set reset flip-flop of the delay time / duty conversion circuit 24. The Q output signal of this flip-flop is a repetitive signal having the logic of “L” for the time during which the pulse passes through the variable delay circuit A21 and having a period equal to that of the clock signal. That is, the signal changes in duty cycle according to the delay time of the variable delay circuit A21.
[0016]
FIG. 7 shows still another embodiment of the present invention. In this circuit, as a delay time / duty conversion circuit, there is provided a variable delay circuit B31 constituting a ring oscillator in which delay cells are connected in series, an output is inverted and connected to an input, and an output of the variable delay circuit B31 is provided. Is used as a trigger to generate a fixed-width pulse, and a fixed pulse generator 32 for inputting the output to the integrator 15 is provided.
The oscillation period of this ring oscillator corresponds to twice the delay time of the variable delay circuit B31. By inputting this oscillation output to the fixed pulse generator 32 having a constant pulse width that operates at the rising edge or the falling edge, a signal D whose pulse width is constant and whose period changes is obtained. That is, the signal changes in duty cycle according to the delay time of the variable delay circuit B31.
FIG. 8 shows the timing relationship between the output C of the variable delay circuit B31 and the output D of the fixed pulse generator 32 in this case.
[0017]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
That is, a circuit that keeps the delay time of the CMOS gate constant can be realized with a simple additional circuit and with low power consumption. Further, there is an effect of realizing a delay time control circuit that can be obtained by designating an accurate delay time signal.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of the present invention.
FIG. 2 is a basic circuit diagram and timing diagram of an inverter according to the present invention.
FIG. 3 is a timing diagram of the circuit of the present invention.
FIG. 4 is a circuit diagram showing an example of a delay time control unit of the present invention.
FIG. 5 is a circuit diagram showing an example of a logical threshold voltage control circuit of the present invention.
FIG. 6 is a circuit block diagram showing another embodiment of the present invention.
FIG. 7 is a circuit block diagram showing still another embodiment of the present invention.
FIG. 8 is a timing chart in the circuit shown in FIG.
[Explanation of symbols]
11 Delay circuit A
12 Delay circuit B
13 logic circuits 14 and 24 delay time / duty conversion circuit 15 integrator 16 delay time control unit 17 delay time setting voltage DAC
18 logic threshold voltage control circuit 20 pulse generator 21 variable delay circuit A
31 Variable delay circuit B
32 Fixed pulse generator

Claims (4)

A delay circuit A (11) and a rear-end delay circuit B (12) are provided among delay circuits in which pulses having a constant period are inputted and delay cells are connected in series,
A delay time / duty conversion circuit (14) comprising a flip-flop reset by a pulse A generated by a delay circuit A (11) and set by a pulse B generated by a delay circuit B (12);
An integrator (15) for converting the duty into a voltage level signal;
A delay time control unit (16) for controlling the delay time of the delay circuit so that the duty is constant is provided,
A delay time setting voltage DAC (17) for adjusting a set value of the delay time is provided;
A logic threshold voltage control circuit (18) for generating another delay control voltage from the delay control voltage of the delay time control unit (16);
A logic circuit (13), which is a general circuit in an IC whose delay time is controlled by a delay control voltage, is provided.
A delay time control circuit.   The delay time control unit (16) includes a circuit that compares the output V1 of the integrator (15) with the output V2 of the delay time setting voltage DAC (17) and generates a voltage for controlling the delay time. The delay time control circuit according to claim 1. The logic threshold voltage control circuit (18) includes a reference voltage generation circuit (181) that generates an intermediate value between the power supply VDD and the power supply VSS.
Provided is a threshold value generation circuit (183) configured such that NVcont and PVcont have voltage fluctuations symmetrically;
Threshold for generating PVcont by using as input the intermediate voltage of the reference voltage generating circuit (181) that generates an intermediate value of both power supplies and the intermediate voltage of the threshold generating circuit (183) controlled by NVcont and PVcont. 3. The delay time control circuit according to claim 1, further comprising a value voltage control circuit (182). The delay time / duty conversion circuit (24) is provided with a variable delay circuit A (21) in which a clock signal is input via a pulse generator (20) and delay cells are connected in series.
4. A flip-flop comprising an input signal of the variable delay circuit A (21) input to a reset terminal and an output signal input to a set terminal, and comprising at least one of claim 1, 2, and 3 The delay time control circuit described in 1.

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