}Γ 五、發明説明（/) 發明領域： 本發明是關於一種半導體積體電路(Integrated Circuit ; 1C)的製造方法，特別是有關於場效電晶體(Field Effect Transistor ; FET)中複晶矽與金屬接觸窗的製造方法 (method) ° 發明背景： 半導體場效電晶體(FET)電路中，爲了連接不同元件層 次之目的，則必須透過接觸窗來達成。然而，在現今半導體 工業致力於縮小元件尺寸以提升半導體電路上之元件密度， 並改善元件的工作速度以降低其生產成本的同睁，於半導體 積體電路的製程以及元件的物理特性等各方面都會使接觸窗 的準確度與再現性(reproduction)控制的能力受到影響。 經濟部中央作龙馬貝工消资合作社印装 現請參閱圖一及圖二，以說明習知的複晶矽接觸窗製造 方法。圖一中所不爲傳統的自行對準(self-aligned)複晶砂接 觸窗的佈局圖(layout)，按照電路設計準則(circuit design rule)，接觸窗(2)(其大小爲2 λ X 2 λ )的長度及寬度與金屬線 (6)(寬爲2 λ )、複晶矽(4)(寬爲2 λ )的寬度相同，但接觸窗與 相鄰元件之間仍需有1 λ的距離，亦即爲圖一虛線部分之接 觸窗延伸區(8)(Contact Extension)，因此也限制了積體電路 元件的集積密度(packing density)。接著，請參閱圖二，係爲 圖一延著AA'方向的剖面圖(cross section)。其中複晶砂(4)係 沈積於場氧化層(1〇)(FOX)之上，接著在複晶矽(4)上分別覆 蓋絕緣的TEOS二氧化矽(12)、氮化矽(14)、硼磷攙雜玻璃 (BPSG)(16)等介電層，然後，再用微影及蝕刻技術以形成金 表紙張尺度適用中國國家標隼（CNS )八4叱格（、} Γ V. Description of the Invention (/) Field of the Invention: The present invention relates to a method for manufacturing a semiconductor integrated circuit (Integrated Circuit; 1C), and more particularly, to a polycrystalline silicon in a Field Effect Transistor (FET). Method for manufacturing contact window with metal ° Background of the invention: In the field effect transistor (FET) circuit, in order to connect different element levels, it must be achieved through the contact window. However, in the current semiconductor industry, efforts are being made to reduce the size of components to increase the density of components on semiconductor circuits, and to improve the working speed of components to reduce their production costs. In terms of semiconductor integrated circuit manufacturing processes and the physical characteristics of components, etc. Both affect the accuracy and reproduction control of the contact window. Printed by the Central Ministry of Economic Affairs, Long Mabei Industrial Cooperative, please refer to Figures 1 and 2 to illustrate the conventional method of manufacturing polycrystalline silicon contact windows. Figure 1 does not show the layout of a traditional self-aligned polycrystalline sand contact window. According to the circuit design rule, the contact window (2) (its size is 2 λ X 2 λ) have the same length and width as the metal wire (6) (width 2 λ) and polycrystalline silicon (4) (width 2 λ), but there still needs to be 1 λ between the contact window and adjacent components The distance is the contact extension (8) (Contact Extension) of the dashed part in Figure 1, so it also limits the packing density of integrated circuit components. Next, please refer to FIG. 2, which is a cross section extending along AA ′ direction in FIG. 1. The polycrystalline sand (4) is deposited on the field oxide layer (10) (FOX), and then the polycrystalline silicon (4) is covered with insulating TEOS silicon dioxide (12) and silicon nitride (14), respectively. Dielectric layers such as boro-phosphorus doped glass (BPSG) (16), and then lithography and etching techniques are used to form gold watch paper. The size of the paper is applicable to the Chinese National Standard (CNS) of 8 4 grid (,
五、發明説明（y) 經濟部中央標準局員工消費合作社印製 屬與複晶矽接觸窗(2)的位置以及縱向的複晶矽線，接著， 沈積一層金屬，最後再利用蝕刻方式，去掉不必要的金屬部 分，以構成橫向的金屬線。傳統佈局方式之金屬蝕刻步驟必 須分二階段進行，首先以電漿蝕刻法運行，但是反應氣體中 的氯氣(Cl2)，同時也會以相同速率蝕刻掉複晶矽，因此在接 近蝕刻金屬反應終點時，就需改以溼蝕刻方式來進行蝕刻金 屬’然而該溼蝕刻方式容易造成金屬(26)線寬不易控制，以 及製程複雜化。所以，如何改進上述複晶矽接觸窗之缺點， 就成爲半導體工業的一個重要的課題了。 發明的簡要說明： . 本發明之主要目的爲一種場效電晶體中複晶矽與金屬接 觸窗(contact window)的製造方法(method)。 本發明之次一目的爲提供一種場效電晶體中改進複晶矽 容易斷路問題的製造方法，以提升產品的良率。 本發明之另一目的爲提供一種場效電晶體中複晶體與金 屬接觸窗的製造方法，在蝕刻的製程中，可減少一道溼蝕刻 的步驟，提升產品的產能(through put)。 本發明係利用以下之製程步驟，以達成上述之目的。首先， 係在矽基板上形成一場氧化層，接著，在場氧化層之上連續 沈積形成複晶矽膜以及第一介電層。接下來的步驟，係爲本 發明之精義所在，先利用微影及蝕刻的方法，將複晶矽膜上 方的第一介電層打開一個開口寬度較複晶矽及金屬線寬爲小 的接觸窗，再進行第二次微影及蝕刻的步驟，將複晶矽膜形 成二條縱向的複晶矽線，其間係以複晶矽襯墊相連接，以構 3 (請乇閱請背面之.';i意事項再填巧本頁) •丨%.V. Description of the invention (y) The employee's cooperative of the Central Standards Bureau of the Ministry of Economic Affairs prints the position of the contact window (2) with the polycrystalline silicon and the vertical polycrystalline silicon line, then deposits a layer of metal, and finally uses the etching method to remove Unnecessary metal parts to form horizontal metal wires. The traditional layout of the metal etching step must be performed in two stages. First, the plasma etching method is used, but the chlorine gas (Cl2) in the reaction gas will also etch away the polycrystalline silicon at the same rate, so it is near the end of the etching metal reaction. In this case, it is necessary to change the wet etching method to etch the metal. However, the wet etching method easily causes the line width of the metal (26) to be difficult to control and the process to be complicated. Therefore, how to improve the shortcomings of the above-mentioned polycrystalline silicon contact window has become an important subject for the semiconductor industry. Brief description of the invention: The main object of the present invention is a method for manufacturing a compound crystal silicon-metal contact window in a field effect transistor. A secondary object of the present invention is to provide a manufacturing method for improving the problem of easy disconnection of a polycrystalline silicon in a field effect transistor to improve the yield of a product. Another object of the present invention is to provide a method for manufacturing a complex crystal and a metal contact window in a field effect transistor. In the etching process, a wet etching step can be reduced and the throughput of the product can be improved. The present invention utilizes the following process steps to achieve the above purpose. First, a field oxide layer is formed on a silicon substrate, and then a polycrystalline silicon film and a first dielectric layer are continuously deposited on the field oxide layer. The next steps are the essence of the present invention. First, using lithography and etching, the first dielectric layer above the polycrystalline silicon film is opened to a contact having a width smaller than that of the polycrystalline silicon and the metal line. Window, and then perform the second lithography and etching steps to form the polycrystalline silicon film into two longitudinal polycrystalline silicon lines, which are connected by a polycrystalline silicon liner in order to construct 3 (please read the back of it. '; I will fill in this page again if you want to know) • 丨%.
、1T 本紙張尺度適用中國國家標準（CNS M4規格（210X297公釐）、 1T This paper size applies to Chinese national standard (CNS M4 specification (210X297 mm)
五、發明説明（)） 成複晶矽導通路徑。然後，再沈積第二介電層與第三介電層 於複晶矽線之上，以防止複晶矽與金屬在接觸窗之外有電性 接觸。最後，沈積金屬膜，再利用微影及蝕刻的方法，形成 一條橫向的金屬線，完全覆蓋於接觸窗內的複晶矽上，如 此，就能解決複晶矽容易斷路的問題了。同時，因爲金屬完 全覆蓋於複晶矽之上，在蝕刻金屬的過程中，也就可以節省 了一道爲了避免傷害複晶矽而必須再進行的溼蝕刻之步4。 附圖之簡要說明： 圖一爲習知的複晶砂接觸窗之佈局(layout)圖。 圓一爲習知的複晶砂接觸窗之剖面(cross section)圖。 圖三爲本發明複晶矽接觸窗之佈局圖。 圖四至圖八爲本發明複晶矽接觸窗實施例之製程剖面 —,1---------策------訂 <請先閱讀背面之注意事項再填$大*頁) 經濟部中央標隼局員工消費合作社印«. 圖。 圖號說明： 2-接觸窗 4-複晶矽 6-金屬線 8_接觸窗延伸區 10-場氧化層 12-TE0S 二氧化 ft 14-氮化矽 16-硼磷攙雜玻璃 21-半導體矽基板 22-接觸窗 24-複晶矽膜 26-金屬線 28-複晶矽襯墊 30-場氧化層 32-第一介電層 34-第二介電層 36-第三介電層 37-光阻膜 發明之詳細說明： _ 4 本紙乐尺度適用中國國家樣準（CNS ) A4規格（2】OX 297公釐）V. Description of the invention ()) A multi-crystalline silicon conduction path. Then, a second dielectric layer and a third dielectric layer are deposited on the polycrystalline silicon line to prevent the polycrystalline silicon and the metal from making electrical contact outside the contact window. Finally, a metal film is deposited, and then a lithographic and etching method is used to form a horizontal metal line that completely covers the polycrystalline silicon in the contact window. In this way, the problem of easy disconnection of the polycrystalline silicon can be solved. At the same time, because the metal is completely covered on the polycrystalline silicon, in the process of etching the metal, a wet etching step 4 that must be performed in order to avoid damaging the polycrystalline silicon can be saved4. Brief description of the drawings: FIG. 1 is a layout diagram of a conventional polycrystalline sand contact window. Circle one is a cross section view of a conventional polycrystalline sand contact window. FIG. 3 is a layout diagram of a polycrystalline silicon contact window according to the present invention. Figures 4 to 8 are process cross sections of the embodiment of the polycrystalline silicon contact window according to the present invention. --------------------- Order & Please read the precautions on the back before filling (* Page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. Description of drawing number: 2-contact window 4-polycrystalline silicon 6-metal wire 8_contact window extension area 10-field oxide layer 12-TE0S dioxide ft 14-silicon nitride 16-borophosphorus doped glass 21-semiconductor silicon substrate 22-contact window 24-polycrystalline silicon film 26-metal wire 28-polycrystalline silicon pad 30-field oxide layer 32-first dielectric layer 34-second dielectric layer 36-third dielectric layer 37-light Detailed description of the invention of the barrier film: _ 4 This paper scale is applicable to China National Standard (CNS) A4 specifications (2) OX 297 mm
經濟部中央樓準局員工消費合作社印製 五、發明説明（p) 以下以形成超大型積體電路(VLSI)之複晶矽與金屬接觸 窗的實施例，來說明本發明之方法。 現請參閱圖三，爲本發明複晶矽接觸窗的佈局圖，與圖 一傳統方式不同之處在於’在沈積複晶矽膜之後，先在複晶 矽上方打開一寬度較金屬線寬爲小的接觸窗(contact window)(22)(1.2 λ X 1.2 λ )，再利用微影及蝕刻技術形成二 條縱向的複晶矽線(24)加上一複晶矽襯墊(polysilicon pad)(28)，其中該複晶矽襯墊(28)係連接該二條縱向之複晶 矽線(24)以構成複晶矽導通路徑(conduction path)，兩條複晶 矽線之間的距離爲1.2 λ，最後再形成橫向的屬線(26)(2 λ)，如此金屬線(26)就能完全覆蓋住接觸窗內的複晶矽之 上，可解決複晶矽易斷路的問題。 圖四至圖八爲本發明複晶矽接觸窗實施例之製程，係爲 沿著圖三CC’方向的剖面圖，以下將詳細說明，以使貴審 查委員進一步明瞭本發明之精義。 首先，請參閱圖四，在半導體矽基板(21)上，長出一場 氧化層(30)(field oxide ; FOX)，其厚度係介於4000至10000 埃之間。接著，在所述場氧化層(30)之上，沈積一層複晶矽 膜(24)，所述複晶矽膜(24)，通常是利用同步磷攙雜(in-situ phosphorus doped)之低壓化學氣相沈積法(LPCVD)形成，其 反應氣體是(15%PH3+85%SiH4)與(5%PH3+95%N2)之混合氣 體，反應溫度約爲550°C，其厚度介於1000至4000埃之間， 主要係根據接觸窗的尺寸大小來決定。 _ 5 本紙張尺度適用中國國家標準（〇^)^4規格（210'/ 297公釐) I /^1 — —^^1« ^mB I —·8· m^— HI— \ ί ·νό (請先閱讀背面之注意事項再填芎本頁)Printed by the Consumers' Cooperative of the Central Bureau of the Ministry of Economic Affairs of the People's Republic of China 5. Description of the Invention (p) The following is a description of the method of the present invention by forming an example of a polycrystalline silicon and metal contact window of a very large scale integrated circuit (VLSI). Please refer to FIG. 3 for the layout of the polycrystalline silicon contact window according to the present invention. The difference from the traditional method of FIG. 1 is that after the deposition of the polycrystalline silicon film, first open a width above the polycrystalline silicon. Small contact window (22) (1.2 λ X 1.2 λ), and then using lithography and etching technology to form two vertical polycrystalline silicon lines (24) plus a polysilicon pad ( 28), wherein the polycrystalline silicon pad (28) is connected to the two longitudinal polycrystalline silicon wires (24) to form a polycrystalline silicon conduction path, and the distance between the two polycrystalline silicon wires is 1.2 λ, and finally form a lateral belonging line (26) (2 λ), so that the metal line (26) can completely cover the polycrystalline silicon in the contact window, which can solve the problem that the polycrystalline silicon is easily broken. Figures 4 to 8 show the process of the embodiment of the polycrystalline silicon contact window of the present invention, which is a cross-sectional view taken along the CC 'direction of Figure 3, which will be described in detail below to make your reviewing members understand the essence of the present invention. First, referring to FIG. 4, a field oxide (FOX) layer (30) is grown on the semiconductor silicon substrate (21), and the thickness is between 4000 and 10,000 Angstroms. Next, a layer of a polycrystalline silicon film (24) is deposited on the field oxide layer (30). The polycrystalline silicon film (24) is usually a low-pressure chemistry using in-situ phosphorus doped. Formed by vapor deposition (LPCVD), the reaction gas is a mixed gas of (15% PH3 + 85% SiH4) and (5% PH3 + 95% N2), the reaction temperature is about 550 ° C, and the thickness is between 1000 and Between 4000 angstroms, it is mainly determined according to the size of the contact window. _ 5 This paper size applies Chinese national standard (〇 ^) ^ 4 specifications (210 '/ 297 mm) I / ^ 1 — — ^^ 1 «^ mB I — · 8 · m ^ — HI— \ ί · νό (Please read the notes on the back before filling this page)
經濟部中央堞準局員工消费合作社印製 五、發明説明（f) 請參閱圖五A，係先覆蓋一層第一介電層(32)絕緣層於 所述複晶矽膜(24)之上。所述第一介電層(32)通常是利用低 壓化學氣相沈積法形成之TEOS二氧化矽，其反應氣體是矽 甲烷或四乙基矽酸鹽(TEOS)，反應溫度約爲650〜750°C ’ 反應壓力介於0.1到1.0 Torr，其厚度介於1000到3000埃之 間。接著進行微影及蝕刻之技術於所述第一介電層(32)上， 以形成複晶矽之接觸窗(22)，而形成改良後之複晶矽圖形， 爲一條複晶矽線(24)，其間係由一複晶襯墊(28)(pad)相連 接，如圖五B所示。 請參閱圖六，首先，連續沈積一薄的第二介電層(34)以 及一第三介電層(36)二絕緣層於所述接觸窗(22)與第一介電 層(32)上。所述第二介電層(34)，通常是利用低壓化學氣相 沈積法形成之氮化矽，其反應氣體爲SiCl2H2和NH32混合氣 體，其反應溫度介於650到750°C之間，反應壓力大約爲0.25 Torr，其厚度介於300到1000埃之間。而所述第三介電層(36) 之硼磷攙雜玻璃膜(BPSG)通常是利用大氣壓化學相沈積法 (APCVD)形成，其反應壓力約爲1 Torr，反應溫度約400°C， 反應氣體是Si(C2H50)4、丁1^與!^2之混合氣體，其厚度介於 6000至10000埃之間，並在920°C環境下進行熱整流(Thermal Flow)以平坦化所述之硼磷攙雜玻璃(BPSG)。 接著請參閱圖七，再覆蓋一層光阻膜(37)於所述第二介 電層(34)及第三介電層(36)之上，並利用微影及電漿蝕刻技 術，製定出接觸窗延伸區之圖案。其中所述第二介電層(34) 和第三介電層(36)之電漿蝕刻，可以利用磁場增強式活性離 __6 本紙張尺度適5中國國家標準（CNS ) A4規格（210:297公釐） I 11 /於 I ii- (請先閲讀背面之注意窜.項再填芎本頁) 經濟部中央燥隼局員工消費合作社印製 五'發明説明（έ) 子電漿蝕刻技術(MERIE)或電子迴旋共振電漿蝕刻技術(ECR) 或傳統的活性離子式電漿蝕刻技術(RIE)予以完成，其反應 氣體通常是CF4、CHF3、02以及Ar。 最後，請參閱圖八，係爲本發明複晶矽接觸窗之完成結 構的剖面圖。係爲先沈積一層金屬膜(26)在所述接觸窗(22) 之上，所述金屬膜(26)可爲鋁(A1)或99%Al+l%Si合金或 95%Al+l%Si+4%Cu合金等材料，其厚度約爲5000到12000 埃之間。然後再利用微影及蝕刻技術，去掉不必要的鋁金屬 部分以形成金屬線，如圖八所示。金屬蝕刻通常係利用電漿 蝕刻法進行。其反應氣體可用Cl2、BC13、CFi及CHF3等氣 體，反應溫度介於60至100°C之間，金屬蝕刻之後，即完成 本發明複晶矽接觸窗的製作了。 本發明之實施例具有以下之優點： 第一：改良了複晶矽接觸窗的佈局方式，使得金屬整 個覆蓋住接觸窗內的複晶矽，有效地避免了複 晶矽在金屬蝕刻步驟中造成斷路的可能，提升 了產品的良率(yield)。 第二：因爲金屬整個覆蓋住接觸窗的複晶矽，所以在 蝕刻過程中，可省去爲避免傷害複晶矽而必須 再進行一溼蝕刻之步驟，可減少製程的步驟， 進而增加產品的產能。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明之範圍，而且熟知半導體技藝人士皆能明瞭，適當而 m^— vm n^— . In— nnf 1.1^ I tl^^i TJ *-'tv (請"閱讀背面之.注意事項再填寫本I > 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） B" 五、發明説明（y ) 作些微的改變及調整，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍。 8 本纸張尺度適用中國國家標準（CNS ) Λ4叹诂<Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 5. Description of the invention (f) Please refer to Figure 5A, which is covered with a first dielectric layer (32) and an insulating layer on the polycrystalline silicon film (24). . The first dielectric layer (32) is usually TEOS silicon dioxide formed by a low-pressure chemical vapor deposition method. The reaction gas is silane or tetraethyl silicate (TEOS), and the reaction temperature is about 650 to 750. ° C 'The reaction pressure is between 0.1 and 1.0 Torr and its thickness is between 1000 and 3000 Angstroms. Next, a technique of lithography and etching is performed on the first dielectric layer (32) to form a contact window (22) of polycrystalline silicon, and a modified polycrystalline silicon pattern is formed as a polycrystalline silicon line ( 24), which is connected by a polycrystalline pad (28) (pad), as shown in FIG. 5B. Please refer to FIG. 6. First, a thin second dielectric layer (34) and a third dielectric layer (36) and two insulating layers are successively deposited on the contact window (22) and the first dielectric layer (32). on. The second dielectric layer (34) is usually silicon nitride formed by a low-pressure chemical vapor deposition method. The reaction gas is a mixed gas of SiCl2H2 and NH32. The reaction temperature is between 650 and 750 ° C. The pressure is about 0.25 Torr and its thickness is between 300 and 1000 Angstroms. The boron-phosphorus doped glass film (BPSG) of the third dielectric layer (36) is usually formed by atmospheric pressure chemical phase deposition (APCVD), and the reaction pressure is about 1 Torr, the reaction temperature is about 400 ° C, and the reaction gas is It is a mixed gas of Si (C2H50) 4, Ding1 ^ and! ^ 2, its thickness is between 6000 and 10,000 Angstroms, and the thermal flow is performed at 920 ° C to flatten the boron. Phosphorous doped glass (BPSG). Referring to FIG. 7, a photoresist film (37) is covered on the second dielectric layer (34) and the third dielectric layer (36), and the photolithography and plasma etching techniques are used to formulate The pattern of the contact window extension. Wherein, the plasma etching of the second dielectric layer (34) and the third dielectric layer (36) can utilize magnetic field-enhanced active ionization__6 This paper is suitable for 5 Chinese National Standards (CNS) A4 specifications (210: 297 mm) I 11 / Yu I ii- (please read the note on the back. Please fill in this page first) Print the 5 'invention description printed by the staff consumer cooperative of the Central Bureau of Economic Affairs of the Ministry of Economics (（) Plasma etching technology (MERIE) or electron cyclotron resonance plasma etching technology (ECR) or traditional reactive ion plasma etching technology (RIE). The reaction gases are usually CF4, CHF3, 02, and Ar. Finally, please refer to FIG. 8, which is a sectional view of the completed structure of the polycrystalline silicon contact window of the present invention. A metal film (26) is first deposited on the contact window (22). The metal film (26) may be aluminum (A1) or 99% Al + l% Si alloy or 95% Al + l% Materials such as Si + 4% Cu alloy have a thickness of about 5000 to 12000 Angstroms. Then use lithography and etching technology to remove unnecessary aluminum metal parts to form metal lines, as shown in Figure 8. Metal etching is usually performed by plasma etching. The reaction gas can be Cl2, BC13, CFi, and CHF3. The reaction temperature is between 60 and 100 ° C. After the metal is etched, the production of the polycrystalline silicon contact window of the present invention is completed. The embodiments of the present invention have the following advantages: First: The layout of the polycrystalline silicon contact window is improved, so that the entire metal is covered by the polycrystalline silicon in the contact window, which effectively prevents polycrystalline silicon from being caused during the metal etching step. The possibility of disconnection improves the yield of the product. Second: Because the metal covers the polycrystalline silicon of the contact window, during the etching process, a wet etching step must be performed to avoid damage to the polycrystalline silicon, which can reduce the process steps and increase the product's cost. Capacity. The above is a detailed description of the present invention by using preferred embodiments, but not limiting the scope of the present invention, and those skilled in the art of semiconductors will understand that it is appropriate and m ^ — vm n ^ —. In— nnf 1.1 ^ I tl ^^ i TJ *-'tv (Please " Read the back. Note and fill in this I > This paper size uses Chinese National Standard (CNS) A4 specification (210X297mm) B " V. Description of Invention (y)) Minor changes and adjustments will still not lose the essence of the present invention, nor deviate from the spirit and scope of the present invention. 8 This paper size applies the Chinese National Standard (CNS)