A7 、發明説明（ <發明之範圍> 製造本方微小化«合式晶片排容⑻器及其 <發明之背景> 之描诫 傳統以厚膜印刷燒結製 裝 如第1圖所示，其作法為在基層t片阻）器單元乃 製作底電極2，Q θ上以厚臊印刷燒結製程 电位2，泛面電極3，介電層4， 層6，保護層7與標示層8，赫人+電阻層5，上電極 之I作，此種以印機結製 减知電極 訂 列幾項特性： 侍之曰日片包谷（阻）器有下 列幾1電阻值之變化程度，或製程能力乃取決於下 Α.底電極層2，電阻層5，上 電極層6之印刷擴散情 經濟部中央標準局員工消費合作社印製 電阻層之印刷厚度變化(1 。 二層：層之材料特性嫩 D.上^⑽使電容，電阻值之變化有可能 5〇%或以上’而使製程良率不易控制。J20-2·由於需要考慮電極層印刷擴散情 以避免短路等現象’使上電極有效設計面積二= --- A7 A7 五 、發明説明（>) 況亦發生於電阻層。 由上述說明可以得知，如 程能力及增加有效零組件 。^缺點，以提昇製 又，習見晶片排“❼/為重要的課題。 所示，對於某些電路：二、二端配置’如第2圖 或層數’導致•件組裝密度;日力=外的佈局空間 度。例如第3A圖之低頻清 -次疋祜加PC版製造難 需如第3B圖’增加額外的:地線路二阻串接時， 才能滿足功能的需求。因此如何正確的導通孔， 板時，增加額外的二:之：發 究改良，經長期研⑼有本紅針對該缺失進行研 <發明之總論> 因此本發明旨在提供一種晶片。 方法以及晶片排容器端電極之正確配置^構益电極之製作 依本：明之此種晶片.排容阻上電極之 T係提”種以薄膜與微影_方法製作之上 方，，可解決厚膜印刷製程上之良率限制，同時由於採用 之缚膜製程具有精確尺寸控制之優點，可以減少佈局之 制’增加有效上電極面積’亦即對於同尺寸面積之_，（ 此種製程可穫得較大之電容值與較高之製程良率， 發明之另一目的。 ’ A7 B7 經濟部中央標準局負工消費合作社印製A7 、 Explanation of the invention (< Scope of invention > Manufacturing the local miniaturized «combined wafer discharge container and its < Background of invention > The method is to make the bottom electrode 2 on the base layer, and the device unit is to make the bottom electrode 2, and print the sintering process potential 2 on the Q θ with thick sintering. The surface electrode 3, the dielectric layer 4, the layer 6, the protective layer 7, and the labeling layer 8. , Heren + resistance layer 5, the upper electrode of I, this printing machine structure to reduce the knowledge of the electrode sets out several characteristics: Shi Zhiyue Japanese film package valley (resistor) device has the following 1 degree of resistance value change, Or the process capability depends on the printing thickness of the lower A. bottom electrode layer 2, resistance layer 5, and upper electrode layer 6. The printing thickness of the resistance layer printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (1. Second layer: layer of layer The material characteristics are tender D. The capacitors and resistance values may be changed by 50% or more, making the process yield rate difficult to control. J20-2 · Since the need to consider the electrode layer printing diffusion to avoid short circuits, etc. Effective design area of upper electrode 2 = --- A7 A7 V. Description of the invention (>) Occurs in the resistance layer. From the above description, it can be known that, such as the process capability and the increase of effective components. ^ Disadvantages to improve the system and the chip array "排 / is an important issue. As shown, for some circuits: Second, The two-end configuration 'as shown in Figure 2 or the number of layers' leads to • assembly density; daily force = external layout space. For example, the low-frequency clean-up of the PC version in Figure 3A is difficult to increase as shown in Figure 3B. Extra: Only when the two resistances of the ground line are connected in series, can the functional requirements be met. Therefore, how to add a correct via hole to the board, add an extra two: < Summary of the invention > Therefore, the present invention aims to provide a wafer. Method and correct arrangement of the end electrodes of the wafer row container ^ The fabrication of the structure electrode is based on such a wafer. The T-system of the drain-tolerant upper electrode The method of “improving” the film and lithography method can solve the yield limitation on the thick film printing process. At the same time, because the film binding process used has the advantage of precise size control, it can reduce the layout system. Electrode surface '_ I.e., for the same size of the area, (such a process is a further object of greater availability of high capacitance value of the process yield, invention.' A7 B7 Bureau of Standards negative economic working portion printed consumer cooperatives
.為月之剖面結構圖。 明之此種晶片排容端電極之兩種貫施配 五、發明説明（·) 依本發明之此種晶片排容上電極之端電極之配置結 構。系提供一種共地型排容之端電極配置結構，該種位於 晶片端共地電極之配置結構，將使客戶在製造PC板時，大 幅減少佈局產生之導通孔與層數，增加零組件置放密度與 減少PC的板製造成本，此為本發明之又一目的。 至於本發明之詳細結構、製作方法步驟，以及其他功 效與特徵，則參照下列依附圖所作之說明，即可得到完全 的了解： <圖示之簡單說明> 第1圖為習見之厚膜印刷燒結製程製作之晶片排容阻 器單元結構圖。 第2圖為以8 Pin 4C結構為例之習見晶片排容器零組 件端電極之%f圖。 第2皮器之線路圖(3A圖）與構成圖(38圖）。 第明之晶片排容阻電極之製作方法步驟 圖。 第 第 置示意圖 第7圖為本發明之此種晶片排容端電極之配置應用於 濾波器之一例，其中，7A圖為排阻之構成示意圖；7B圖 為排容之構成示意圖；7C圖為PC板之配置佈局圖；7D圖 為組裝成RC濾波器後之整體構成示意圖。 <圖示中元件名稱與符號對照> 本纸張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） I--------t-------IT------.^ (請先閱讀背面之注意事項再填寫本頁) 五 發明説明（ 1 2 3 4 5 6 9 基板. 晶面下電極. 晶为端電極, 晶面介電層. 晶面電阻層 晶面上電極 晶面護層. 晶面標示層. 晶片端電極. A7 B7 2, 10 3, 11 4, 12 6, 13 5, 14 7, 15 8, 16 9, 17 晶面下電極 晶背端電極. 晶面介電層 晶面上電極 晶面電阻層. 晶面護層 晶面標示層. 晶片端電極. (請先閲讀背面之注意事項再填寫本頁) -裝· •灰 部 A 標 準 局 Ά 工 消 費 合 作 杜 印 製 <較佳具體實例之詳細描述> 請參照第4圖，本發明之此種B 方法，其步驟為： b種日日片排容阻電極之仏 ⑴空白氧化鋁基板1切割（第4a 上形成切割線ιοί, 102。 ；虱化鋁基板 (2)底電極與背面電極印刷（第4B 割3的基板上形成底電極(未示)盘^以印刷方式糾 P)介電層印刷（第4C圖）：以印刷方面電極Π。 與背面電極之基板上形成介電層12，於已形成底電本 (4) 薄膜方式沉積厚〇 卿上 13(第4D圖）。 極（含電阻層）材米 (5) 微影及蝕刻之方式產生控制電極。 (6) 測試控制電極電容值並選擇適當 ⑺微f彡及蝴之^•式赵電容冑 f極光罩。 (8)微影及钱刻之方式產生電阻層 蛋130(第犯圖）。 S圓案！4(第奸圖）。 ---------- 210Χ297/^^~ A7 B7 五、發明説明（ (9)電阻層雷射切割。. 0〇)端電極製作。 '&本發明以薄膜方式沉積上電極（含電阻層）材料，並用 微影及蝕刻之方式與預測電極墊之製作與量測之手段，達 ，製作出正確電容上電極面積之晶片排容阻器之目的。其 剖面結構如第5圖，將雷射切割之氧化鋁基板丨以厚膜印 刷燒結製程製作底電極10，背面電極11，以及介電層12 後利用薄膜方式，如喷藏法(Sputter)，沉積厚〇1 — 厚=上電極13(含電阻層與導體層，如NiCr/NiCu/Cu)材料， 接著以微影及蝕刻之方式產生控制電極，並量測控制電極 之電容值，利用此種方式選擇適當之上電極光罩以修正介 =層印刷時，不同片/批次之印刷厚度差異，以達到設計目 標值。接著再對此晶片以選定之上電極光罩曝光，顯影後 ^蝕刻出電容器上電極，利用微影及蝕刻高精度的特性， 可以將同一片（80X84刪)晶片之電容值(50pf)控制在3%(一 ，標準差）以内。如此便可以得到高製造良率的晶片電容器 晶片排容器。對於電容阻器則再加曝一道電阻層光罩以相 同的微影及㈣之方式產生電阻層14 _。接下來採用傳 統後段製程’包括雷射修整阻值，護層15與標示層Μ之 =刷製程，再配合電鍍後製程完成端電極17之製作，即 完成本發明之晶片排容器零組件製作。 本發明之此種晶片排容端電極之構成請參照6 其配置為·· 晶片排容器之共地極位於晶片端側（包括一側與 8 ----------壯衣------’玎------^ (請先閱讀背面之注意事項再填寫本頁〕 經濟部中央橾準局貝工消費合作社印製 A7 B7 五、發明説明（ 側）’排容器之輪入端（不必需均位於晶片同一側）不與 電容器之共地極呈同—直線之配置者。 相較於第2圏示之習見晶片排容器零組件，本發明且 有以下之優點··對於某些應用電路’會簡化p c板的佈局空 間或層數’提高零組件組裝密度，降低pc版製造難度 如第7圖之低頻渡波器之佈局，在與電阻串接時，由於其 接地線路接點(pin 5，_於晶片棑容 波^ 裝 訂 輸入端〇^，2’3,4)與輸出端伽6,7^^1二 呈直線配置’相較於第2圖所示者，可省去額外的導^ 及拉線’使客戶在設計PC板時，大幅減少產生之 層數，增加零組件置放密度並與減少K：板製造成本、 從以上所述可知本發明之—種微小化 容阻器之製造方法與晶片排容器之結構対= 晶片排容阻器之構成與製造 ^有傳、洗曰曰片 線 片電容阻器產業之迅速發展:二Τ::= 開使用’合科槪之蚊1請麟專利，實騎t么 經濟部中央標準局員工消費合作社印製. Is the cross-sectional structure of the moon. The two kinds of consistent arrangement of the electrode for accommodating the end of such a wafer are described. V. Description of the invention (·) According to the arrangement structure of the terminal electrode of the electrode for the accommodating of such a wafer according to the present invention. It provides a common-ground-capacitive terminal electrode configuration structure. This common-electrode configuration structure at the chip end will enable customers to significantly reduce the number of vias and layers generated by layout when manufacturing PC boards, and increase component placement. Densification and reduction of PC board manufacturing costs are another object of the present invention. As for the detailed structure, manufacturing method steps, and other functions and features of the present invention, you can get a complete understanding with reference to the following description made with reference to the drawings: < Simple description of the diagram > Structure diagram of wafer row resistor unit produced by printing and sintering process. Figure 2 is a% f diagram of the end electrode of a conventional wafer row container component using the 8 Pin 4C structure as an example. Circuit diagram (Fig. 3A) and constitution diagram (Fig. 38) of the second skin tool. The figure shows the manufacturing method steps of the chip row capacitive resistor electrode. The 7th schematic diagram is an example of the application of the arrangement of the chip capacitor terminal electrode of the present invention to a filter. Among them, FIG. 7A is a schematic diagram of the structure of exclusion; FIG. 7B is a schematic diagram of the structure of exclusion; FIG. 7C is PC board configuration layout diagram; 7D is a schematic diagram of the overall structure after assembled into an RC filter. < Comparison of component names and symbols in the illustration > This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) I -------- t ------- IT ------. ^ (Please read the precautions on the back before filling out this page) Five invention descriptions (1 2 3 4 5 6 9 substrate. Crystal surface electrode. Crystal is terminal electrode, crystal surface dielectric layer. Crystal plane resistance layer Crystal plane electrode Crystal plane protection layer. Crystal plane marking layer. Chip end electrode. A7 B7 2, 10 3, 11 4, 12 6, 13 5, 14 7, 15 8, 16 9, 17 Crystal plane Bottom electrode, back electrode, crystal surface dielectric layer, crystal surface electrode, crystal surface resistance layer, crystal surface protective layer, crystal surface marking layer, chip end electrode. (Please read the precautions on the back before filling this page) • Grey Department A Standard Bureau, industrial and consumer cooperation, du print < detailed description of preferred specific examples > Please refer to FIG. 4, the method of this B method of the present invention, the steps are as follows: b. Electrode blank Alumina substrate 1 is cut (the cutting line is formed on section 4a, 102.); the bottom electrode and the back electrode of the aluminum substrate (2) are printed (the bottom electrode is formed on the substrate cut from section 4B (not shown)) Plate Brush-type correction P) Dielectric layer printing (Figure 4C): Print the electrode Π. A dielectric layer 12 is formed on the substrate with the back electrode, and a thick film (4) is deposited on the substrate. (Figure 4D). Electrode (including resistance layer) material meters (5) Control electrodes are generated by lithography and etching. (6) Test the capacitance of the control electrode and select the appropriate ⑺ • f Zhao capacitors.胄 f Aurora hood. (8) The resistive layer egg 130 is produced by lithography and money engraving (second figure). S round case! 4 (second figure). ---------- 210 × 297 / ^ ^ ~ A7 B7 V. Description of the invention ((9) Laser cutting of resistance layer. .0〇) fabrication of terminal electrode. '&Amp; The present invention deposits the material of the upper electrode (including the resistance layer) by thin film, and uses lithography and etching. Methods and methods of making and measuring electrode pads, to achieve the purpose of making a wafer row varistor with the correct electrode area on the capacitor. Its cross-sectional structure is shown in Figure 5. The laser-cut alumina substrate is thickened. After the film printing and sintering process is used to make the bottom electrode 10, the back electrode 11, and the dielectric layer 12, a thin film method is used, such as the spray method (Sputter). Product thickness 〇1 — Thickness = material of upper electrode 13 (including resistance layer and conductor layer, such as NiCr / NiCu / Cu), and then generate the control electrode by lithography and etching, and measure the capacitance of the control electrode. Use this In this way, a suitable upper electrode mask is selected to correct the printing thickness difference of different sheets / batches when interlayer printing is performed, so as to achieve the design target value. Then, the wafer is exposed with the selected upper electrode mask. After development, the capacitor upper electrode is etched. Using the characteristics of lithography and etching, the capacitance value (50pf) of the same (80X84 deleted) wafer can be controlled. Within 3% (one, standard deviation). In this way, a chip capacitor container with a high manufacturing yield can be obtained. For the capacitor resistor, a resistive layer mask is additionally exposed to generate the resistive layer 14 _ in the same manner as the lithography and plutonium. Next, the traditional back-end process is used to include the laser trimming resistance value, the protective layer 15 and the labeling layer M = the brushing process, and the production of the terminal electrode 17 is completed with the post-plating process to complete the wafer row container component manufacturing of the present invention. Please refer to 6 for the structure of the chip discharge terminal electrode of the present invention. The configuration is that the common ground electrode of the chip row container is located on the wafer end side (including one side and 8 ---------- strong clothing- ----- '玎 ------ ^ (Please read the precautions on the back before filling out this page] A7 B7 printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs. The wheel end of the container (not necessarily located on the same side of the chip) is not the same as the common ground of the capacitor-a straight line configuration. Compared to the conventionally shown wafer row container components shown in the second paragraph, the present invention has the following Advantages · For some application circuits, it will "simplify the layout space or number of layers of the pc board", increase the assembly density of components, and reduce the difficulty of manufacturing the pc version. The ground contact (pin 5, _ on the chip 棑 capacity wave ^ binding input terminal ^, 2'3, 4) and the output terminal 6, 6, ^ ^ 1 are arranged in a straight line, compared to the figure 2 Showers can eliminate the need for additional guides and cables to enable customers to significantly reduce the number of layers generated when designing PC boards, and increase component density. And reduce K: plate manufacturing cost. From the above, we can know that the present invention-a method of manufacturing a miniaturized resistor and the structure of a wafer row container 対 = the structure and manufacture of a wafer row resistor The rapid development of the chip wire chip resistor industry: two T :: = open to use 'Heke's Mosquito 1 please Lin patent, printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs