TW367546B - Manufacturing method of flash memory with self-aligned drain junction - Google Patents

Manufacturing method of flash memory with self-aligned drain junction

Info

Publication number
TW367546B
TW367546B TW087101658A TW87101658A TW367546B TW 367546 B TW367546 B TW 367546B TW 087101658 A TW087101658 A TW 087101658A TW 87101658 A TW87101658 A TW 87101658A TW 367546 B TW367546 B TW 367546B
Authority
TW
Taiwan
Prior art keywords
polycrystalline silicon
substrate
silicon layer
insulation layer
barrier
Prior art date
Application number
TW087101658A
Other languages
Chinese (zh)
Inventor
Hung-Cheng Sung
Di-Sheng Guo
Ya-Fen Lin
Chia-Dar Hsieh
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW087101658A priority Critical patent/TW367546B/en
Application granted granted Critical
Publication of TW367546B publication Critical patent/TW367546B/en

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Abstract

A kind of manufacturing method of flash memory with self-aligned drain junction which includes the following steps: provide a substrate; form sequentially the gate oxide, a floating polycrystalline silicon layer, a barrier and the first insulation on the surface of substrate; define the first insulation layer for etching and forming the first and the second openings on part of the surface of the exposed barrier; define the barrier to etch and form the third opening on part of the surface of the exposed floating polycrystalline silicon layer; through the third opening, form a thick bird-beak type insulation layer by applying thermal oxidation on the floating polycrystalline silicon; through the second opening, form a drain are by doping ions on one side of the substrate; remove the residual barrier and the first insulation layer; employ the thick bird-beak type insulation layer as the mask for anisotropic etching floating crystalline silicon layer to the surface of gate oxide; form sequentially a tunnel-penetrated oxide and a controlled polycrystalline silicon layer to elastically cover the substrate; define the controlled polycrystalline silicon layer and etched forming a specified pattern which constitutes a split gate with the tunnel-penetrated oxide, gate oxide, thick bird-beak insulation layer and floating polycrystalline silicon layer; and form a source area by doping ions on the other side of the substrate.
TW087101658A 1998-02-07 1998-02-07 Manufacturing method of flash memory with self-aligned drain junction TW367546B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087101658A TW367546B (en) 1998-02-07 1998-02-07 Manufacturing method of flash memory with self-aligned drain junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087101658A TW367546B (en) 1998-02-07 1998-02-07 Manufacturing method of flash memory with self-aligned drain junction

Publications (1)

Publication Number Publication Date
TW367546B true TW367546B (en) 1999-08-21

Family

ID=57941238

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087101658A TW367546B (en) 1998-02-07 1998-02-07 Manufacturing method of flash memory with self-aligned drain junction

Country Status (1)

Country Link
TW (1) TW367546B (en)

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