TW366552B - Method of manufacturing DRAM capacitor components - Google Patents

Abstract

Method of manufacturing DRAM capacitor components by using the self-alignment technology to overcome the troubles caused by inaccurate alignment in the manufacturing process so as to increase the electrical capacity of the capacitor component by increasing the surface space of the electrode as a compact side to meet the design rule, including the manufacturing method the following steps: presentation of a silicon substrate having on it a transistor formed, including gate electrode, source/drain and an oxide area; forming a first insulation layer on the chip with etching for forming a contact opening protruding the substrate surface of the contact window and the first insulation layer; forming a second insulation layer on said first conductive layer, coating a photoresist layer on said second insulation layer before defining said second insulation layer using the know optic microfilm and etching technology, preserving the area above the contact window as mask for continuous etching for said first conductor layer; forming a third insulation layer on said first conductor layer and the second insulation layer on the contact window contacting the same; non-equivalent direction etching said third insulation layer for forming a sidewall spacing layer on said second insulation layer; using said second insulation layer on said contact window and said sidewall gap as mask for etching said conductor layer; removal of said second insulation layer; using said sidewall gap as mask for etching the surface of said first conductor layer, for forming a bump structure, for self-alignment with the edge of said sidewall gap layer, for the lower-level electrode of the capacitor; removal of said sidewall gap layer; forming a dielectric layer on said lower-level electrode and forming a second conductor layer on said dielectric layer, for upper-level electrode of the capacitor, thus accomplishing the making of the DRAM cell.