TW362323B - Address memory structure of ethernet switch and the address handling of network nodes - Google Patents

Address memory structure of ethernet switch and the address handling of network nodes

Info

Publication number
TW362323B
TW362323B TW087104225A TW87104225A TW362323B TW 362323 B TW362323 B TW 362323B TW 087104225 A TW087104225 A TW 087104225A TW 87104225 A TW87104225 A TW 87104225A TW 362323 B TW362323 B TW 362323B
Authority
TW
Taiwan
Prior art keywords
address
ethernet switch
memory structure
network nodes
memory
Prior art date
Application number
TW087104225A
Other languages
English (en)
Inventor
He-Shian Lin
Wen-Tsung Lin
Original Assignee
Winbond Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronic Corp filed Critical Winbond Electronic Corp
Priority to TW087104225A priority Critical patent/TW362323B/zh
Priority to US09/092,837 priority patent/US6490288B1/en
Application granted granted Critical
Publication of TW362323B publication Critical patent/TW362323B/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/45—Network directories; Name-to-address mapping
    • H04L61/4552—Lookup mechanisms between a plurality of directories; Synchronisation of directories, e.g. metadirectories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
TW087104225A 1998-03-20 1998-03-20 Address memory structure of ethernet switch and the address handling of network nodes TW362323B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW087104225A TW362323B (en) 1998-03-20 1998-03-20 Address memory structure of ethernet switch and the address handling of network nodes
US09/092,837 US6490288B1 (en) 1998-03-20 1998-06-05 Address memory structure and method for processing network node addresses in the Ethernet switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087104225A TW362323B (en) 1998-03-20 1998-03-20 Address memory structure of ethernet switch and the address handling of network nodes

Publications (1)

Publication Number Publication Date
TW362323B true TW362323B (en) 1999-06-21

Family

ID=21629734

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087104225A TW362323B (en) 1998-03-20 1998-03-20 Address memory structure of ethernet switch and the address handling of network nodes

Country Status (2)

Country Link
US (1) US6490288B1 (zh)
TW (1) TW362323B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316795C (zh) * 1999-09-10 2007-05-16 Lg-北电株式会社 建立非管理以太网交换机结构信息的设备和方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7694025B1 (en) 2006-03-31 2010-04-06 Integrated Device Technology, Inc. Method and device for base address sorting and entry into base address registers
US7647438B1 (en) 2006-05-09 2010-01-12 Integrated Device Technology, Inc. Binary base address sorting method and device with shift vector
US7779197B1 (en) 2006-05-09 2010-08-17 Integrated Device Technology, Inc. Device and method for address matching with post matching limit check and nullification
US7634586B1 (en) 2006-06-05 2009-12-15 Integrated Device Technology, Inc. Device for concurrent limit validity check

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471472A (en) * 1991-07-30 1995-11-28 Synernetics Inc. Network multiplexer
JP3376135B2 (ja) * 1994-12-16 2003-02-10 キヤノン株式会社 ネットワークシステム及びノード装置及びその制御方法及び伝送制御方法
KR100210806B1 (ko) * 1996-12-10 1999-07-15 유기범 프로세서간 통신(ipc)노드주소 초기화 방법
KR100210807B1 (ko) * 1996-12-23 1999-07-15 유기범 프로세서간 통신 메세지 라우팅 장치
US6393548B1 (en) * 1997-02-14 2002-05-21 Advanced Micro Devices, Inc. Variable 16 or 32 bit PCI interface which supports steering and swapping of data
US6240485B1 (en) * 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316795C (zh) * 1999-09-10 2007-05-16 Lg-北电株式会社 建立非管理以太网交换机结构信息的设备和方法

Also Published As

Publication number Publication date
US6490288B1 (en) 2002-12-03

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Legal Events

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MK4A Expiration of patent term of an invention patent