TW351018B - Method of manufacturing of the figured capacitor in D-RAMs - Google Patents

Method of manufacturing of the figured capacitor in D-RAMs

Info

Publication number
TW351018B
TW351018B TW087102129A TW87102129A TW351018B TW 351018 B TW351018 B TW 351018B TW 087102129 A TW087102129 A TW 087102129A TW 87102129 A TW87102129 A TW 87102129A TW 351018 B TW351018 B TW 351018B
Authority
TW
Taiwan
Prior art keywords
dielectric layer
forming
layer
etching
capacitor
Prior art date
Application number
TW087102129A
Other languages
Chinese (zh)
Inventor
Xie-Lin Wu
Original Assignee
Tsmc Acer Semiconductor Mfg Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsmc Acer Semiconductor Mfg Corp filed Critical Tsmc Acer Semiconductor Mfg Corp
Priority to TW087102129A priority Critical patent/TW351018B/en
Application granted granted Critical
Publication of TW351018B publication Critical patent/TW351018B/en

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Abstract

A sort of method of manufacturing of the figured capacitor in D-RAMs, including at least: forming the first dielectric layer on the semiconductor wafer; forming the first conductor layer onto the first dielectric layer; forming the second dielectric layer onto the first conductor layer; forming the third dielectric layer onto the second dielectric layer; etching the third dielectric layer and the bottom area of the second dielectric layer; etching in sequence the second dielectric layer, being the first conductor layer and the first dielectric layer to form the contact opening in contact part of the semiconductor wafer, being the etching process with a screen of the third dielectric layer, which is removed in the etching of the first dielectric layer; forming of the second conductor layer on the second dielectric layer and in the contact opening, the second conductor layer in contact part of the area of the semiconductor wafer; forming the structure of the substrate electrode, by iso-directional etching of the second conductor layer and the second dielectric layer and the first conductor layer, before equal-directional etching the first dielectric layer for forming; forming the fourth dielectric layer onto the substrate electrode; and forming the third conductor layer on the fourth dielectric layer for forming the top electrode of the capacitor.
TW087102129A 1998-02-16 1998-02-16 Method of manufacturing of the figured capacitor in D-RAMs TW351018B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087102129A TW351018B (en) 1998-02-16 1998-02-16 Method of manufacturing of the figured capacitor in D-RAMs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087102129A TW351018B (en) 1998-02-16 1998-02-16 Method of manufacturing of the figured capacitor in D-RAMs

Publications (1)

Publication Number Publication Date
TW351018B true TW351018B (en) 1999-01-21

Family

ID=57939973

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087102129A TW351018B (en) 1998-02-16 1998-02-16 Method of manufacturing of the figured capacitor in D-RAMs

Country Status (1)

Country Link
TW (1) TW351018B (en)

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