TW345638B - Control structure for a high-speed asynchronous pipeline - Google Patents
Control structure for a high-speed asynchronous pipelineInfo
- Publication number
- TW345638B TW345638B TW086114134A TW86114134A TW345638B TW 345638 B TW345638 B TW 345638B TW 086114134 A TW086114134 A TW 086114134A TW 86114134 A TW86114134 A TW 86114134A TW 345638 B TW345638 B TW 345638B
- Authority
- TW
- Taiwan
- Prior art keywords
- control structure
- asynchronous pipeline
- stages
- control circuit
- control
- Prior art date
Links
- 238000001514 detection method Methods 0.000 abstract 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3884—Pipelining
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Information Transfer Systems (AREA)
- Dram (AREA)
- Shift Register Type Memory (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/720,755 US5937177A (en) | 1996-10-01 | 1996-10-01 | Control structure for a high-speed asynchronous pipeline |
Publications (1)
Publication Number | Publication Date |
---|---|
TW345638B true TW345638B (en) | 1998-11-21 |
Family
ID=24895160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086114134A TW345638B (en) | 1996-10-01 | 1997-09-27 | Control structure for a high-speed asynchronous pipeline |
Country Status (6)
Country | Link |
---|---|
US (1) | US5937177A (zh) |
EP (2) | EP0834802A3 (zh) |
JP (1) | JPH11167791A (zh) |
KR (1) | KR19980032458A (zh) |
SG (1) | SG79221A1 (zh) |
TW (1) | TW345638B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6502180B1 (en) * | 1997-09-12 | 2002-12-31 | California Institute Of Technology | Asynchronous circuits with pipelined completion process |
US9092595B2 (en) | 1997-10-08 | 2015-07-28 | Pact Xpp Technologies Ag | Multiprocessor having associated RAM units |
US7546444B1 (en) | 1999-09-01 | 2009-06-09 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US6477637B1 (en) * | 1999-09-30 | 2002-11-05 | International Business Machines Corporation | Method and apparatus for transporting store requests between functional units within a processor |
US6574690B1 (en) | 1999-12-29 | 2003-06-03 | Sun Microsystems, Inc. | Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first and second subordinate fifo |
US7681018B2 (en) | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US6420907B1 (en) * | 2000-09-29 | 2002-07-16 | Sun Microsystems, Inc. | Method and apparatus for asynchronously controlling state information within a circuit |
US20020078328A1 (en) * | 2000-12-14 | 2002-06-20 | International Business Machines Corporation | Pulse-controlled micropipeline architecture |
US6925549B2 (en) * | 2000-12-21 | 2005-08-02 | International Business Machines Corporation | Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages |
US6859873B2 (en) * | 2001-06-08 | 2005-02-22 | Infineon Technologies Ag | Variable length instruction pipeline |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
AU2003233109A1 (en) * | 2002-06-14 | 2003-12-31 | Koninklijke Philips Electronics N.V. | Fifo-register |
US7423696B2 (en) * | 2005-01-07 | 2008-09-09 | Hewlett-Packard Development Company, L.P. | Concurrent luminance-saturation adjustment of digital images |
EP1927045A2 (en) * | 2005-09-05 | 2008-06-04 | Nxp B.V. | Asynchronous ripple pipeline |
US7890826B2 (en) * | 2006-12-11 | 2011-02-15 | Oracle America, Inc. | Method and apparatus for test of asynchronous pipelines |
US7971043B2 (en) * | 2007-11-22 | 2011-06-28 | Andes Technology Corporation | Electronic system and method for changing number of operation stages of a pipeline |
US20150074353A1 (en) * | 2013-09-06 | 2015-03-12 | Futurewei Technologies, Inc. | System and Method for an Asynchronous Processor with Multiple Threading |
US9385717B1 (en) * | 2014-05-30 | 2016-07-05 | Altera Corporation | Level-sensitive two-phase single-wire latch controllers without contention |
CN112667292B (zh) * | 2021-01-26 | 2024-04-05 | 北京中科芯蕊科技有限公司 | 一种异步微流水线控制器 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3510680A (en) * | 1967-06-28 | 1970-05-05 | Mohawk Data Sciences Corp | Asynchronous shift register with data control gating therefor |
US4151609A (en) * | 1977-10-11 | 1979-04-24 | Monolithic Memories, Inc. | First in first out (FIFO) memory |
US4225920A (en) * | 1978-09-11 | 1980-09-30 | Burroughs Corporation | Operator independent template control architecture |
FR2552916B1 (fr) * | 1983-09-29 | 1988-06-10 | Thomas Alain | File d'attente asynchrone a empilement de registres |
US5187800A (en) * | 1985-01-04 | 1993-02-16 | Sun Microsystems, Inc. | Asynchronous pipelined data processing system |
US4791551A (en) * | 1985-02-11 | 1988-12-13 | Analog Devices, Inc. | Microprogrammable devices using transparent latch |
US4805139A (en) * | 1987-10-22 | 1989-02-14 | Advanced Micro Devices, Inc. | Propagating FIFO storage device |
GB9114513D0 (en) * | 1991-07-04 | 1991-08-21 | Univ Manchester | Condition detection in asynchronous pipelines |
US5572691A (en) * | 1993-04-21 | 1996-11-05 | Gi Corporation | Apparatus and method for providing multiple data streams from stored data using dual memory buffers |
US5513224A (en) * | 1993-09-16 | 1996-04-30 | Codex, Corp. | Fill level indicator for self-timed fifo |
DE69430352T2 (de) * | 1993-10-21 | 2003-01-30 | Sun Microsystems Inc., Mountain View | Gegenflusspipeline |
US5638009A (en) * | 1993-10-21 | 1997-06-10 | Sun Microsystems, Inc. | Three conductor asynchronous signaling |
-
1996
- 1996-10-01 US US08/720,755 patent/US5937177A/en not_active Expired - Lifetime
-
1997
- 1997-09-26 EP EP97402249A patent/EP0834802A3/en not_active Withdrawn
- 1997-09-26 EP EP02027382A patent/EP1296221A1/en not_active Withdrawn
- 1997-09-27 TW TW086114134A patent/TW345638B/zh active
- 1997-09-30 JP JP9284373A patent/JPH11167791A/ja active Pending
- 1997-10-01 SG SG9703626A patent/SG79221A1/en unknown
- 1997-10-01 KR KR1019970050738A patent/KR19980032458A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
SG79221A1 (en) | 2001-03-20 |
JPH11167791A (ja) | 1999-06-22 |
KR19980032458A (ko) | 1998-07-25 |
EP1296221A1 (en) | 2003-03-26 |
EP0834802A3 (en) | 1999-05-19 |
EP0834802A2 (en) | 1998-04-08 |
US5937177A (en) | 1999-08-10 |
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