TW341001B - Delay circuit - Google Patents

Delay circuit

Info

Publication number
TW341001B
TW341001B TW085113212A TW85113212A TW341001B TW 341001 B TW341001 B TW 341001B TW 085113212 A TW085113212 A TW 085113212A TW 85113212 A TW85113212 A TW 85113212A TW 341001 B TW341001 B TW 341001B
Authority
TW
Taiwan
Prior art keywords
output
delay circuit
voltage
accumulator
signal
Prior art date
Application number
TW085113212A
Other languages
English (en)
Inventor
Yasuhiko Tsukikawa
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW341001B publication Critical patent/TW341001B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/0013—Avoiding variations of delay due to power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00136—Avoiding asymmetry of delay for leading or trailing edge; Avoiding variations of delay due to threshold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks
TW085113212A 1996-05-14 1996-10-29 Delay circuit TW341001B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11902196A JP3702038B2 (ja) 1996-05-14 1996-05-14 遅延回路

Publications (1)

Publication Number Publication Date
TW341001B true TW341001B (en) 1998-09-21

Family

ID=14751028

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085113212A TW341001B (en) 1996-05-14 1996-10-29 Delay circuit

Country Status (4)

Country Link
US (1) US6121812A (zh)
JP (1) JP3702038B2 (zh)
KR (1) KR100262029B1 (zh)
TW (1) TW341001B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3023776B2 (ja) * 1998-04-28 2000-03-21 セイコーインスツルメンツ株式会社 遅延回路
JP2000306382A (ja) * 1999-02-17 2000-11-02 Hitachi Ltd 半導体集積回路装置
CA2263061C (en) * 1999-02-26 2011-01-25 Ki-Jun Lee Dual control analog delay element
KR100370233B1 (ko) * 1999-05-19 2003-01-29 삼성전자 주식회사 입력버퍼 회로
US6753705B1 (en) * 2000-07-27 2004-06-22 Sigmatel, Inc. Edge sensitive detection circuit
US6632686B1 (en) * 2000-09-29 2003-10-14 Intel Corporation Silicon on insulator device design having improved floating body effect
JP4053232B2 (ja) * 2000-11-20 2008-02-27 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
US6624680B2 (en) * 2000-12-29 2003-09-23 Texas Instruments Incorporated Reduction of propagation delay dependence on supply voltage in a digital circuit
JP2004096493A (ja) * 2002-08-30 2004-03-25 Nec Electronics Corp パルス発生回路及び半導体装置
US7057450B2 (en) * 2003-07-30 2006-06-06 Winbond Electronics Corp. Noise filter for an integrated circuit
US7167400B2 (en) * 2004-06-22 2007-01-23 Micron Technology, Inc. Apparatus and method for improving dynamic refresh in a memory device
US7279924B1 (en) * 2005-07-14 2007-10-09 Altera Corporation Equalization circuit cells with higher-order response characteristics
FR2977077B1 (fr) * 2011-06-27 2013-08-02 Commissariat Energie Atomique Generateur de retards utilisant une resistance programmable a base de materiau a changement de phase
CN103873038B (zh) * 2012-12-17 2017-02-08 快捷半导体(苏州)有限公司 一种延时时间调整电路、方法和集成电路
JP6380827B2 (ja) * 2014-01-27 2018-08-29 富士電機株式会社 遅延回路
US9865486B2 (en) 2016-03-29 2018-01-09 Globalfoundries Inc. Timing/power risk optimized selective voltage binning using non-linear voltage slope
CN112438020B (zh) * 2018-08-01 2022-05-17 美光科技公司 半导体装置、延迟电路和相关方法
JP2021129255A (ja) * 2020-02-17 2021-09-02 ミツミ電機株式会社 パルス信号送信回路
KR102568596B1 (ko) * 2022-01-04 2023-08-21 주식회사 피델릭스 기준 전압 레벨 변동을 저감하는 버퍼 회로

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924566B2 (ja) * 1981-04-30 1984-06-11 岩崎通信機株式会社 可変遅延回路
KR930003482A (ko) * 1991-07-16 1993-02-24 젯.엘.더머 반전 시간 지연 회로
JP3020345B2 (ja) * 1992-05-19 2000-03-15 株式会社 沖マイクロデザイン 半導体記憶回路

Also Published As

Publication number Publication date
US6121812A (en) 2000-09-19
KR970076846A (ko) 1997-12-12
JP3702038B2 (ja) 2005-10-05
JPH09307415A (ja) 1997-11-28
KR100262029B1 (ko) 2000-07-15

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