TW334617B - The process of DRAM cell with crown capacitor - Google Patents

Abstract

A process of DRAM cell with crown capacitor, it includes following steps: (a) Provide semiconductor substrate, which has already formed transistor that includes gate, source/drain and an insulating to cover on transistor. (b) Selectively etch insulating till the semiconductor substrate surface, to form a contact opening to expose one of source and drain as contact area. (c) Form 1st conductive layer to cover on insulating surface, and fill contact window, and to form electrical connection with contact area. (d) Sequentially form etching stopper and a screen layer on 1st conductive layer, in which, the etching stopper has different material with 1st conductive layer. (e) Define the pattern of screen to form plural openings, to expose area used for separating each memory cell. (f) Form insulating sidewall at screen sidewall, and remove the exposing portion of etching stopper. (g) Use insulating sidewall as mask, anisotropically etch screen and 1st conductive layer, separately till exposing etching stop and insulating surface, used to define a capacitor range. (h) Remove portion of etching stopper that is uncovered by insulating sidewall layer, to expose 1st conductive surface. (I) Use insulating sidewall as mask, anisotropically etch 1st conductive layer till a certain depth, used to form a storage electrode with protruding crown-shape. (j) Remove insulating sidewall and etching stopper. (k) Form dielectric layer on capacitor storage electrode to expose the surface. (l) Form 2nd conductive layer on dielectric layer, to compose a relative electrode, to finish the producing of DRAM cell.