TW334546B - Data processor - Google Patents

Data processor

Info

Publication number
TW334546B
TW334546B TW086101951A TW86101951A TW334546B TW 334546 B TW334546 B TW 334546B TW 086101951 A TW086101951 A TW 086101951A TW 86101951 A TW86101951 A TW 86101951A TW 334546 B TW334546 B TW 334546B
Authority
TW
Taiwan
Prior art keywords
instruction
data processor
execution
format
executed
Prior art date
Application number
TW086101951A
Other languages
English (en)
Inventor
Masahiro Uminaga
Yasuhiko Saitou
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW334546B publication Critical patent/TW334546B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
TW086101951A 1996-03-18 1997-02-19 Data processor TW334546B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6057196 1996-03-18

Publications (1)

Publication Number Publication Date
TW334546B true TW334546B (en) 1998-06-21

Family

ID=13146088

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101951A TW334546B (en) 1996-03-18 1997-02-19 Data processor

Country Status (3)

Country Link
US (1) US20020116599A1 (zh)
KR (1) KR970066927A (zh)
TW (1) TW334546B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9772800B2 (en) 2014-10-03 2017-09-26 Genesys Logic, Inc. Universal serial bus controller and wiring substrate

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6957321B2 (en) * 2002-06-19 2005-10-18 Intel Corporation Instruction set extension using operand bearing NOP instructions
US7984272B2 (en) * 2007-06-27 2011-07-19 International Business Machines Corporation Design structure for single hot forward interconnect scheme for delayed execution pipelines
US9286072B2 (en) 2011-10-03 2016-03-15 International Business Machines Corporation Using register last use infomation to perform decode-time computer instruction optimization
US9329869B2 (en) * 2011-10-03 2016-05-03 International Business Machines Corporation Prefix computer instruction for compatibily extending instruction functionality
US9354874B2 (en) 2011-10-03 2016-05-31 International Business Machines Corporation Scalable decode-time instruction sequence optimization of dependent instructions
CN102411492B (zh) * 2011-11-25 2014-04-23 北京创毅视讯科技有限公司 一种数据处理的方法和装置
JP6422381B2 (ja) * 2015-03-18 2018-11-14 ルネサスエレクトロニクス株式会社 プロセッサ、プログラムコード変換装置及びソフトウェア
GB2543304B (en) 2015-10-14 2020-10-28 Advanced Risc Mach Ltd Move prefix instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9772800B2 (en) 2014-10-03 2017-09-26 Genesys Logic, Inc. Universal serial bus controller and wiring substrate

Also Published As

Publication number Publication date
KR970066927A (ko) 1997-10-13
US20020116599A1 (en) 2002-08-22

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