TW316299B - - Google Patents

Description

Printed 316S99 A7 B7 by the Negative Work Consumer Cooperative of the Central Ministry of Economic Affairs V. Description of the invention (1) Background of the invention The present invention relates to a control circuit between bus bars. This signal is used to replace multiple delays in small computers such as computer systems. Good _ confluence ·-row, and there is about electric system with _ control signal). In recent years, personal computers have become more popular, and the extended bus used to make information communication between the CPU and multiple input / output devices has been changed considerably, and CPU components can be greatly improved. Fu Tong's standard bus called ISA (Industry Standard Architecture) has been adopted by the extended M bus in general personal computers. Therefore, there are many expansion boards based on this standard value in the commercial market. Due to the improvement of the performance through cp.u, the rapid processing capability of mi fishing has been achieved. The data transmission speed between the CPU and the input / output device is increased as long as the ISA bus is used. It has recently been noticed that the standard used for this extended bus is the bus standard called PC "Peripheral Component Interconnect", which has been established as a bus standard for American Corporation. PCI Bus τ ς A Bg Μ Age #r eating afr Luar ar Taiwan S ti 'information collision prevention ability can be provided to the bureaucratic-suspect-space from the version of the announcement organization, by the configuration of the function of I / O space, so there is a month to make PCJJUL In the future, it will be used in the input and output buses of high-performance small computers (such as workstations and personal computers). The PC I bus standard defines the upper limit of the number of sugar tanks with "« g and connected busbars, to prevent the use of high power The bad-electric-king-characteristics caused by the operating frequency. Therefore, _—m “, must be equipped with multiple—PCI sleep streams to provide the system with multiple devices and multiple expansion slots with an upper limit of η. The method chosen is based on the paper standard applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page)

No. Jjr / Postal Code Patent Application Special_Chinese Specification Amendment Page ·, A Kunguo Amendment in March _ Β7 '~ ： Β7 Ikr 雅 五, Invention Description (2) Work Monthly Ends Provided by PCISIG " PCI to PCI Bridge Architecture " Specifications. tlltll! ^^ Tolerated. Amended. Printed by Beigong Consumer Cooperation, Central Bureau of Standards, Ministry of Economic Affairs. When multiple PCI buses are configured, this method illustrates a guide wire for the bridge circuit to alternate the first PCI bus (main bus) and the second PCI Busbar (second busbar). The manual of the PCI-PCI bridge chip also describes — a similar technology 'see " DEC chip 21505 PCI-to-PCI Bridge Data Sheet ", pages 3, 1-5, published by Digital Instruments. Figures 2A and 2B are computer systems with dual bus configurations and traditional PCI-PCI bridges. In FIG. 2A, the system includes CPU1, memory 2, and bus / memory controller 3, which are used to execute the local bus 1QQ of CPU 1 (hereinafter referred to as “processor bus π”) to the first PCI bus Conversion between 2000, access control of memory 2, etc .; PCI-PCI bridge circuit (1) 4 is used to alternately use the first PCI bus 200 and the second PCI bus 201, and another PCI- The PCI bridge circuit (2) 5 is used to interleave the second PCI bus 201 and the third PCI bus 202. The PCI devices used to control multiple input / output devices are connected to the corresponding PCI bus. For example, this Location # The assumed configuration can be: PCI devices 6 and 7 connected to the first PCI bus 200 are the controller 1 used to control a display and file storage unit (not shown), and connected to the third PCI bus 202 The PCI devices 8 and 9 can be controllers for controlling a communication network. The PCI-PCI bridge circuit 2 (5) and the PCI devices 8 and 9 are connected to the second PCI bus 201 via the connector 10. In this way, one level Configure the connection between the processor bus 100 and multiple PCI buses 200-202. Note that although not shown in the figure The commercial controller and expansion board used for ISA bus can also be used in the system of PCI-ISA bridge circuit in Figure 2 to apply the Chinese National Standard (CNS) A4 specification to the PCI bus and traditional ISA bus. 210X297mm) (Please read the precautions on the back before filling in this page) Order Λ -5-Λ 年 正 A7 B7 V. Description of invention 1 Transfer between rows Y ^ S—1-exchange., Central Bureau of Standards, Ministry of Economic Affairs Printed by employee consumer cooperatives. Generally, these bridge circuits contain one or more LSIs. PCI-PCI bridge circuits 4, 5 are actually configured by the same LSI, especially with the internal configuration shown in FIG. 2B. A part of the first PCI bus (main bus) interface connects the main target unit 41 and the first main unit 43, and a part for interfacing with the second PCI bus (second bus) The second main unit 42 and the second target unit 44 are connected. Moreover, the PCI-PCI bridge circuit includes a configuration register 45, which is based on the PCI bus standard, and is used to receive and buffer data circulating through the bus of the two buses Set the PCIs, etc. When connecting the second bus When the device is accessed by a device connected to the first bus (the first bus is like the bus / memory controller 3), the first target unit 41 in the PCI-PCI bridge circuit 4 receives the access and It passes through to the second main unit 42 which circulates the generated bus as the access to the second bus. Similarly, when the device connected to the first bus is the device connected to the second bus When accessed, the second target unit 44 in the PCI-PCI bridge circuit 4 receives the access and passes it to the first main unit 43, which in turn generates a bus cycle as the first bus Access. In this way, because multiple PCI buses can be implemented in a single system via the PCI-PCI bridge circuit PCI that performs alternate functions, the system can provide a large number of PCI devices and expand the local area. However, the PCI-PCI bridge circuit described above only receives and Through the access between the first PCI bus and the second PCI bus. In particular, the paper standard of PCI-PCI bridge circuit is only applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ~: -6-(please read the precautions on the back before filling in this page) Order Λ

Receiving on one bus generates a birth control as another bus

The bus controller of the bus is used as the target and the bus is the target, and the bus is produced. The PCI bus must provide an integrated control mechanism that is connected to it, which is shared by the link, and an interrupt control mechanism between the processors needs it locally. Therefore, the corresponding control is to decode the bus cycle, etc., so that the entire. Moreover, because the corresponding control circuit consists of the number of parts and the PCI-PCI bridge circuit required to assemble these parts on the board, the base area is required to increase the number of parts, so the whole system is (Fill in this page again) Ordered by the Ministry of the Qing Dynasty Central Bureau of Precinct Employee Consumer Cooperation Du Printing Apparatus Summary of the invention The problem described in the present invention, and the invention uses the computer system of the present invention using the connection between the target objects and the like. In order to achieve the above-mentioned inter-control circuit, the purpose is to solve the inter-bus control circuit for the computer system with dual bus configuration. Another purpose is to effectively reduce the size of logic signals through the entire computer system, basically avoiding the use of multiple identical signals for control circuits between buses. Another object is to provide a low-cost, dual-bus configuration to further understand the other objects of the present invention. For the purpose, the bus used in the computer system of the present invention excludes that the first PCI bus and the second PCI bus are alternately used in this paper standard. Chinese National Standard (CNS) Α4 specification (210Χ297 mm) Λ! 7 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. In addition to the functions of the invention description (5), it contains the F-control mechanism, a device for connecting the jcj bus bar, and a J8L control mechanism for controlling Interrupt actions between local processors. In particular, when receiving an I stream that accesses one of the I ^ and the ^ bus. Discharge media • ring, the inter-bus control "ilLa way decision @ is a pair of access to devices connected to other buses , Or a pair of shared memory access, the shared __ 丨 丨 丨 _ 丨 丨 丨 丨 丨 丨 丨 1111- 1 AJI in the memory of the PC I sleep row is announced. Based on the results, if the bus cycle is an independent one, the device connects one of the second and second j bus to the other bus, and generates a bus cycle on the other bus as the main device. If the result of% ^ shows that the bus cycle is-access to the memory for A, the shield 1 < inter-discrimination control circuit generates min j as the target object for the bus cycle, and accesses to jgjui. Moreover, if the _set on the second bus (local processor) is used, the control circuit between the I-banks uses the internally provided rib (dP.dinhd) register, based on the temporary setting UP in the On the second busbar, the medium-sized lambs produced by the cows. y k In the electric pulse system with dual sink JLJI configuration, basically the bus bar controls the JIL military demand circuit to circulate the sink J & bar and so on. In the present invention, a common memory control mechanism and an intermediate connection mechanism t are provided for the inter-sink control circuit, so that a single decoder circuit used for code, bus, and ring can be shared by these mechanisms. In addition, the Russian-French-Macro function is also provided for the control circuit of Huiyue _ row (please read the precautions on the back and then fill out this page). Binding · Binding-Paper size is applicable to China National Standard #CN （CNS） A4 Specifications (21〇X; 297 mm) S16239 Ministry of Economic Affairs Central Standard Juzheng Consumer Cooperative Printed A7 ____B7 V. Description of Invention (6) Decode the result of the goose A male cycle and decide whether it is a shared flow. In memory, the memory of the memory controller λ «through the interrupt control mechanism can be integrated in the bus circuit between the bus bars. This integration also helps to reduce the number of parts and the layout area in the computer system. The block diagram in Figure 1 is a block diagram of the present invention, which uses the dual-sink $ challenge ▼ • the configuration of the system; the block diagram in Figure 2A The configuration of a traditional computer system with a row configuration; the block in Figure 2 ^^ shows the traditional PCI-PC I bridge; Figure U: the block shows the configuration of the PCLL-PCI bridge (inter-bus control circuit) in the present invention; and The block diagram of FIG. 42a corresponds to the details of the first target sassafras unit 401 and the second target control unit 403. DESCRIPTION OF PREFERRED EMBODIMENTS The following describes the embodiments of the present invention, and please refer to _. Figure 1 shows a block diagram of the computer system type M of the present invention. The portion 300 formed by the dots is an example of expansion. It refers to an example of an expansion board that is not connected to the first flow bar in a computer system. In the embodiment that will be described here, the '第 -P C.IM stream 9 η 1 initially contains an extended private ^, and the local iJL selects U-, U ·, ^) via the control signal 60, (please read the note on the back first Please fill in this page again for details) • The paper size of the staple thread is applicable to the China National Standard (CNS) A4 specification (210X297mm)

A7 B7 Printed by Dui Consumption Cooperation, Central Bureau of Standards, Ministry of Economic Affairs V. Invention description (61 is connected to the second PCI bus 201. The computer system shown in FIG. 1 includes a main CPU1, a main memory 2; and a first Two high-speed access buffer storage memory 20, a bus / memory controller 3, used to perform the conversion function of the processor bus 100 of the main CPU 1 to the first PCI bus 200, a pair of main memory 2 Access control, etc .; and PCI-PCI bridge signal 40, used to alternately use the first PCI bus 200 and the second PCI bus 201. PCI devices used to control different input / output devices (6, 7 , 60, 61) is connected to the corresponding PCI bus. For example, the PCI devices 6, 7 connected to the first PCI bus 200 may be a circuit device that controls a display and a file storage unit (not shown), and is connected to the first The PCI devices 60, 61 of the two PCI buses 201 can be LSIs that serve as a local CPU and local memory to the second PCI bus 201 (or reverse). As shown in the figure, the control LSI is two sets of local CPUs (70, 71, 72, 73) and local memory (80, 81, 82, 83) and the second PCI bus 201 In particular, the control LSI is the interface between the local CPU 70 and the local memory 80 group and another group of local CPU 71 and the local memory 81 to the second CPU bus 201. Similarly, the control LSI jl is a group of local CPU 72 and local The interface between the memory 82 and another set of local CPU 73 and local memory 83 to the second CPU bus 201. It should be noted that other control LSIs can be connected to the second CPU bus 201 in the same manner. Moreover, the first The PCI-PCI bridge circuit 40 interleaved by the PCI bus 200 and the second PCI bus 201 is connected to the global memory 50, which is a memory that can be shared from the local CPUs 70-73. The global memory 50 includes multiple types It is the data shared by local CPU70-73. The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page)

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A7 B7 316299 V. Invention description LH-} · (Please read the notes on the back before filling in this page) In one of the preferred embodiments of this embodiment, image processing can be shared by the corresponding local CPU. In the simplest use, the screen of an image is divided into four screens, so that the local CPU 70-73 is assigned to the image processing performed separately in the corresponding divided sub-screen, and the CPU integrates the individually processed sub-screens to match the first The display connected to the PCI bus displays the image of the entire process. In this matter, the data for display is stored in the global memory 50, and the corresponding CPU 70-73 accesses the display data according to the access, and the data is stored in the global memory 50. When multiple CPUs connect the second CPU bus to create a micro-processing configuration, the PCI-PCI bridge with CPU control function can be used more efficiently. The block of FIG. 3 illustrates the internal configuration of the PCI-PCI bridge circuit 40. It should be noted that the connection from one component to another component in FIG. 3 is indicated by the arrow line. For each digital text enclosed by a circle, it is also used to indicate the connection of the line part with arrows. If drawn, it will make the graphics more complicated. "Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Please refer to Figure 3 The PCI-PCI bridge circuit 40 includes an interface circuit 410, which is an interface between the PCI-PCI bridge circuit and the first PCI bus (bus master) 200; and the second PCI bus (second bus) The interface between 201 is interface unit 420. The PCI-PCI bridge circuit 40 also includes a first target column control (PTC) unit 401, which responds to access from the first bus when the first bus 200 is the target; a second master control (SMC) unit 402, used to access the second bus 201 as the bus master; the second target control (STC) unit 403 is used to respond to access from the second bus 201, the second bus 201 as a target; and a first main control (PMC) unit 404, the wood paper scale is applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) ~ -11 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 5. Description of invention (9) It is used to access the first bus 2jlq as the bus master. A w. Mm storage unit (CNF) unit cut 5 is based on P 丄; bus markers> also set pCI space and so on. For details on setting PCI space based on PCI bus specifications, see the above data sheet " DEC chip 21050 PCI-PCI Bridge Data Sheet ", fifth paragraph, pages 5-1 to 5-2 1. The PC 丨 -JCI bridge circuit 4f) also includes a second instantaneous bus arbitration (ARB) unit 406 to arbitrate the second bus acquisition request from the main device C. The device and the second bus 201 Connection; full area memory control, system (£ ^ C) unit 408 is used to control the full-body memory 411 ^ interface; an interrupt control (SIC) unit 409 is used for local 〇 «〇7〇-73 and the main CPU1 generation Interrupt signal; and a control register (REG) unit 4 07, used to set the control address for C township and STC recognition 9. The PCI-PCI bridge circuit 40 further includes a base Jg / I_O control unit 41, which is used to provide the clock signal and the reset signal from the first bus 201 to the corresponding block of the second bus and ^ 1; 1 data is temporarily reserved for the first buffer 412 for accessing the first bus 200; and the second buffer 413 is for temporarily retaining data accessed for the: 1 second bus 201. In the above configuration, when the number of one bus connected to 2JU) (such as bus memory controller 3) and the connection of the second bus 20 1 (such as control LS I 60) are equipped with an access action At this time, the auxiliary operation of the PCI-PCI bridge circuit 4α will be described below, and please refer to FIGS. 4A-4B. The 4A and 4B are details of important components in the PCI-PCI bridge circuit 40. In 圚 ii, 4J, the first purlin control unit 101 includes a decoupling S circuit ^ " i, which decodes the instantaneous cyclic received from the first interface 4 L0;-the Chinese national standard is more applicable than the paper size (CNS) Λ4 specification (210Χ 297mm), 〇 (please read the precautions on the back and then fill out this page) Installation-Order S16299 A7 Printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs Beigong Consumer Cooperative_B7 V. Invention description ( l〇) Comparator circuit for comparing the address decoded by the decoder circuit 4 ^ 50 «with the address reserved in the configuration register 405 to determine the net; 453, used to process the internal P (K1 of the LULCI bridge circuit) in the register (CNF unit 405 and REG unit 407); — GM access unit 454, used to handle access to the entire area 50 (2); and the second busbar access unit 455, used to handle access to one of the devices connected to the second busbar 201 (3). The corresponding processing unit is configured by hardware logic. The CNF unit 40¾ includes a 1/0 basic address register 456, which is used to reserve an area in a Pgi space, which is mapped by the control 4W6-register (including the device connected to the first and second bus) ; And a memory 1 base address register 4 57 for storing (: 1 space area mapped to the area Ή domain 0 secondly, the operation of the PCj-PCI bridge circuit Q will be described, and Please refer to the figure from U. When the first bus and bus access is generated from the first bus, the first interface 4 10 receives the bus access and sends the bus access to the unit 401. The path unit 401 decodes The address and commands contained in the decoder circuit 4. The decoded bits are stored in the I / O basic address register 4 56 and the configuration register The address register 45mjt is compared. Moreover, the solution is analyzed, and the hard command is used to determine the bus that is connected to it, whichever is selected in (2), Q), (3) Access. If the result of the decision is to receive the bus access. It falls in the internal "-3L register access slot 1), then the process enters the temporary 1 access unit. Scratchpad The access unit 453 outputs read / write signals to the scratchpad. CNF unit 4 〇5 Classic Please read the notes on the back i}-refill the clothing page nail line the paper thick scale is applicable to China National Standardization (CNS) A4 specifications (210X297 mm) -13 V. Description of invention (hi

A7 B7 Printed by REG unit 407 of the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy. Based on the read / write signal, the data 'is written to or read from the scratchpad. If the result of the decision shows that the received bus access falls within the access to the full area memory (2), the GM access unit 454 is performed. Output a start signal in the GM access unit 454, address in the whole area memory, and send appropriate data to the GMC unit 408 »The GMC unit 408 controls the reading / writing of the data to the whole area memory 50 based on these signals Into. If the result of the decision shows that the received bus access falls within the access to the second bus 201, the second bus access unit 455 is executed. The second bus access unit 455 outputs signals, such as signals to the SMC unit 402, addresses, data, commands, etc. At the same time, the bus access received by the first interface unit 410 is stored in the PSB unit 412. When the SMC unit 402 receives the start signal from the second bus access unit 45 5, it outputs a request signal to the ARB 406 to obtain the bus being on the second bus 201. At the same time, the SMC unit 402 gets bus access from the PSB unit 412. After the SMC unit 402 receives an allow signal output by the ARB unit 406 in response to the request signal, the output signal related to the bus cycle includes addresses, commands, etc., from the second bus 2Q1PSB unit 412 to the second The interface unit 420 generates a bus cycle on the second bus 201. The device accessing the object on the second bus 201 (e.g., the control LSI 60) decodes these signals and responds to the access. The possible types of access from the second bus 201 are access to the registers in the PCI-PCI bridge circuit 40 (4), access to the full-area memory 50 (5), and access to the first bus 2Ό0 connected device access (6) »(please read the notes on the back before filling this page)

、 1T Λ: • Γ—. This paper wave scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -14-A7 B7 Printed by the Ministry of Economic Affairs, Central Falcon Bureau Male Workers Consumer Cooperative V. Invention Description () 12 Figure 4B shows that the configuration of the ST unit 401 is similar, so the circuits of the phase Jli are represented by the same reference numbers. The following describes the operation of processing bus access from the second bus. When the bus access is from the second bus 2 01 When it is generated, the second bus interface 42 0 receives this bus access and sends it to the LC unit 420. The STC unit 403 will decode the address and command, information, and code in the decoder circuit 451. The access falls in that access U) '(5), and the results of these processes are determined according to J * to the temporary good access unit U3, the GM access unit 4_5Λ or the first-bus access list 455. Corresponding group, the processing performed is the same as the access performed by the first bus 200. In particular, if the result of the decision shows that the received bus access falls to the internal interface (4) , The register access unit 453 in the STC unit 403 outputs a read / Write the signal to the scratchpad.-Based on this read / write signal, Yuan 407 reads the data from the scratchpad; the data. If the result of the decision shows that the received bus access falls within the mjs memory access ( 5), the fetch unit 4 54 in STC, unit 403 outputs a start signal, the address of the whole area memory 50, and the appropriate WSUSL to the GMC unit 408. The GMC unit 408 controls the data to the whole area based on these signals Read and write to the memory 50. If the result of the decision shows that access to the failed bus access m I " " access to the device with the first bus channel 20.0 (6), then in the unit β 40 The bus access unit 458 outputs such as start signal, address, data, etc. to PMC Yong. 404, and stores the bus cycle received by the second interface unit 420 in the SPB unit 413. When receiving the start signal, the PMC unit 4 04 loses (please read the note on the back-install-fill in this page) The paper size of the specification is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15-A7 B7 Economy Printed by the Central Bureau of Standards of the Ministry of Industry Male Workers' Consumer Cooperative V. Description of Invention (13) A request signal is sent to A bus 200 to obtain a bus on the first bus 20_〇. Then, after receiving the number from the first public, the PMC unit 404 outputs the bus access from the SiB unit 413 ( Address, command, etc.) to the first bus 200 to generate a bus cycle in the first bus 200. The device (such as PCI device 6) that accesses the target in the first bus 200 The signal is decoded and responds to the access. In the above operation, if access is made to the main CJMI1 or any CPU in the local CPU 70-73., The SIC unit 409 executes interrupt processing. The SIC unit 409 generates an interrupt signal to the local CPU 70-73 based on the setting value in the REG unit 407. In the REG unit 407, first set the bit corresponding to the individual processor, such as the main 1, the device connected to the second bus 1, etc. When an access to each processor is detected in the comparator signal, the PTC unit 401 and the STC unit 403 set a bit corresponding to the processor requested in the REG unit 407. The SIC_unit 409 monitors the REG unit 407 and outputs a request to the processor (device) corresponding to the positioning element. After completing the interrupt processing, each processor informs the AIC unit 409 that the processing has been completely interrupted, and therefore, the result is processed. From the first bus bar joa to the whole area of the 100 million yuan ribs or connected to the second diversion bar 201 installed oxygen ϋ access, PTC unit 401 can use PSB unit 412 to perform control to achieve faster access processing, Therefore, the potential to restrict access. Especially, during the data entry period, after receiving the name, the PTC unit _401 returns a completed letter paper size when the write operation to the PSB412 unit overflows. China National Standards (CNS) A4 specification (210X297mm) (please read the item f on the back to fill in this page) (fill in too

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T 16-/ 316299 A7 B7 V. Description of the invention (No. 14 is the first bus 200, and write operation is performed on the whole area memory 50, and at the same time the device is connected to the second bus 201. On the other hand, in During the data register, in response to the first bit i requested by the data, the PCI unit 4 01-cliff 1 data, which is sent to the first ^^ row 200 g data volume, and stored in the PSB unit 412 read Fetch the data so that the data is read from the PSB unit 412, and if the addresses are consecutive in the series of loops, no read loop is generated for the relative device. This result ^ the number of times to access the read destination ms is less and Hi mm in color, so it can shorten the migration time. STCILi element 403 can also use the SI unit 413 to perform similar operations as the unit 401, so that when the second confluence 301 to the entire area of the memory 50 When accessing or accessing the device connected to the first bus 200 occurs, potential access can be restricted. As described above, the bridge of the present invention allows the computer I to configure multiple PC I buses and configure a _._ In mind_100 million body control mechanism, this machine is difficult to connect to the devices of the second PC I bus, and the configuration is low Interrupt Control Machine _Μ · ΜΜΗύι «_ι_ι _ 缹 ⑷ 丄 Fruit please fill in the notes before filling out this page. Ordered by the Ministry of Economic Affairs Central Bureau of Industry and Commerce of the Zhengong Consumer Cooperative *. This paper size is used in China Standard (CNS) A4 specification (210X297mm) 17-

Claims (1)

6. The scope of patent application Λ »BS C8 D8 Members are kindly asked to expressly mention whether the five copies of the “Ministry of Economic Affairs Central Standards Bureau® C Industrial and Consumer Cooperatives” printed on the date mentioned on the year and month ‘whether the more substantive content is allowed to be amended. Patent Application No. 8510S146 Amendments to the Chinese Patent Application Scope Amended in March 1986 1. A computer system with dual busbar configuration includes: a higher-order processing unit: a first busbar, which is used in The signal is transmitted between the first-level processing unit and the corresponding unit; a second bus bar; a device connecting the second bus bar; and _ a bus bar control circuit for interconnecting the first bus bar and the second bus bar ; And wherein the computer system also includes a full area memory connected to the control circuit between the busbars, and the control circuit between the busbars includes: a first interface for communicating signals with the first busbar;-second Interface for communicating signals with the second bus; a memory controller for controlling the whole area memory; and a control output for determining the bus received for the first interrupt target The bus cycle is an access to the device connected to the second bus or to the global memory, and based on the result of the decision, to force the controller to access the global memory or to receive the bus Bus cycle generated as the target substance, and the other generates a bus cycle of the bus as the bus master device. This paper uses the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling in this education) 6. Patent application scope 2. For example, the computer system of the first patent application scope, where The first and second bus bars are PCI bus bars. 3. A computer system as claimed in item 1 of the patent scope, wherein: the bus-to-bus control circuit includes a register for storing an address, and the address is used to access a device connected to the second bus, and Store another address, this address is used to access the whole area memory, and the control signal refers to the register to compare the address included in the bus cycle with the address stored in the register Address, and determines whether the bus cycle received for the first interface target is a device connected to the second bus or access to the global memory. 4. The computer system as claimed in item 1 of the patent scope, wherein: the inter-bus control circuit includes an interrupt control signal for controlling the interruption of each device connected to the second bus. 5. A computer system as claimed in item 4 of the patent scope, wherein: when the result of the decision indicates access to the device connected to the second bus, the control signal provides information on the interrupt control signal to specify a device in the corresponding device Device to force the interrupt control signal to perform interrupt processing. Printed by the Beigong Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) 6. A kind of busbar control circuit with a configuration, including: a first interface for The signal communicates with the first bus; a second interface is used to communicate the signal with the second bus; a control signal is used to receive the bus cycle generated on the first bus as a target, and to The bus cycle generated by the second bus is used as the bus master; and a 100-million body controller is used to control the control circuit connected to the bus. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm ). The A8 B8 C8 _ D8 printed by the Men ’s Workers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 6. The whole-area memory linked to the scope of the patent application, where the control signal determines that the bus cycle received by the first interface target is The device connected to the second bus or access to the global memory, and forcing the memory controller to access the global memory or to the second The bus device is used to generate a bus to follow the mui. Ring. 7. For example, the inter-bus control circuit in item 6 of the patent scope, where the first and second busses are PCI buses β 8. For the inter-bus control circuit in item 6 of the patent scope, a temporary A register for storing the address of the access device connected to the second bus and accessing the address of the memory of the whole area, wherein the control signal refers to the register for comparison with the bus cycle The address in and the address stored in the register, and it is determined that the bus received by the target of the first interface is cycled as a device connected to the second bus, or to the memory of the entire area access. 9. If the inter-bus control circuit of item 6 of the patent application scope further includes an interruption control circuit for controlling the interruption operation of each device connected to the second bus "10. If the patent application item 9 Inter-bus control circuit, wherein when the result of the decision indicates an access to the device connected to the second bus, the control signal provides information to the interrupt control signal to designate a device in the corresponding device to force the interrupt control The signal performs interrupt processing. 1 i. For example, the control circuit between the busbars in item 6 of the patent scope, in which the paper standard adopts the Chinese National Standard Falcon (CNS) A4 specification (210x297 public) --------- Μ --- --- IT ------ 1 (Please read the precautions on the back before filling in this page) -3-8 8 8 8 ABCD α16299 6. Patent application scope The control signal is a single crystal integrated signal. ( Please read the precautions on the back before filling in this page) 12. A kind of bus control circuit with a configuration, including a first interface for communication between the signal and the first bus; a second interface , Used to communicate the signal with the second bus;-control signal, used to receive the bus cycle generated on one bus as the target, and the bus cycle generated by another bus as the bus master Controller: and an interrupt control signal to control the interruption to each device connected to the second bus, wherein the control signal cyclically decodes the bus received from the first and second bus, and when the bus When aiming at the device connected to the second bus The signal designates a device that is the target of the bus cycle, and forces the interrupt control signal to perform interrupt processing. 1 3. The bus-to-bus control circuit as claimed in item 12 of the patent scope, where the first and second The bus is a PCI bus. Printed by the Ministry of Economic Affairs, Central Bureau of Economic and Social Affairs and Consumer Cooperatives 1 4. If the patent application scope item 12 of the bus inter-bus control circuit, it also contains a temporary storage for storing the corresponding device bit The device is connected to the second bus, wherein the bus cycle is decoded, and when the bus cycle is aimed at the device connected to the second bus, a bit set in the register corresponding to the device , And the interrupt control signal informs the device by monitoring the register. 15. If the patent application scope item; 12 of the inter-bus control circuit, it also includes a memory controller for controlling the inter-bus control The size of the circuit paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -4-A8 B8 C8 D8 ~, patent application printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs A surrounding global memory, wherein the control signal determines whether the bus cycle received by the first interface is directed to the device connected to the second bus or is access to the global memory, based on the determined As a result, the memory controller is forced to access the global memory device or generate a bus cycle for the device connected to the second bus. 16. The inter-bus control circuit of item 5 of the patent application includes The second register is used to store the access address, and the address is used to access the corresponding device connected to the second bus, and stores an address, and the address accesses the whole area memory, The control signal compares the address contained in the decoded bus cycle with the address in the second register to determine that the bus access target is a link to a second bus The device or the access to the whole area's memory. 1 7. As for the inter-busbar control circuit according to item 12 of the patent application scope, wherein the inter-busbar control circuit is a single-crystal lumped body circuit. This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm) --------- 义 ------ ITI ^ -----. Ii ^ ----- Ϊ. — (Please read the notes on the back before filling this page) 5